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Publication years (Num. hits)
1983-2002 (17) 2003-2020 (11)
Publication types (Num. hits)
article(7) inproceedings(21)
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The graphs summarize 57 occurrences of 47 keywords

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Found 28 publication records. Showing 28 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
140Ramakrishna Voorakaranam, Abhijit Chatterjee Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF analog verification, fault diagnosis, test generation, analog testing, Backtrace
120Martin Stáva, Ondrej Novák Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace
86Rajesh Ramadoss, Michael L. Bushnell Test generation for mixed-signal devices using signal flow graphs. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
74Alfred V. Gomes, Abhijit Chatterjee Robust optimization based backtrace method for analog circuits. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Kim T. Le, Kewal K. Saluja A Heuristic Measure to Maximize Detected Faults per Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF combinational circuit testing, dynamic test compaction, fault selection, test generation, testability measures, backtrace
47Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal An efficient automatic test generation system for path delay faults in combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
40Rajesh Ramadoss, Michael L. Bushnell Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
40Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang Computation of floating mode delay in combinational circuits: practice and implementation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
34Jingling Zhao, Congxiang Yu, Yunze Ni A Universal Defense System Based on Backtrace Canary for ELF Against Vulnerabilities. Search on Bibsonomy AINA The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
34Lee Aaron Newberg Memory-efficient dynamic programming backtrace and pairwise local sequence alignment. Search on Bibsonomy Bioinform. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Martin Stáva, Ondrej Novák HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. Search on Bibsonomy DDECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Chao Liu 0001, Xifeng Yan, Hwanjo Yu, Jiawei Han 0001, Philip S. Yu Mining Behavior Graphs for "Backtrace" of Noncrashing Bugs. Search on Bibsonomy SDM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Andrei Mekler, Jaan Raik Multiple-objective backtrace for solving test generation constraints. Search on Bibsonomy SoC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Antonio Lioy Adaptative backtrace and dynamic partitioning enhance ATPG. Search on Bibsonomy ICCD The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
27Dong Shi, Xinming Zhang 0001, Wenbo Zhu, Enbo Wang RCDS: A Ranking-Based Algorithm to Compute the CDS of the Ad Hoc Networks. Search on Bibsonomy NCM (1) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ad hoc networks, broadcast, connected dominating set, backtrace
27Hideo Fujiwara, Takeshi Shimono On the Acceleration of Test Generation Algorithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults
20Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman Parallel fault backtracing for calculation of fault coverage. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
20Jing Yang 0003, Mary Lou Soffa, Leo Selavo, Kamin Whitehouse Clairvoyant: a comprehensive source-level debugger for wireless sensor networks. Search on Bibsonomy SenSys The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded debugging, wireless sensor networks, distributed debugging, source-level debugging
20Andrew M. Cheadle, A. J. Field, J. W. Ayres, Neil Dunn, Richard A. Hayden, Johan Nyström-Persson Visualising dynamic memory allocators. Search on Bibsonomy ISMM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF visualisation of objects, garbage collection, memory management, dynamic memory allocation, language implementation
20Hanhua Chen, Hai Jin 0001 Identifying Community Structure in Semantic Peer-to-Peer Networks. Search on Bibsonomy SKG The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Wojciech Bozejko, Mieczyslaw Wodecki Solving the Flow Shop Problem by Parallel Tabu Search. Search on Bibsonomy PARELEC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
20Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
20M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff A New Test Generation Approach for Embedded Analogue Cores in SoC. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
20Ramakrishna Voorakaranam, Abhijit Chatterjee Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
20Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min Memory Efficient ATPG for Path Delay Faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization
20Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler A hierarchical test pattern generation system based on high-level primitives. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
20Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert SOCRATES: a highly efficient automatic test pattern generation system. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
20M. Ladjadj, John F. McDonald 0001 Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
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