Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
65 | Himanshu Kaul, Jae-sun Seo, Mark A. Anders 0001, Dennis Sylvester, Ram Krishnamurthy 0001 |
A robust alternate repeater technique for high performance busses in the multi-core era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 372-375, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Ketan N. Patel, Igor L. Markov |
Error-correction and crosstalk avoidance in DSM busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 9-14, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DSM busses, error-correction, crosstalk noise, bus encoding |
52 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 861-864, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten |
Routing of analog busses with parasitic symmetry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 14-19, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout |
52 | L. Di Silvio, Daniele Rossi 0001, Cecilia Metra |
Crosstalk Effect Minimization for Encoded Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 214-218, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
52 | Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano |
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 77-82, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Baher Haroun, Behzad Sajjadi |
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 75-81, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
52 | Friedhelm Meyer auf der Heide, Hieu Thien Pham |
On the Performance of Networks with Multiple Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 92, 9th Annual Symposium on Theoretical Aspects of Computer Science, Cachan, France, February 13-15, 1992, Proceedings, pp. 97-108, 1992, Springer, 3-540-55210-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
51 | Nick A. Mould, Brian F. Veale, John K. Antonio, Monte P. Tull, John R. Junger |
Design of steering vectors for dynamically reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet |
Implementing Snoop-Coherence Protocol for Future SMP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 745-752, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Paul Metzgen, Dominic Nancekievill |
Multiplexer restructuring for FPGA implementation cost reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 421-426, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
busses, recoding, FPGA, synthesis, multiplexers, restructuring, logic optimization |
42 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Achievable bounds on signal transition activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 126-129, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
achievable bounds, busses, Low power, information theory, power estimation, CMOS circuits, switching activity |
42 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
39 | Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra |
Power Consumption of Fault Tolerant Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 542-553, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten |
Algorithms for automatic length compensation of busses in analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 159-166, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout |
39 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 624-633, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Bassel Soudan |
Reducing Inductive Coupling Skew in Wide Global Signal Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 223-226, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | André K. Nieuwland, Atul Katoch, Daniele Rossi 0001, Cecilia Metra |
Coding Techniques for Low Switching Noise in Fault Tolerant Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 183-189, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow |
Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 190-196, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi |
Power Comparison of Throughput Optimized IC Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 35-44, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Helge Scheidig, M. F. Schneider, R. Spurk |
Efficient and Scalable Logic Busses for Message-Passing Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDMCC ![In: Distributed Memory Computing, 2nd European Conference, EDMCC2, Munich, FRG, April 22-24, 1991, Proceedings, pp. 183-192, 1991, Springer, 3-540-53951-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
38 | Ahmed Elkammar, Norman Scheinberg, Srinivasa Vemuru |
Bus Encoding Scheme To Eliminate Unwanted Signal Transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 472-480, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Håvard Kolle Riis, Philipp Häfliger |
An Asynchronous 4-to-4 AER Mapper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational Intelligence and Bioinspired Systems, 8th International Work-Conference on Artificial Neural Networks, IWANN 2005, Vilanova i la Geltrú, Barcelona, Spain, June 8-10, 2005, Proceedings, pp. 494-501, 2005, Springer, 3-540-26208-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Marek Tudruj, Lukasz Masko |
A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 4th International Conference, PPAM 2001 Naleczow, Poland, September 9-12, 2001, Revised Papers, pp. 51-64, 2001, Springer, 3-540-43792-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet |
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 22-29, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Bandwidth requirement, SMP architecture, optical bus, shared bus |
38 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Extensions to Programmable DSP architectures for Reduced Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 37-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Low Power Design, DSP Architecture |
38 | Friedhelm Meyer auf der Heide, Klaus Schröder, Frank Schwarze |
Routing on Networks of Optical Crossbars (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. I ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume I, pp. 299-306, 1996, Springer, 3-540-61626-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Luca Muratori, Lorenzo Peretto, Beatrice Pulvirenti, Raffaella Di Sante, Giovanni Bottiglieri, Federico Coiro |
A vehicle integrated thermal management system for electric busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MetroAutomotive ![In: IEEE International Workshop on Metrology for Automotive, MetroAutomotive 2022, Modena, Italy, July 4-6, 2022, pp. 139-144, 2022, IEEE, 978-1-6654-6689-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Markus Linnartz, Yasmin Dufner, Nicola Fricke |
Information Presentation in Autonomous Shuttle Busses: -What and How? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ArtsIT ![In: ArtsIT, Interactivity and Game Creation - Creative Heritage. New Perspectives from Media Arts and Artificial Intelligence. 10th EAI International Conference, ArtsIT 2021, Virtual Event, December 2-3, 2021, Proceedings, pp. 413-423, 2021, Springer, 978-3-030-95530-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Ubaid Mehmood, Irene Moser, Prem Prakash Jayaraman, Abhik Banerjee |
Occupancy Estimation using WiFi: A Case Study for Counting Passengers on Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WF-IoT ![In: 5th IEEE World Forum on Internet of Things, WF-IoT 2019, Limerick, Ireland, April 15-18, 2019, pp. 165-170, 2019, IEEE, 978-1-5386-4980-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Guilherme Valle Loures Brandão, Wilian Daniel Henriques do Amaral, Caio Augusto Rabite de Almeida, Jose Alberto Barroso Castañon |
Simplified Thermal Comfort Evaluation on Public Busses for Performance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (20) ![In: Design, User Experience, and Usability: Understanding Users and Contexts - 6th International Conference, DUXU 2017, Held as Part of HCI International 2017, Vancouver, BC, Canada, July 9-14, 2017, Proceedings, Part III, pp. 581-593, 2017, Springer, 978-3-319-58639-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
27 | Melike Erdogan, Ihsan Kaya |
Evaluating Alternative-Fuel Busses for Public Transportation in Istanbul Using Interval Type-2 Fuzzy AHP and TOPSIS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Multiple Valued Log. Soft Comput. ![In: J. Multiple Valued Log. Soft Comput. 26(6), pp. 625-642, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
27 | Sebastian Wagner, Gunter Nitzsche |
Advanced steer-by-wire system for worlds longest busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITSC ![In: 19th IEEE International Conference on Intelligent Transportation Systems, ITSC 2016, Rio de Janeiro, Brazil, November 1-4, 2016, pp. 1932-1938, 2016, IEEE, 978-1-5090-1889-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Francesco Biral, Marco Galvani, Michele Zucchelli, Giuliano Giacomelli |
Objective performance evaluation on mountain routes of diesel-electric hybrid busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: IEEE International Conference on Mechatronics, ICM 2013, Vicenza, VI, Italy, February 27 - March 1, 2013, pp. 394-399, 2013, IEEE, 978-1-4673-1386-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Bassel Soudan |
The effect of SRNR on timing characteristics of signal busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 639-645, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Bassel Soudan |
Reducing signal timing variations in inter-core busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 43(2), pp. 237-249, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli |
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 18th European Conference on Circuit Theory and Design, ECCTD 2007, Seville, Spain, August 26-30, 2007, pp. 368-371, 2007, IEEE, 978-1-4244-1341-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rolf Ernst, Gernot Spiegelberg, Thomas Weber 0002, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marek Jersak |
Automotive networks: are new busses and gateways the answer or just another challenge? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 263, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
automotive networks |
27 | Ketan N. Patel, Igor L. Markov |
Error-correction and crosstalk avoidance in DSM busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1076-1080, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Bassel Soudan |
Managing inductive coupling in wide signal busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 537-40, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
27 | Daniele Rossi 0001, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra |
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 135-140, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Bassel Soudan |
Reducing mutual inductance of wide signal busses through swizzling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003, pp. 870-873, 2003, IEEE, 0-7803-8163-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Abdelkader El Kamel, Jean-Yves Dieulot, Pierre Borne |
Fuzzy controller for lateral guidance of busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIC ![In: Proceedings of the 2002 IEEE International Symposium on Intelligent Control, ISIC 2002, Vancouver, BC, Canada, October 27-30, 2002, pp. 110-115, 2002, IEEE, 0-7803-7620-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | William J. Buchanan |
Computer busses - design and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2000 |
RDF |
|
27 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
A coding framework for low-power address and data busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(2), pp. 212-221, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 18-23, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Windsor W. Hsu, Jih-Kwon Peir |
Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The Computer Science and Engineering Handbook ![In: The Computer Science and Engineering Handbook, pp. 427-446, 1997, CRC Press, 0-8493-2909-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
27 | Alberto Aloisio, S. Cavaliere, F. Cevenini, L. Merola, D. J. Fiore |
Custom busses for large scale data acquisition systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996, pp. 1155-1161, 1996, IEEE, 0-7803-3650-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Shlomo Kipnis |
Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(4), pp. 484-489, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Mary L. Bailey, Michael A. Pagels, Kachung Kevin Wong |
How using busses in multicomputer programs affects conservative parallel simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADS ![In: Proceedings of the Seventh Workshop on Parallel and Distributed Simulation, PADS 1993, San Diego, California, USA, May 16-19, 1993, pp. 93-100, 1993, ACM, 978-1-56555-055-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Roger B. Hughes, M. D. Francis, Simon Finn, Gerry Musgrave |
Formal Tools in Tri-State Design in Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and its Applications, Proceedings of the IFIP TC10/WG10.2 Workshop HOL'92, Leuven, Belgium, 21-24 September 1992, pp. 459-475, 1992, North-Holland/Elsevier, 0-444-89880-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
27 | Shlomo Kipnis |
Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 401-406, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
27 | Christian Ewering |
A New Allocation Method for the Synthesis of Partitioned Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme ![In: Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, GME/GI/ITG-Fachtagung, Dortmund, Oktober 1990, Proceedings, pp. 115-129, 1990, Springer, 3-540-53163-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
27 | K. Braun, Erwin M. Thurner |
Designüberlegegungen und Konzept eines konfigurierbaren lokalen Busses für Spezialprozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architektur von Rechensystemen, Tagungsband, 11. ITG/GI-Fachtagung, 7.-9. März 1990, München, Germany, pp. 59-69, 1990, VDE Verlag, 3-8007-1688-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
27 | Christian Ewering |
Automatic High Level Syntesis of Partitioned Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 304-307, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
27 | Zicheng Guo, Rami G. Melhem |
Embedding pyramids in array processors with pipelined busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990, pp. 665-676, 1990, IEEE, 0-8186-9089-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
27 | D. Simon |
Finding the Trap Door Through Patent Protection of Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29 - March 4, 1988, pp. 376-381, 1988, IEEE Computer Society, 0-8186-0828-5. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
25 | Sudeep Pasricha, Nikil D. Dutt |
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 700-705, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton |
GreenBus: a generic interconnect fabric for transaction level modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 905-910, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC, SystemC, TLM, on-chip communication |
25 | Brock J. LaMeres, Sunil P. Khatri |
Performance model for inter-chip communication considering inductive cross-talk and cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4130-4133, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Atul Katoch, Harry J. M. Veendrick, Evert Seevinck |
High speed current-mode signaling circuits for on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4138-4141, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson |
Tester Architecture For The Source Synchronous Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 738-747, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Marek Tudruj, Lukasz Masko |
Program Execution Control for Communication on the Fly in Dynamic Shared Memory Processor Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland, pp. 15-20, 2002, IEEE Computer Society, 0-7695-1730-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi |
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 14-19, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | David J. Greaves |
A Verilog to C Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 122-127, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Vijay Sundararajan, Keshab K. Parhi |
Reducing bus transition activity by limited weight coding with codeword slimming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 13-16, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Michael Mock, Edgar Nett |
Real-Time Communication in Autonomous Robot Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISADS ![In: The Fourth International Symposium on Autonomous Decentralized Systems, ISADS 1999, Tokyo, Japan, March 20-23, 1999, pp. 34-41, 1999, IEEE Computer Society, 0-7695-0137-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiple-access bus, TDMA, control system, real-time communication, robotic system |
25 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi |
Interconnect Diagnosis of Bus-Connected Multi-RAM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 40-47, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Ingrid Verbauwhede, Mihran Touriguian |
A Low Power DSP Engine for Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(2), pp. 177-186, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Robert W. Horst |
TNet: A Reliable System Area Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 15(1), pp. 37-45, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
TNet, routing, reliability, multiprocessor, wormhole routing, multistage interconnect network, flow control, I/O, system area network, massively parallel processing, IPC |
13 | Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001 |
A path-load based adaptive routing algorithm for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
quality of service, networks on chip, dynamic routing, traffic monitoring |
13 | Gunar Schirner, Rainer Dömer |
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(1), pp. 4:1-4:29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
system-on-chip, System level design, transaction level modeling |
13 | Chunjie Duan, Sunil P. Khatri |
Energy Efficient and High Speed On-Chip Ternary Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 515-518, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich |
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings, pp. 117-129, 2008, Springer, 978-3-540-78152-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Marcel Nassar, Kapil Gulati, Arvind K. Sujeeth, Navid Aghasadeghi, Brian L. Evans, Keith R. Tinsley |
Mitigating near-field interference in laptop embedded wireless transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 1405-1408, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman |
An Extensible I/O Subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 269-270, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Fahimeh Jafari, Mohammad Hossien Yaghmaee, Mohammad Sadegh Talebi, Ahmad Khonsari |
Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (1) ![In: Computational Science - ICCS 2008, 8th International Conference, Kraków, Poland, June 23-25, 2008, Proceedings, Part I, pp. 436-445, 2008, Springer, 978-3-540-69383-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Network-on-Chip, flow control, Max-Min fairness |
13 | Abhisek Pan, James W. Tschanz, Sandip Kundu |
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 343-351, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals |
A High-Speed Optical Multi-Drop Bus for Computer Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 3-10, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus |
13 | Kelly D. Larson |
Translation of an existing VMM-based SystemVerilog testbench to OVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 237, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
OVM, VMM, testbenches, SystemVerilog |
13 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8), pp. 1454-1464, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger |
Implementation and Evaluation of a Dynamically Routed Processor Operand Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 7-17, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | W. Mack Grady, Mehrdad Vatani, Ari Arapostathis |
A new fault location method for electric power grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSC ![In: Proceedings of the 2007 Summer Computer Simulation Conference, SCSC 2007, San Diego, California, USA, July 16-19, 2007, pp. 63-69, 2007, Simulation Councils, Inc., 1-56555-316-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
electric power grids, voltage sags, fault location |
13 | Marieka Hoedemaeker, Mark A. Neerincx |
Attuning In-Car User Interfaces to the Momentary Cognitive Load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (16) ![In: Foundations of Augmented Cognition, Third International Conference, FAC 2007, Held as Part of HCI International 2007, Beijing, China, July 22-27, 2007, Proceedings, pp. 286-293, 2007, Springer, 978-3-540-73215-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
In-car services, central management, workload, adaptive user interface |
13 | Dimitrios N. Serpanos, Wayne H. Wolf |
VLSI models of network-on-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 72-77, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto |
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 660-665, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Bradley R. Quinton, Steven J. E. Wilton |
Embedded Programmable Logic Core Enhancements for System Bus Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 202-209, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat |
NoC Implementation in FPGA Using Torus Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 778-781, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han |
Performance modeling for early analysis of multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 209-214, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling |
13 | Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy 0001 |
A robust edge encoding technique for energy-efficient multi-cycle interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 68-73, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-cycle interconnect, interconnect, encoding, repeaters |
13 | Lochi Yu, Samar Abdi |
Automatic SystemC TLM generation for custom communication platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 41-46, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari, Mohammad Hossien Yaghmaee |
A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings. Part III, pp. 398-409, 2007, Springer, 978-3-540-74482-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Werner Hein, Jens Berkmann, Manfred Zimmermann, Mario Huemer |
Object Oriented Signal Data Structures in VLSI Implementations of Wireless Modems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2007, 11th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 12-16, 2007, Revised Selected Papers, pp. 936-943, 2007, Springer, 978-3-540-75866-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Marek Tudruj, Lukasz Masko |
Parallel Matrix Multiplication Based on Dynamic SMP Clusters in SoC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking ISPA 2007 Workshops, ISPA 2007 International Workshops SSDSN, UPWN, WISH, SGC, ParDMCom, HiPCoMB, and IST-AWSN Niagara Falls, Canada, August 28 - September 1, 2007, Proceedings, pp. 375-385, 2007, Springer, 978-3-540-74766-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Patrick Leteinturier |
Automotive semi-conductor trend & challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 559, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Brock J. LaMeres, Sunil P. Khatri |
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 522-527, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski |
A Graph Based Algorithm for Data Path Optimization in Custom Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 496-503, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
Constraint-driven bus matrix synthesis for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 30-35, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Peter Sobe, Kathrin Peter |
Construction of efficient OR-based deletion - tolerant coding schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Lukasz Masko, Gregory Mounie, Denis Trystram, Marek Tudruj |
Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland, pp. 95-100, 2006, IEEE Computer Society, 0-7695-2554-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|