Search results for "cache-coherent"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	Yang Zeng, Santosh G. Abraham	Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	partitioning regular grid applications, irregular boundaries, cache-coherent multiprocessors, regular grid, domain decomposition techniques, message passing multiprocessors, false coherency traffic, cache line, coalescing algorithm, domain decomposition algorithm, Indian Ocean circulation application, KSR1 multiprocessor, coherency traffic, message passing, multiprocessing systems, interprocessor communication
52	Maged M. Michael, Ashwini K. Nanda	Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
51	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
49	Zheng Zhang 0001, Josep Torrellas	Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA.	HPCA	1997	DBLP DOI BibTeX RDF	remote conflict miss, NUMA with Remote Cache, shared-memory multiprocessor, cache coherent, COMA
48	Steven Cameron Woo, Jaswinder Pal Singh, John L. Hennessy	The Performance Advantages of Integrating Block Data Trabsfer in Cache-Coherent Multiprocessors.	ASPLOS	1994	DBLP DOI BibTeX RDF
45	Sung-Eui Yoon, Peter Lindstrom 0001	Random-Accessible Compressed Triangle Meshes.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	cache-coherent layouts, mesh data structures, random access, external memory algorithms, Mesh compression
41	Jonas Skeppstedt, Michel Dubois 0001	Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps.	ICPP	1997	DBLP DOI BibTeX RDF	hybrid compiler/hardware prefetching, low-overhead cache miss traps, data prefetching technique, cache coherent multiprocessors, cache miss traps, trap handler, simulated multiprocessor, compiler, multiprocessors, multiprocessing systems
41	Karen A. Tomko, Santosh G. Abraham	Data and program restructuring of irregular applications for cache-coherent multiprocessor.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
41	Philippas Tsigas, Yi Zhang 0004	Evaluating the performance of non-blocking synchronization on shared-memory multiprocessors.	SIGMETRICS/Performance	2001	DBLP DOI BibTeX RDF
41	Farnaz Mounes-Toussi, David J. Lilja	Write buffer design for cache-coherent shared-memory multiprocessors.	ICCD	1995	DBLP DOI BibTeX RDF	write-buffer configurations, one word per buffer entry, one block per buffer entry, write-through, write-back, competitive-performance, shared-memory multiprocessors, shared memory systems, cache-coherent, memory architecture, buffer storage, cache storage, execution-driven simulator, write policies
41	Ashwini K. Nanda, Laxmi N. Bhuyan	Design and Analysis of Cache Coherent Multistage Interconnection Networks.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	cache coherent multistage interconnection networks, multiple copy cache coherence protocol, multistage bus network, coherence traffic, performance evaluation, protocols, multiprocessor interconnection networks, simulation models
40	Sangman Moh, Jae-Hong Shim, Yang-Dong Lee, Jeong-A Lee, Beom-Joon Cho	Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net.	ISCIS	2003	DBLP DOI BibTeX RDF
40	John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta	Memory System Performance of UNIX on CC-NUMA Multiprocessors.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
38	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems.	ICPADS	2007	DBLP DOI BibTeX RDF
38	Doug Burger, David A. Wood 0001	Accuracy vs. performance in parallel simulation of interconnection networks.	IPPS	1995	DBLP DOI BibTeX RDF	Wisconsin Wind Tunnel, cache-coherent shared-memory machines, network simulation models, high network loads, nonuniform traffic patterns, performance evaluation, performance, parallel computers, interconnection networks, parallel architectures, virtual machines, multiprocessor interconnection networks, accuracy, shared memory systems, parallel simulation, parallel applications, cache-coherence protocols, network contention
35	Andrea Marongiu, Luca Benini, Mahmut T. Kandemir	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.	CASES	2007	DBLP DOI BibTeX RDF	code parallelization, MPSoCs, barrier synchronization
35	Jim Nilsson, Fredrik Dahlgren	Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors.	IPDPS	2000	DBLP DOI BibTeX RDF
35	Phillip B. Gibbons, Ephraim Korach	On Testing Cache-Coherent Shared Memories.	SPAA	1994	DBLP DOI BibTeX RDF
34	Christopher Connelly, Carla Schlatter Ellis	A workload characterization for coarse-grain multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	coarse-grain multiprocessors, associated coherency maintenance, memory blocks, cache-coherent multiprocessors, page-based distributed shared memory systems, fine-grain systems, performance evaluation, performance, scalability, replication, multiprocessing systems, workload characterization, granularity, scalable shared memory multiprocessors
33	Abderahman Kriouile	Formal Methods for Functional Verification of Cache-Coherent System-on-Chip. (Méthodes Formelles pour la vérification fonctionnelle des systèmes sur puce cache cohérent).		2015	RDF
33	Sang-Hwa Chung, Soo-Cheol Oh	An SCI-Based PC Cluster Utilizing Coherent Network Cache.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	network cache, cluster system, CC-NUMA, SCI
30	Yunheung Paek, Angeles G. Navarro, Emilio L. Zapata, Jay P. Hoeflinger, David A. Padua	An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	array privatization, noncoherent caches, Put/Get, compiler, multiprocessors, dependence analysis, shared-memory programming
29	Dongming Jiang, Hongzhang Shan, Jaswinder Pal Singh	Application Restructuring and Performance Portability on Shared Virtual Memory and Hardware-Coherent Multiprocessors.	PPoPP	1997	DBLP DOI BibTeX RDF
29	Rohan Samarasinghe, Yoshihiro Yasutake, Takaichi Yoshida	Optimizing the Access Performance and Data Freshness of Distributed Cache Objects Considering User Access Pattern.	AINA	2005	DBLP DOI BibTeX RDF
29	John P. Sustersic, Ali R. Hurson	A Quality of Service (QoS) Implementation of Internet Cache Coherence.	AINA (1)	2004	DBLP DOI BibTeX RDF
29	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
29	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
29	Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura	An Optical Bus Computer Cluster with a deferred cache coherence protocol.	ICPADS	1996	DBLP DOI BibTeX RDF	Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
28	Chris Holt, Jaswinder Pal Singh, John L. Hennessy	Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory Machines.	ISCA	1996	DBLP DOI BibTeX RDF
26	Albert Meixner, Daniel J. Sorin	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
26	Albert Meixner, Daniel J. Sorin	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.	DSN	2006	DBLP DOI BibTeX RDF
26	Hyonho Lee	Transformations of Mutual Exclusion Algorithms from the Cache-Coherent Model to the Distributed Shared Memory Model.	ICDCS	2005	DBLP DOI BibTeX RDF
26	Masaru Takesue	A Model of Pipelined Mutual Exclusion on Cache-Coherent Multiprocessors.	Euro-Par	2003	DBLP DOI BibTeX RDF	Models, pipelining, mutual exclusion
26	Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou	Fast Synchronization on Scalable Cache-Coherent Multiprocessors using Hybrid Primitives.	IPDPS	2000	DBLP DOI BibTeX RDF	performance evaluation, synchronization, shared-memory, cache-coherence, scalable architectures
26	Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi	Temporal Streaming of Shared Memory.	ISCA	2005	DBLP DOI BibTeX RDF
25	Christian Fensch, Marcelo Cintra	An OS-based alternative to full hardware coherence on tiled CMPs.	HPCA	2008	DBLP DOI BibTeX RDF
25	Wanxia Qu, Yang Guo 0003, Zhengbin Pang, Xiaodong Yang	Efficient Verification of Parameterized Cache Coherence Protocols.	ICYCS	2008	DBLP DOI BibTeX RDF
25	Qiong Li, Zhengbin Pang, Yufeng Guo, Enqiang Zhou, Xuejun Yang	A GPDMA-based Distributed Shared I/O Solution for CC-NUMA System.	ICYCS	2008	DBLP DOI BibTeX RDF
25	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.	MICRO	2002	DBLP DOI BibTeX RDF
24	Tae-Joon Kim, Bochang Moon, Duksu Kim, Sung-Eui Yoon	RACBVHs: Random-Accessible Compressed Bounding Volume Hierarchies.	IEEE Trans. Vis. Comput. Graph.	2010	DBLP DOI BibTeX RDF	Hierarchy and BVH compression, cache-coherent layouts, ray tracing, collision detection, random access
24	Ruibo Wang	Investigating Software Transactional Memory on Big SMP Machines.	SNPD	2009	DBLP DOI BibTeX RDF	Software Transactional Memory (STM), cache coherent Non-Uniform Memory Access (ccNUMA), Scalability
24	Steffen Christgau	One-sided communication on a non-cache-coherent many-core architecture (Einseitige Kommunikation auf einer nicht-cache-kohärenten Vielkern-Prozessorarchitektur) (PDF / PS)		2017	RDF
24	Sabela Ramos, Torsten Hoefler	Cache Line Aware Algorithm Design for Cache-Coherent Architectures.	IEEE Trans. Parallel Distributed Syst.	2016	DBLP DOI BibTeX RDF
24	Alberto Ros 0001, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato	Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems.	ISPA	2012	DBLP DOI BibTeX RDF
24	Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson	Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	high-bandwidth interconnects, distributed shared memory, parallel systems, clusters of workstations, low-latency
24	Courtney R. Gibson, Angelos Bilas	Shared Virtual Memory Clusters with Next-Generation Interconnection Networks and Wide Compute Nodes.	HiPC	2001	DBLP DOI BibTeX RDF
24	Dongming Jiang, Jaswinder Pal Singh	A Methodology and an Evaluation of the SGI Origin2000.	SIGMETRICS	1998	DBLP DOI BibTeX RDF
24	Tom Lovett, Russell M. Clapp	STiNG: A CC-NUMA Computer System for the Commercial Marketplace.	ISCA	1996	DBLP DOI BibTeX RDF
22	Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima	Verification of an Industrial CC-NUMA Server.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
22	Lory D. Molesky, Krithi Ramamritham	Recovery Protocols for Shared Memory Database Systems.	SIGMOD Conference	1995	DBLP DOI BibTeX RDF
22	Rohit Chandra, Scott Devine, Ben Verghese, Anoop Gupta, Mendel Rosenblum	Scheduling and Page Migration for Multiprocessor Compute Servers.	ASPLOS	1994	DBLP DOI BibTeX RDF
21	Mirko Loghi, Massimo Poncino, Luca Benini	Cache coherence tradeoffs in shared-memory MPSoCs.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip, Cache coherence
21	Mirko Loghi, Massimo Poncino	Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.	DATE	2005	DBLP DOI BibTeX RDF
21	Anant Agarwal, David A. Kranz, Rajeev Barua, Venkat Natarajan	Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors.	Compiler Optimizations for Scalable Parallel Systems Languages	2001	DBLP DOI BibTeX RDF
21	Jinseok Kong, Gyungho Lee	Relaxing the Inclusion Property in Cache Only Memory Architecture.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
21	Ben Verghese, Scott Devine, Anoop Gupta, Mendel Rosenblum	Operating System Support for Improving Data Locality on CC-NUMA Compute Servers.	ASPLOS	1996	DBLP DOI BibTeX RDF
21	Mats Brorsson	SM-prof: A Tool to Visualise and Find Cache Coherence Performance Bottlenecks in Multiprocessor Programs.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
21	Gyungho Lee	An assessment of COMA multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
21	Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, David A. Wood 0001	The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers.	SIGMETRICS	1993	DBLP DOI BibTeX RDF
20	Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi	Store-Ordered Streaming of Shared Memory.	IEEE PACT	2005	DBLP DOI BibTeX RDF
20	Angelos Bilas, Dongming Jiang, Jaswinder Pal Singh	Accelerating shared virtual memory via general-purpose network interface support.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	clusters, applications, system area networks, shared virtual memory
19	Robert L. Bocchino Jr., Vikram S. Adve, Bradford L. Chamberlain	Software transactional memory for large scale clusters.	PPoPP	2008	DBLP DOI BibTeX RDF	clusters, scalability, software transactional memory (stm), distributed memory architectures
17	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
17	Xiaogang Qiu, Michel Dubois 0001	Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
17	Gary Gostin, Jean-Francois Collard, Kirby Collins	The architecture of the HP Superdome shared-memory multiprocessor.	ICS	2005	DBLP DOI BibTeX RDF
17	Jaydeep Marathe, Anita Nagarajan, Frank Mueller 0001	Detailed cache coherence characterization for OpenMP benchmarks.	ICS	2004	DBLP DOI BibTeX RDF	SMPs, program instrumentation, coherence protocols, cache analysis, dynamic binary rewriting
17	Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration.	HPCA	2000	DBLP DOI BibTeX RDF	directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
17	Kazuki Joe, Akira Fukuda	Applying the Semi-Markov Memory and Cache Coherence Interference Model to an Updating Based Cache Coherence Protocol.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
17	Margaret Martonosi, David Ofelt, Mark A. Heinrich	Integrating Performance Monitoring and Communication in Parallel Computers.	SIGMETRICS	1996	DBLP DOI BibTeX RDF
17	Mazin S. Yousif, Chita R. Das	A Switch Cache Design for MIN-Based Shared-Memory Multiprocessors.	CONPAR	1994	DBLP DOI BibTeX RDF
17	Jonas Skeppstedt, Per Stenström	Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols.	ASPLOS	1994	DBLP DOI BibTeX RDF
17	Ioannis Schoinas, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, James R. Larus, David A. Wood 0001	Fine-grain Access Control for Distributed Shared Memory.	ASPLOS	1994	DBLP DOI BibTeX RDF
16	Henry N. Schuh, Arvind Krishnamurthy, David E. Culler, Henry M. Levy, Luigi Rizzo, Samira Manabi Khan, Brent E. Stephens	CC-NIC: a Cache-Coherent Interface to the NIC.	ASPLOS (1)	2024	DBLP DOI BibTeX RDF
16	Hyokeun Lee, Kwanseok Choi, Hyuk-Jae Lee, Jaewoong Sim	SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link.	PACT	2023	DBLP DOI BibTeX RDF
16	Fei Gao 0016, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu 0001, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff	DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.	CICC	2023	DBLP DOI BibTeX RDF
16	Daecheol You, Jae Min Kim, Taesung Kim, Junho Huh	Automotive Multi-Chip System with Cache Coherent Interconnect for Pipelined Parallel Applications.	ICCE	2023	DBLP DOI BibTeX RDF
16	Yuxin Ren 0001, Gabriel Parmer, Dejan S. Milojicic	Sharing non-cache-coherent memory with bounded incoherence.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
16	Chen Ding 0001, Benjamin Reber, Dorin Patru	Cache-coherent CLAM (WIP).	LCTES	2022	DBLP DOI BibTeX RDF
16	Zixuan Wang, Joonseop Sim, Euicheol Lim, Jishen Zhao	Enabling Efficient Large-Scale Deep Learning Training with Cache Coherent Disaggregated Memory Systems.	HPCA	2022	DBLP DOI BibTeX RDF
16	Sajjad Tamimi, Florian Stock, Andreas Koch 0001, Arthur Bernhardt, Ilia Petrov 0001	An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing.	FCCM	2022	DBLP DOI BibTeX RDF
16	Ankit Bhardwaj, Todd Thornley, Vinita Pawar, Reto Achermann, Gerd Zellweger, Ryan Stutsman	Cache-coherent accelerators for persistent memory crash consistency.	HotStorage	2022	DBLP DOI BibTeX RDF
16	Arthur Bernhardt, Sajjad Tamimi, Florian Stock, Tobias Vinçon, Andreas Koch 0001, Ilia Petrov 0001	Cache-Coherent Shared Locking for Transactionally Consistent Updates in Near-Data Processing DBMS on Smart Storage.	EDBT	2022	DBLP DOI BibTeX RDF
16	Isaac Sánchez Barrera	Exploiting data locality in cache-coherent NUMA systems.		2022	RDF
16	Georgios Kornaros	RSMCC: Enabling Ring-based Software Managed Cache-Coherent Embedded SoCs.	PDP	2020	DBLP DOI BibTeX RDF
16	Ho-Ren Chuang, Robert Lyerly, Stefan Lankes, Binoy Ravindran	Scaling Shared Memory Multiprocessing Applications in Non-cache-coherent Domains.	SYSTOR	2020	DBLP DOI BibTeX RDF
16	Yuxin Ren 0001, Gabriel Parmer, Dejan S. Milojicic	Bounded incoherence: a programming model for non-cache-coherent shared memory architectures.	PMAM@PPoPP	2020	DBLP DOI BibTeX RDF
16	Moyang Wang, Tuan Ta, Lin Cheng, Christopher Batten	Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems.	ISCA	2020	DBLP DOI BibTeX RDF
16	Suk Chan Kang	Optimizing high locality memory references in cache coherent shared memory multi-core processors.		2020	RDF
16	Alexander Kroh, Oliver Diessel	Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
16	Junchang Wang, Qi Jin, Xiong Fu, Yun Li 0009, Peichang Shi	Accelerating Wait-Free Algorithms: Pragmatic Solutions on Cache-Coherent Multicore Architectures.	IEEE Access	2019	DBLP DOI BibTeX RDF
16	Tamer Ahmed Eltaras, William Fornaciari, Davide Zoni	Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs.	PDP	2019	DBLP DOI BibTeX RDF
16	Paul N. Whatmough, Sae Kyu Lee, Marco Donato, Hsea-Ching Hsueh, Sam Likun Xi, Udit Gupta, Lillian Pentecost, Glenn G. Ko, David M. Brooks, Gu-Yeon Wei	A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
16	Paolo Grani, Sandro Bartolini	Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs.	ACM J. Emerg. Technol. Comput. Syst.	2018	DBLP DOI BibTeX RDF
16	Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet	A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.	ESSCIRC	2018	DBLP DOI BibTeX RDF
16	Steffen Christgau, Bettina Schnor	Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture.	Concurr. Comput. Pract. Exp.	2017	DBLP DOI BibTeX RDF
16	Ricardo Fernández Pascual, Alberto Ros 0001, Manuel E. Acacio	To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.	J. Supercomput.	2017	DBLP DOI BibTeX RDF
16	Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu	A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications.	ISORC	2017	DBLP DOI BibTeX RDF
16	Manuel Mohr, Carsten Tradowsky	Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores.	DATE	2017	DBLP DOI BibTeX RDF
16	Xin He, Zhiwen Chen 0006, Jianhua Sun 0002, Hao Chen 0002, Dong Li 0001, Zhe Quan	Exploring Synchronization in Cache Coherent Manycore Systems: A Case Study with Xeon Phi.	ICPADS	2017	DBLP DOI BibTeX RDF
16	Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara	Software Cache Coherent Control by Parallelizing Compiler.	LCPC	2017	DBLP DOI BibTeX RDF