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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 517 occurrences of 343 keywords
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Results
Found 500 publication records. Showing 500 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
100 | Kashif Ali, Mokhtar Aboelaze, Suprakash Datta |
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 35-42, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
85 | Xavier Vera, Björn Lisper, Jingling Xue |
Data cache locking for tight timing calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(1), pp. 4:1-4:38, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
data cache analysis, embedded systems, Worst-case execution time, safety critical systems |
83 | Muhamed F. Mudawar |
Scalable cache memory design for large-scale SMT architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 65-71, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scalable multiported cache memory, simultaneous multithreaded architectures |
70 | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
HitME: low power Hit MEmory buffer for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 335-340, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Huesung Kim, Arun K. Somani, Akhilesh Tyagi |
A reconfigurable multi-function computing cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 85-94, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
56 | Caroline Benveniste, Peter A. Franaszek, John T. Robinson |
Cache-Memory Interfaces in Compressed Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1106-1116, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
memory compression, performance analysis, trace-driven simulation, cache design, Memory system design |
56 | Jih-Fu Tu |
Cache Management for Discrete Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Third International Symposium, ISPA 2005, Nanjing, China, November 2-5, 2005, Proceedings, pp. 205-215, 2005, Springer, 3-540-29769-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency |
56 | Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001 |
Compiler-Directed Cache Assist Adaptivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 88-104, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
54 | Maria Grigoriadou, Maria Toula, Evangelos Kanidis |
Design and Evaluation of a Cache Memory Simulation Program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALT ![In: 2003 IEEE International Conference on Advanced Learning Technologies, ICALT 2003, Athens, Greece, July 9-11, 2003, pp. 170-174, 2003, IEEE Computer Society, 0-7695-1967-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
53 | Somnath Ghosh, Margaret Martonosi, Sharad Malik |
Cache miss equations: a compiler framework for analyzing and tuning memory behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 21(4), pp. 703-746, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
optimization, compilation, program transformation, cache memories |
53 | Tohru Ishihara, Farzan Fallah |
A non-uniform cache architecture for low power system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 363-368, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, compiler, microprocessor, cache memory |
52 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Reducing leakage in a high-performance deep-submicron instruction cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 77-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Prasanna Palsodkar, Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar |
An Approach for Four Way Set Associative Multilevel CMOS Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 11th International Conference, KES 2007, XVII Italian Workshop on Neural Networks, Vietri sul Mare, Italy, September 12-14, 2007. Proceedings, Part I, pp. 740-746, 2007, Springer, 978-3-540-74817-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim |
Bounding Cache-Related Preemption Delay for Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 27(9), pp. 805-826, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Real-time system, cache memory, schedulability analysis, fixed-priority scheduling, preemption |
50 | Ju-Hyun Kim, Gyoung-Hwan Hyun, Hyuk-Jae Lee |
Cache Organizations for H.264/AVC Motion Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 534-541, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Le Cai, Yung-Hsiang Lu |
Power reduction of multiple disks using dynamic cache resizing and speed control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 186-190, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
disk rotation speed, power management, disk cache |
48 | Chun-Chieh Lin, Chuen-Liang Chen |
Object Placement for Fully Associative Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (2) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume II: Workshops, pp. 480-485, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Ying Zheng, Brian T. Davis, Matthew Jordan |
Performance evaluation of exclusive cache hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 89-96, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Amir H. Hashemi, David R. Kaeli, Brad Calder |
Efficient Procedure Mapping Using Cache Line Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), Las Vegas, Nevada, USA, June 15-18, 1997, pp. 171-182, 1997, ACM, 0-89791-907-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
46 | Chuanjun Zhang |
An efficient direct mapped instruction cache for application-specific embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 45-50, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
efficient cache design, instruction cache, low power cache |
46 | Kurt Mehlhorn, Peter Sanders 0001 |
Scanning Multiple Sequences Via Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 35(1), pp. 75-93, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam |
Morphable Cache Architectures: Potential Benefits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 128-137, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 147-157, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Tohru Ishihara, Kunihiro Asada |
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 282-287, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Martin Thuresson, Per Stenström |
Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2008 International Conference on Parallel Processing, ICPP 2008, September 8-12, 2008, Portland, Oregon, USA, pp. 478-486, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Milenkovic |
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, Huntsville, Alabama, USA, April 2-3, 2004, pp. 267-272, 2004, ACM, 1-58113-870-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance evaluation, cache memory, replacement policy |
43 | Jung-Hoon Lee |
Next High Performance and Low Power Flash Memory Package Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(4), pp. 515-520, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory |
43 | Mohsen Soryani, Mohsen Sharifi, Mohammad Hossein Rezvani |
Performance Evaluation of Cache Memory Organizations in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2-4 April 2007, Las Vegas, Nevada, USA, pp. 1045-1050, 2007, IEEE Computer Society, 978-0-7695-2776-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Gianni Franceschini |
Proximity Mergesort: optimal in-place sorting in the cache-oblivious model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Fifteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2004, New Orleans, Louisiana, USA, January 11-14, 2004, pp. 291-299, 2004, SIAM, 0-89871-558-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
42 | Andrea Prati 0001 |
Exploring multimedia applications locality to improve cache performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 8th ACM International Conference on Multimedia 2000, Los Angeles, CA, USA, October 30 - November 3, 2000., pp. 509-510, 2000, ACM, 1-58113-198-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Rama Sangireddy, Huesung Kim, Arun K. Somani |
Low-Power High-Performance Reconfigurable Computing Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(10), pp. 1274-1290, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Hong Wang 0003, Tong Sun, Qing Yang 0001 |
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 381-390, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
38 | Richard E. Ladner, Ray Fortna, Bao-Hoang Nguyen |
A Comparison of Cache Aware and Cache Oblivious Static Search Trees Using Program Instrumentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Experimental Algorithmics ![In: Experimental Algorithmics, From Algorithm Design to Robust and Efficient Software [Dagstuhl seminar, September 2000], pp. 78-92, 2000, Springer, 3-540-00346-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Huesung Kim, Arun K. Somani, Akhilesh Tyagi |
A reconfigurable multifunction computing cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(4), pp. 509-523, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Akira Yamawaki 0002, Masahiko Iwane |
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA, pp. 324-333, 2005, IEEE Computer Society, 0-7695-2509-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Jeffrey B. Rothman, Alan Jay Smith |
Sector Cache Design and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August - 1 September 2000, San Francisco, California, USA, pp. 124-133, 2000, IEEE Computer Society, 0-7695-0728-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
sector cache, simulation, architecture, workloads, multiprogramming |
35 | Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell, Vineet Chadha, Jaideep Moses |
Rate-based QoS techniques for cache/memory in CMP platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 479-488, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs |
35 | Kiyofumi Tanaka, Takenori Fujita |
Leakage Energy Reduction in Cache Memory by Software Self-invalidation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 163-174, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Sangyeun Cho, Lei Jin 0002, Kiyeon Lee |
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 3-11, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Huesung Kim, Arun K. Somani, Akhilesh Tyagi |
On Reconfiguring Cache for Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 296-297, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
cache, convolution, reconfigurable hardware |
34 | Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann |
Memory performance prediction for high-performance microprocessors at deep submicrometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1705-1718, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Philip J. Koopman Jr., Peter Lee 0001, Daniel P. Siewiorek |
Cache Behavior of Combinator Graph Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 14(2), pp. 265-297, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
self-modifying code, combinators, abstract machine, graph reduction |
34 | Rita Cucchiara, Massimo Piccardi, Andrea Prati 0001 |
Hardware Prefetching Techniques for Cache Memories in Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 311-319, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories |
34 | Ravi Mukkamala, Ashok K. Agrawala |
Modeling Memory Reference Patterns of Programs in Cache Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 1999, Proceedings of the 7th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 24-28 October, 1999, College Park, Maryland, USA, pp. 288-295, 1999, IEEE Computer Society, 0-7695-0381-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | David L. Rhodes, Wayne H. Wolf |
Unbalanced Cache Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 16-23, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | James E. Bennett, Michael J. Flynn |
Prediction Caches for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 81-90, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Prediction cache, Dynamic scheduling, Memory latency, Victim cache, Stream buffer |
31 | Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González 0001 |
A fast and accurate framework to analyze and optimize cache memory behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 26(2), pp. 263-300, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, sampling, Cache memories |
31 | Xiaoping Zhu, Teng-Tiow Tay |
A Compiler-Controlled Instruction Cache Architecture for an Embedded Low Power Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China, pp. 815-821, 2005, IEEE Computer Society, 0-7695-2432-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | José Aguilar 0001, Ernst L. Leiss |
A General Adaptive Cache Coherency-Replacement Scheme for Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IICS ![In: Innovative Internet Computing Systems, International Workshop IICS 2001, Ilmenau, Germany, June 21-22, 2001, Proceedings, pp. 116-125, 2001, Springer, 3-540-42275-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Victor M. DeLaLuz, Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer |
Access Pattern Restructuring for Memory Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(4), pp. 289-303, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
banked memories, embedded systems, Compiler optimization, energy consumption, access pattern |
29 | Nikolas Kroupis, Dimitrios Soudris |
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 505-515, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Tzi-cker Chiueh, Prashant Pradhan |
Cache Memory Design for Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 409-418, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Routing Table Lookup, Caching, Network Processors |
29 | Hyacinthe Aboudja, Jonathan Simonson |
Real-Time Systems Performance Improvement with Multi-Level Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 78-81, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen |
The TM3270 Media-Processor Data Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 334-341, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Chuanjun Zhang, Jun Yang 0002, Frank Vahid |
Low Static-Power Frequent-Value Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 214-219, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Alvin R. Lebeck |
Cache conscious programming in undergraduate computer science. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 30th SIGCSE Technical Symposium on Computer Science Education, SIGCSE 1999, New Orleans, Louisiana, USA, March 14-28, 1999, pp. 247-251, 1999, ACM, 1-58113-085-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González 0001 |
Memory Bank Predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 666-670, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim |
An Accurate Worst Case Timing Analysis for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(7), pp. 593-604, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor |
27 | Tay Teng Tiow, Zhu Xiaoping |
A runtime auto scalable power-efficient instruction-cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5270-5273, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Carlos Molina, Carles Aliagas, Montse Garcia 0002, Antonio González 0001, Jordi Tubella |
Non redundant data cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 274-277, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
value replication, low power, compression, cache memories |
27 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 193-203, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Susanne Graf |
Characterization of a Sequentially Consistent Memory and Verification of a Cache Memory by Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 12(2-3), pp. 75-90, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera |
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10139-, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Nicholas Ironmonger |
Trace-Splitting for the Parallel Simulation of Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 317-328, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Ravi R. Iyer 0001, Li Zhao 0002, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt |
QoS policies and architecture for cache/memory in CMP platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2007, San Diego, California, USA, June 12-16, 2007, pp. 25-36, 2007, ACM, 978-1-59593-639-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache/memory, resource sharing priniciples, QoS, quality of service, performance, CMP, service level agreements |
25 | Steven M. German |
Formal Design of Cache Memory Protocols in IBM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 22(2), pp. 133-141, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
formal design of hardware, cache memory protocol, Murphi verifier, protocol verification |
25 | Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems |
Application-adaptive intelligent cache memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 1(1), pp. 56-78, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality |
25 | John E. Sasinowski, Jay K. Strosnider |
A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(8), pp. 997-1001, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
cache memory partitioning, on-line reconfiguration, memory resources, real-time systems, real-time systems, dynamic programming, memory architecture, polynomial time, buffer storage, optimal partitioning, dynamic programming algorithm |
25 | Gurindar S. Sohi |
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(4), pp. 484-492, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits |
25 | Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer |
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1325-1336, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
cache memory systems, realistic workloads, mean miss rate, primed cache, sampling-based method, performance evaluation, performance evaluation, digital simulation, buffer storage, statistical techniques, simulation techniques, address trace |
25 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
Performance of Graceful Degradation for Cache Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 409-415, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos |
Preventing Denial-of-Service Attacks in Shared CMP Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 359-372, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King |
Performance of Shared Cache on Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 541-548, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache |
25 | Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran |
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 295-304, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
miss rate, simulation, LRU, cache simulation, L1 cache |
25 | Ravi R. Iyer 0001 |
Characterization and Evaluation of Cache Hierarchies for Web Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Wide Web ![In: World Wide Web 7(3), pp. 259-280, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
chipsets, snoop filters, simulation, performance evaluation, memory hierarchy, web servers, cache coherence, shared caches, commercial workloads |
25 | James D. Fix |
The set-associative cache performance of search trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Fourteenth Annual ACM-SIAM Symposium on Discrete Algorithms, January 12-14, 2003, Baltimore, Maryland, USA., pp. 565-572, 2003, ACM/SIAM, 0-89871-538-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
25 | David Wonnacott |
Using Time Skewing to Eliminate Idle Time due to Memory Bandwidth and Network Limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 171-180, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
compute balance, machine balance, scalable locality, scalable parallelism, cache optimization, loop tiling |
25 | Sofien Chtourou, Mohamed Chtourou, Omar Hammami |
Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2006, part of the IEEE World Congress on Computational Intelligence, WCCI 2006, Vancouver, BC, Canada, 16-21 July 2006, pp. 2823-2829, 2006, IEEE, 0-7803-9490-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Julien Bourgeois, François Spies, M. J. Zemerly, Thierry Delaitre |
Chronos: a Performance Characterization Tool Inside the EDPEPPS Toolset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 15(2), pp. 123-140, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CPU modeling, cache memory modeling, parallel programing environments, Performance characterization |
24 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
A novel instruction scratchpad memory optimization method based on concomitance metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 612-617, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Jie Tao 0001, Dominic Hillenbrand, Holger Marten |
Instruction Hints for Super Efficient Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (2) ![In: Computational Science - ICCS 2009, 9th International Conference, Baton Rouge, LA, USA, May 25-27, 2009, Proceedings, Part II, pp. 677-685, 2009, Springer, 978-3-642-01972-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation, architecture design, Cache optimization |
23 | Abel G. Silva-Filho, Carmelo J. A. Bastos Filho, Ricardo Massa Ferreira Lima, Davi M. A. Falcão, Filipe R. Cordeiro, Marília P. Lima |
An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 177-184, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Vijay Degalahal, Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Soft errors issues in low-power caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(10), pp. 1157-1166, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
An interleaved cache clustered VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 210-219, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures |
23 | Daranee Hormdee, Jim D. Garside |
AMULET3i Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 152-161, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig |
Performance and power of cache-based reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches |
23 | Abu Asaduzzaman, Imad Mahgoub |
Cache modeling and optimization for portable devices running MPEG-4 video decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 28(1-2), pp. 239-256, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPEG-4, Cache optimization, Portable devices, Cache modeling, Video decoder |
23 | Peng Li 0031, Dongsheng Wang 0002, Songliu Guo, Tao Tian, Weimin Zheng |
Live Range Aware Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 409-415, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Live Range, Cache, Memory Hierarchy |
23 | Siddhartha Chatterjee, Sandeep Sen |
Cache-Efficient Matrix Transposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 195-205, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Ravi R. Iyer 0001, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan |
An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(4), pp. 307-350, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance analysis, Parallel architectures, shared memory |
22 | Bruno Cernuschi-Frías, José Luis Hamkalo, Jonás D. Pfefferman, Hernán Gonzalez |
Analysis of cache memory strategies for some image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings of the 2001 International Conference on Image Processing, ICIP 2001, Thessaloniki, Greece, October 7-10, 2001, pp. 334-337, 2001, IEEE, 0-7803-6725-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell, Srihari Makineni |
CMPSched$im: Evaluating OS/CMP interaction on shared cache management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 113-122, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002 |
Realization of L2 Cache Defect Tolerance Using Multi-bit ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 254-262, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, José Flich |
Understanding cache hierarchy interactions with a program-driven simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE 2007, San Diego, California, USA, Saturday, June 9, 2007, pp. 30-35, 2007, ACM, 978-1-59593-797-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-level caches, cache organization, write policies |
21 | Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque |
A Reconfigurable Data Cache for Adaptive Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 230-242, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Jaeeun Jeon, Gunhoon Lee, Ki Dong Lee, ByoungChul Ahn |
An Adaptive Prefetching Method for Web Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part III, pp. 566-574, 2004, Springer, 3-540-22057-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Carles Aliagas, Carlos Molina, Montse Garcia 0002, Antonio González 0001, Jordi Tubella |
Value Compression to Reduce Power in Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 616-622, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Rama Sangireddy, Huesung Kim, Arun K. Somani |
Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 124-136, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | José Aguilar 0001, Ernst L. Leiss |
A Web Proxy Cache Coherency and Replacement Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web Intelligence ![In: Web Intelligence: Research and Development, First Asia-Pacific Conference, WI 2001, Maebashi City, Japan, October 23-26, 2001, Proceedings, pp. 75-84, 2001, Springer, 3-540-42730-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Giovanni Erbacci, Giuseppe Paruolo, Giancarlo Tagliavini |
Influence of the stride on the cache utilization in the IBM 3090 VF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 443-451, 1989, ACM, 0-89791-309-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
FORTRAN |
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