Search results for "cache/memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
100	Kashif Ali, Mokhtar Aboelaze, Suprakash Datta	Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
85	Xavier Vera, Björn Lisper, Jingling Xue	Data cache locking for tight timing calculations.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	data cache analysis, embedded systems, Worst-case execution time, safety critical systems
83	Muhamed F. Mudawar	Scalable cache memory design for large-scale SMT architectures.	WMPI	2004	DBLP DOI BibTeX RDF	scalable multiported cache memory, simultaneous multithreaded architectures
70	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic	HitME: low power Hit MEmory buffer for embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
61	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multi-function computing cache architecture.	FPGA	2000	DBLP DOI BibTeX RDF
56	Caroline Benveniste, Peter A. Franaszek, John T. Robinson	Cache-Memory Interfaces in Compressed Memory Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	memory compression, performance analysis, trace-driven simulation, cache design, Memory system design
56	Jih-Fu Tu	Cache Management for Discrete Processor Architectures.	ISPA	2005	DBLP DOI BibTeX RDF	Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency
56	Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001	Compiler-Directed Cache Assist Adaptivity.	ISHPC	2000	DBLP DOI BibTeX RDF
54	Maria Grigoriadou, Maria Toula, Evangelos Kanidis	Design and Evaluation of a Cache Memory Simulation Program.	ICALT	2003	DBLP DOI BibTeX RDF
53	Somnath Ghosh, Margaret Martonosi, Sharad Malik	Cache miss equations: a compiler framework for analyzing and tuning memory behavior.	ACM Trans. Program. Lang. Syst.	1999	DBLP DOI BibTeX RDF	optimization, compilation, program transformation, cache memories
53	Tohru Ishihara, Farzan Fallah	A non-uniform cache architecture for low power system design.	ISLPED	2005	DBLP DOI BibTeX RDF	embedded systems, compiler, microprocessor, cache memory
52	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
52	Prasanna Palsodkar, Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar	An Approach for Four Way Set Associative Multilevel CMOS Cache Memory.	KES (1)	2007	DBLP DOI BibTeX RDF
51	Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim	Bounding Cache-Related Preemption Delay for Real-Time Systems.	IEEE Trans. Software Eng.	2001	DBLP DOI BibTeX RDF	Real-time system, cache memory, schedulability analysis, fixed-priority scheduling, preemption
50	Ju-Hyun Kim, Gyoung-Hwan Hyun, Hyuk-Jae Lee	Cache Organizations for H.264/AVC Motion Compensation.	RTCSA	2007	DBLP DOI BibTeX RDF
49	Le Cai, Yung-Hsiang Lu	Power reduction of multiple disks using dynamic cache resizing and speed control.	ISLPED	2006	DBLP DOI BibTeX RDF	disk rotation speed, power management, disk cache
48	Chun-Chieh Lin, Chuen-Liang Chen	Object Placement for Fully Associative Cache.	EUC (2)	2008	DBLP DOI BibTeX RDF
48	Ying Zheng, Brian T. Davis, Matthew Jordan	Performance evaluation of exclusive cache hierarchies.	ISPASS	2004	DBLP DOI BibTeX RDF
48	Amir H. Hashemi, David R. Kaeli, Brad Calder	Efficient Procedure Mapping Using Cache Line Coloring.	PLDI	1997	DBLP DOI BibTeX RDF
46	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
46	Kurt Mehlhorn, Peter Sanders 0001	Scanning Multiple Sequences Via Cache Memory.	Algorithmica	2003	DBLP DOI BibTeX RDF
46	Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam	Morphable Cache Architectures: Potential Benefits.	LCTES/OM	2001	DBLP DOI BibTeX RDF
44	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.	HPCA	2001	DBLP DOI BibTeX RDF
44	Tohru Ishihara, Kunihiro Asada	An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
44	Martin Thuresson, Per Stenström	Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression.	ICPP	2008	DBLP DOI BibTeX RDF
44	Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Milenkovic	Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite.	ACM Southeast Regional Conference	2004	DBLP DOI BibTeX RDF	performance evaluation, cache memory, replacement policy
43	Jung-Hoon Lee	Next High Performance and Low Power Flash Memory Package Structure.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory
43	Mohsen Soryani, Mohsen Sharifi, Mohammad Hossein Rezvani	Performance Evaluation of Cache Memory Organizations in Embedded Systems.	ITNG	2007	DBLP DOI BibTeX RDF
42	Gianni Franceschini	Proximity Mergesort: optimal in-place sorting in the cache-oblivious model.	SODA	2004	DBLP BibTeX RDF
42	Andrea Prati 0001	Exploring multimedia applications locality to improve cache performance.	ACM Multimedia	2000	DBLP DOI BibTeX RDF
40	Rama Sangireddy, Huesung Kim, Arun K. Somani	Low-Power High-Performance Reconfigurable Computing Cache Architectures.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
40	Hong Wang 0003, Tong Sun, Qing Yang 0001	CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches.	ISCA	1995	DBLP DOI BibTeX RDF
38	Richard E. Ladner, Ray Fortna, Bao-Hoang Nguyen	A Comparison of Cache Aware and Cache Oblivious Static Search Trees Using Program Instrumentation.	Experimental Algorithmics	2000	DBLP DOI BibTeX RDF
38	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multifunction computing cache architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
37	Akira Yamawaki 0002, Masahiko Iwane	Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor.	ISPAN	2005	DBLP DOI BibTeX RDF
37	Jeffrey B. Rothman, Alan Jay Smith	Sector Cache Design and Performance.	MASCOTS	2000	DBLP DOI BibTeX RDF	sector cache, simulation, architecture, workloads, multiprogramming
35	Andrew Herdrich, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell, Vineet Chadha, Jaideep Moses	Rate-based QoS techniques for cache/memory in CMP platforms.	ICS	2009	DBLP DOI BibTeX RDF	p-states, performance differentiation, t-states, cache, memory, rate control, qos, clock gating, frequency scaling, dvfs
35	Kiyofumi Tanaka, Takenori Fujita	Leakage Energy Reduction in Cache Memory by Software Self-invalidation.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
35	Sangyeun Cho, Lei Jin 0002, Kiyeon Lee	Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.	RTCSA	2007	DBLP DOI BibTeX RDF
35	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	On Reconfiguring Cache for Computing.	FCCM	1999	DBLP DOI BibTeX RDF	cache, convolution, reconfigurable hardware
34	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
34	Philip J. Koopman Jr., Peter Lee 0001, Daniel P. Siewiorek	Cache Behavior of Combinator Graph Reduction.	ACM Trans. Program. Lang. Syst.	1992	DBLP DOI BibTeX RDF	self-modifying code, combinators, abstract machine, graph reduction
34	Rita Cucchiara, Massimo Piccardi, Andrea Prati 0001	Hardware Prefetching Techniques for Cache Memories in Multimedia Applications.	CAMP	2000	DBLP DOI BibTeX RDF	hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories
34	Ravi Mukkamala, Ashok K. Agrawala	Modeling Memory Reference Patterns of Programs in Cache Memory Systems.	MASCOTS	1999	DBLP DOI BibTeX RDF
33	David L. Rhodes, Wayne H. Wolf	Unbalanced Cache Systems.	MTDT	1999	DBLP DOI BibTeX RDF
33	James E. Bennett, Michael J. Flynn	Prediction Caches for Superscalar Processors.	MICRO	1997	DBLP DOI BibTeX RDF	Prediction cache, Dynamic scheduling, Memory latency, Victim cache, Stream buffer
31	Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González 0001	A fast and accurate framework to analyze and optimize cache memory behavior.	ACM Trans. Program. Lang. Syst.	2004	DBLP DOI BibTeX RDF	optimization, sampling, Cache memories
31	Xiaoping Zhu, Teng-Tiow Tay	A Compiler-Controlled Instruction Cache Architecture for an Embedded Low Power Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
31	José Aguilar 0001, Ernst L. Leiss	A General Adaptive Cache Coherency-Replacement Scheme for Distributed Systems.	IICS	2001	DBLP DOI BibTeX RDF
30	Victor M. DeLaLuz, Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer	Access Pattern Restructuring for Memory Energy.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	banked memories, embedded systems, Compiler optimization, energy consumption, access pattern
29	Nikolas Kroupis, Dimitrios Soudris	Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate.	PATMOS	2007	DBLP DOI BibTeX RDF
29	Tzi-cker Chiueh, Prashant Pradhan	Cache Memory Design for Network Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Routing Table Lookup, Caching, Network Processors
29	Hyacinthe Aboudja, Jonathan Simonson	Real-Time Systems Performance Improvement with Multi-Level Cache Memory.	CCECE	2006	DBLP DOI BibTeX RDF
29	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen	The TM3270 Media-Processor Data Cache.	ICCD	2005	DBLP DOI BibTeX RDF
29	Chuanjun Zhang, Jun Yang 0002, Frank Vahid	Low Static-Power Frequent-Value Data Caches.	DATE	2004	DBLP DOI BibTeX RDF
29	Alvin R. Lebeck	Cache conscious programming in undergraduate computer science.	SIGCSE	1999	DBLP DOI BibTeX RDF
29	Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González 0001	Memory Bank Predictors.	ICCD	2005	DBLP DOI BibTeX RDF
28	Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim	An Accurate Worst Case Timing Analysis for RISC Processors.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor
27	Tay Teng Tiow, Zhu Xiaoping	A runtime auto scalable power-efficient instruction-cache design.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
27	Carlos Molina, Carles Aliagas, Montse Garcia 0002, Antonio González 0001, Jordi Tubella	Non redundant data cache.	ISLPED	2003	DBLP DOI BibTeX RDF	value replication, low power, compression, cache memories
27	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.	CGO	2003	DBLP DOI BibTeX RDF
26	Susanne Graf	Characterization of a Sequentially Consistent Memory and Verification of a Cache Memory by Abstraction.	Distributed Comput.	1999	DBLP DOI BibTeX RDF
25	Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera	Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory.	EUROMICRO	1998	DBLP DOI BibTeX RDF
25	Nicholas Ironmonger	Trace-Splitting for the Parallel Simulation of Cache Memory.	PARLE	1993	DBLP DOI BibTeX RDF
25	Ravi R. Iyer 0001, Li Zhao 0002, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt	QoS policies and architecture for cache/memory in CMP platforms.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	cache/memory, resource sharing priniciples, QoS, quality of service, performance, CMP, service level agreements
25	Steven M. German	Formal Design of Cache Memory Protocols in IBM.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	formal design of hardware, cache memory protocol, Murphi verifier, protocol verification
25	Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems	Application-adaptive intelligent cache memory system.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality
25	John E. Sasinowski, Jay K. Strosnider	A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	cache memory partitioning, on-line reconfiguration, memory resources, real-time systems, real-time systems, dynamic programming, memory architecture, polynomial time, buffer storage, optimal partitioning, dynamic programming algorithm
25	Gurindar S. Sohi	Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits
25	Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer	Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	cache memory systems, realistic workloads, mean miss rate, primed cache, sampling-based method, performance evaluation, performance evaluation, digital simulation, buffer storage, statistical techniques, simulation techniques, address trace
25	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	Performance of Graceful Degradation for Cache Faults.	ISVLSI	2007	DBLP DOI BibTeX RDF
25	Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos	Preventing Denial-of-Service Attacks in Shared CMP Caches.	SAMOS	2006	DBLP DOI BibTeX RDF
25	Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King	Performance of Shared Cache on Multithreaded Architectures.	PDP	1996	DBLP DOI BibTeX RDF	shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache
25	Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran	SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	miss rate, simulation, LRU, cache simulation, L1 cache
25	Ravi R. Iyer 0001	Characterization and Evaluation of Cache Hierarchies for Web Servers.	World Wide Web	2004	DBLP DOI BibTeX RDF	chipsets, snoop filters, simulation, performance evaluation, memory hierarchy, web servers, cache coherence, shared caches, commercial workloads
25	James D. Fix	The set-associative cache performance of search trees.	SODA	2003	DBLP BibTeX RDF
25	David Wonnacott	Using Time Skewing to Eliminate Idle Time due to Memory Bandwidth and Network Limitations.	IPDPS	2000	DBLP DOI BibTeX RDF	compute balance, machine balance, scalable locality, scalable parallelism, cache optimization, loop tiling
25	Sofien Chtourou, Mohamed Chtourou, Omar Hammami	Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration.	IJCNN	2006	DBLP DOI BibTeX RDF
24	Julien Bourgeois, François Spies, M. J. Zemerly, Thierry Delaitre	Chronos: a Performance Characterization Tool Inside the EDPEPPS Toolset.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	CPU modeling, cache memory modeling, parallel programing environments, Performance characterization
24	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	A novel instruction scratchpad memory optimization method based on concomitance metric.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Jie Tao 0001, Dominic Hillenbrand, Holger Marten	Instruction Hints for Super Efficient Data Caches.	ICCS (2)	2009	DBLP DOI BibTeX RDF	simulation, architecture design, Cache optimization
23	Abel G. Silva-Filho, Carmelo J. A. Bastos Filho, Ricardo Massa Ferreira Lima, Davi M. A. Falcão, Filipe R. Cordeiro, Marília P. Lima	An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
23	Vijay Degalahal, Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Soft errors issues in low-power caches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
23	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	An interleaved cache clustered VLIW processor.	ICS	2002	DBLP DOI BibTeX RDF	attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
23	Daranee Hormdee, Jim D. Garside	AMULET3i Cache Architecture.	ASYNC	2001	DBLP DOI BibTeX RDF
23	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	FPGA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches
23	Abu Asaduzzaman, Imad Mahgoub	Cache modeling and optimization for portable devices running MPEG-4 video decoder.	Multim. Tools Appl.	2006	DBLP DOI BibTeX RDF	MPEG-4, Cache optimization, Portable devices, Cache modeling, Video decoder
23	Peng Li 0031, Dongsheng Wang 0002, Songliu Guo, Tao Tian, Weimin Zheng	Live Range Aware Cache Architecture.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Live Range, Cache, Memory Hierarchy
23	Siddhartha Chatterjee, Sandeep Sen	Cache-Efficient Matrix Transposition.	HPCA	2000	DBLP DOI BibTeX RDF
23	Ravi R. Iyer 0001, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan	An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	performance analysis, Parallel architectures, shared memory
22	Bruno Cernuschi-Frías, José Luis Hamkalo, Jonás D. Pfefferman, Hernán Gonzalez	Analysis of cache memory strategies for some image processing applications.	ICIP (3)	2001	DBLP DOI BibTeX RDF
21	Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell, Srihari Makineni	CMPSched$im: Evaluating OS/CMP interaction on shared cache management.	ISPASS	2009	DBLP DOI BibTeX RDF
21	Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002	Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.	DFT	2008	DBLP DOI BibTeX RDF
21	Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, José Flich	Understanding cache hierarchy interactions with a program-driven simulator.	WCAE	2007	DBLP DOI BibTeX RDF	multi-level caches, cache organization, write policies
21	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	A Reconfigurable Data Cache for Adaptive Processors.	ARC	2006	DBLP DOI BibTeX RDF
21	Jaeeun Jeon, Gunhoon Lee, Ki Dong Lee, ByoungChul Ahn	An Adaptive Prefetching Method for Web Caches.	ICCSA (3)	2004	DBLP DOI BibTeX RDF
21	Carles Aliagas, Carlos Molina, Montse Garcia 0002, Antonio González 0001, Jordi Tubella	Value Compression to Reduce Power in Data Caches.	Euro-Par	2003	DBLP DOI BibTeX RDF
21	Rama Sangireddy, Huesung Kim, Arun K. Somani	Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing.	HiPC	2002	DBLP DOI BibTeX RDF
21	José Aguilar 0001, Ernst L. Leiss	A Web Proxy Cache Coherency and Replacement Approach.	Web Intelligence	2001	DBLP DOI BibTeX RDF
21	Giovanni Erbacci, Giuseppe Paruolo, Giancarlo Tagliavini	Influence of the stride on the cache utilization in the IBM 3090 VF.	ICS	1989	DBLP DOI BibTeX RDF	FORTRAN