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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 64 occurrences of 50 keywords
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Results
Found 96 publication records. Showing 96 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
105 | Seiji Kajihara, Tsutomu Sasao |
On the Adders with Minimum Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 10-15, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders |
103 | Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas |
Efficient Reversible Logic Design of BCD Subtractors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Comput. Sci. ![In: Transactions on Computational Science III, pp. 99-121, 2009, Springer, 978-3-642-00211-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BCD subtractors, BCD adders, Reversible logic |
98 | Tomás Lang, Javier D. Bruguera |
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 73-79, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Most significant carry, prefix tree, carry look-ahead adder |
84 | Robert W. Doran |
Variants of an Improved Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(9), pp. 1110-1113, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
look-ahead carry, adder, adders, variation, improved, carry look-ahead adder |
84 | Himanshu Thapliyal, Sumedha K. Gupta |
Design of Novel Reversible Carry Look-Ahead BCD Subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: 9th International Conference in Information Technology, ICIT 2006, Bhubaneswar, Orissa, India, 18-21 December 2006, pp. 253-258, 2006, IEEE Computer Society, 0-7695-2635-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
80 | Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos |
Diminished-One Modulo 2n+1 Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(12), pp. 1389-1399, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders |
69 | Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos |
High-Speed Parallel-Prefix Modulo 2n-1 Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 673-680, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders |
66 | Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan |
Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 140, pp. 105949, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
60 | Bernd Becker 0001, Reiner Kolla |
On the Construction of Optimal Time Adders (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 88, 5th Annual Symposium on Theoretical Aspects of Computer Science, Bordeaux, France, February 11-13, 1988, Proceedings, pp. 18-28, 1988, Springer, 3-540-18834-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
57 | Himanshu Thapliyal, M. B. Srinivas |
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 805-817, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Antonio Blotti, Maurizio Castellucci, Roberto Saletti |
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 118-127, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel |
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 365-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Andreas Herrfeld, Siegbert Hentschke |
Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 174-179, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
MVL, ternary adder, ternary multiplication, VLSI, multiple valued-logic |
51 | Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam |
A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 109, pp. 104992, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
51 | Md. Ashik Zafar Dipto, Afran Sorwar, Elias Ahammad Sojib, Md. Mostak Tahmid Rangon |
Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 11th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2020, Kharagpur, India, July 1-3, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-6851-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
51 | Mehedi Hasan, Parag Biswas, Md. Shihabul Alam, Hasan U. Zaman, Mainul Hossain, Sharnali Islam |
High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 10th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2019, Kanpur, India, July 6-8, 2019, pp. 1-5, 2019, IEEE, 978-1-5386-5906-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
51 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3344, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
51 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1008.3311, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
51 | Gustavo A. Ruiz, Mercedes Granda |
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 35(12), pp. 939-944, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga |
Design of High-Speed Floating Point Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 285-289, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm |
48 | Nhon T. Quach, Michael J. Flynn |
High-Speed Addition in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1612-1615, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit |
48 | Binay Sugla, David A. Carlson |
Extreme Area-Time Tradeoffs in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(2), pp. 251-257, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder |
48 | Yang-Chang Hong, Thomas H. Payne |
Parallel Sorting in a Ring Network of Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(3), pp. 458-464, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
ring network of processors, selection sorting algorithms, ring-connected array, item placement, carry-look-ahead techniques, computer networks, sorting, maintenance, manufacture, parallel implementation, performance improvement, inventory, parallel sorting |
48 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(9), pp. 1113-1121, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder |
48 | Dharma P. Agrawal |
High-Speed Arithmetic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(3), pp. 215-224, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction |
44 | Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Low-Power Carry Skip Adder with Fast Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 269-279, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 215-223, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
36 | Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee |
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(4), pp. 2283-2304, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Riley Jackson, Maxwell Phillips, Firas Hassan, Ahmed Ammar |
High Precision Carry-Look-Ahead Logic for Negation, Absolute Value, and Two's Complement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Tomoyuki Tanaka, Christopher L. Ayala, Nobuyuki Yoshikawa |
A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 105-C(6), pp. 270-276, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
36 | Sharana Basappa, P. Ravi Babu |
A low power architecture for 1D median filter using carry look ahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Adv. Intell. Paradigms ![In: Int. J. Adv. Intell. Paradigms 20(1/2), pp. 16-37, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
36 | Bharat Garg, Sujit Kumar Patel |
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 93(1), pp. 99-111, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
36 | Jianmin Wang, Fengqiu Liu, Yuhu Wu |
Stuck-at Fault Diagnosis of Four-bit Carry Look-ahead Adder by Shannon Expansion via Semi-tensor Product. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SICE ![In: 60th Annual Conference of the Society of Instrument and Control Engineers of Japan, SICE 2021, Tokyo, Japan, September 8-10, 2021, pp. 933-938, 2021, IEEE, 978-4-9077-6473-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
36 | V. Muralidharan, N. Sathish Kumar |
Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 75, pp. 103054, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Hassan Afzali-Kusha, Mehdi Kamal, Massoud Pedram |
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 21st International Symposium on Quality Electronic Design, ISQED 2020, Santa Clara, CA, USA, March 25-26, 2020, pp. 67-72, 2020, IEEE, 978-1-7281-4207-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Tasneem AlSalem, Lina Nazzal, Marah Samara, Mawahib Hussein Sulieman |
Design and Simulation of 90 nm Threshold Logic Carry-Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIT ![In: International Arab Conference on Information Technology, ACIT 2019, Al Ain, United Arab Emirates, December 3-5, 2019, pp. 283-286, 2019, IEEE, 978-1-7281-3010-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Sara Ghafari, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi |
A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019, pp. 157-162, 2019, IEEE, 978-83-63578-16-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | A. Nagalakshmi, Ch. Sirisha, D. N. Madhusudana Rao |
Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.04074, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
36 | Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(8), pp. 1089-1093, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
36 | Ioannis Voyiatzis, Costas Efstathiou |
SIC pair generation in near-optimal time with carry-look ahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018, Taormina, Italy, April 9-12, 2018, pp. 1-2, 2018, IEEE, 978-1-5386-5291-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
36 | Jabulani Nyathi, Abubaker Mutumba |
Slowing the none-critical path to improve carry look-ahead adder power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 890-893, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Pao-Lung Chen |
A low-cost carry look-ahead adder for flying-adder frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-TW ![In: IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2016, Nantou County, Taiwan, May 27-29, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-2073-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Raj Johri, Shyam Akashe, Sanjay Sharma |
High performance 8 bit cascaded carry look ahead adder with precise power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Syst. ![In: Int. J. Commun. Syst. 28(8), pp. 1475-1483, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Mojtaba Valinataj |
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(12), pp. 2845-2857, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Nusrat Jahan Lisa, Hafiz Md. Hasan Babu |
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 238-243, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Himanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia |
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Comput. Sci. ![In: Transactions on Computational Science XVII, pp. 73-97, 2013, Springer, 978-3-642-35839-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas |
New High-Speed Multioutput Carry Look-Ahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 60-II(10), pp. 667-671, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Hafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen |
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 98-103, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Itamar Levi, Ori Bass, Asaf Kaizerman, Alexander Belenky, Alexander Fish |
High speed Dual Mode Logic Carry Look Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 3037-3040, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
36 | P. H. S. T. Murthy, L. Madan Mohan, V. Sreenivasa Rao, V. Malleswara Rao |
4T Carry Look Ahead Adder Design Using MIFG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Information and Communication Technologies - International Conference, ICT 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings, pp. 490-494, 2010, Springer, 978-3-642-15765-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
36 | Alireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali |
A low-cost fault-tolerant technique for Carry Look-Ahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, pp. 217-222, 2009, IEEE Computer Society, 978-1-4244-4596-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas |
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 547-552, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Himanshu Thapliyal, Hamid R. Arabnia |
Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006, pp. 64-69, 2006, CSREA Press, 1-60132-009-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
36 | Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas |
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), March 8-11, Dubai/Sharjah, UAE, pp. 88-92, 2006, IEEE Computer Society, 1-4244-0211-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Bart Desoete, Alexis De Vos |
A reversible carry-look-ahead adder using control gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 33(1-2), pp. 89-104, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko |
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(6), pp. 810-818, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
36 | James B. Kuo, Hung-Pin Chen 0001, H. J. Huang |
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2027-2030, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
34 | Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Static Low-Power, High-Performance 32-bit Carry Skip Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 615-619, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim |
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 350-359, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Krister Landernäs, Johnny Holmberg, Mark Vesterbacka |
A high-speed low-latency digit-serial hybrid adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 217-220, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Feng Zhou, Peter Kornerup |
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 180-187, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
32 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1986, Bratislava, Czechoslovakia, August 25-29, 1996, Proceedings, pp. 218-229, 1986, Springer, 3-540-16783-8. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
30 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Fast Low-Power 64-Bit Modular Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 609-617, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien |
Performance comparison of quantum-dot cellular automata adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2522-2526, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman |
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(1), pp. 69-72, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
binary signed-digit number system, most significant carry detection, Sign detection |
25 | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas |
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 343-350, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen |
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 142-145, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Swapnil Bahl |
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 331-339, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas |
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 387-392, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 155-163, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
21 | Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002 |
An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(10), pp. 1563-1571, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
number comparison, sign determination, overflow detection, VLSI, RNS, parity check |
21 | Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu |
The new architecture of radix-4 Chinese abacus adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 12, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis |
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 127-134, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Sheng Sun, Larry McMurchie, Carl Sechen |
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 213-223, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy |
(Quasi-) Linear Path Delay Fault Tests for Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 101-105, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Tin Wai Kwan, Maitham Shams |
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 23-32, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer |
QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 217-228, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas |
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 181-185, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ECDL, CMOS, adder, digital circuits |
16 | Ciaran McIvor, Máire McLoone, John V. McCanny |
FPGA Montgomery Multiplier Architectures - A Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 279-282, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Ciaran McIvor, Máire McLoone, John V. McCanny |
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 509-512, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | P. C. Chen, James B. Kuo |
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 441-444, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Bhushan A. Shinkre, James E. Stine |
A pipelined clock-delayed domino carry-lookahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 171-175, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim |
A Novel Clocking Strategy for Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 307-312, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
VLSI circuits for low-power high-speed asynchronous addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 608-613, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Mohab Anis, Mohamed I. Elmasry |
Self-timed MOS current mode logic for digital applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 113-116, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Hong-Yi Huang, Teng-Neng Wang |
High-speed CMOS logic circuits in capacitor coupling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 634-637, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Hamid Mahmoodi-Meimand, Ali Afzali-Kusha |
Efficient power clock generation for adiabatic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 642-645, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Gin Yee, Carl Sechen |
Clock-delayed domino for dynamic circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 425-430, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 195-204, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Mahmoud A. Manzoul |
Parallel CLA Algorithm for Fast Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 27-30 August 2000, Quebec, Canada, pp. 55-58, 2000, IEEE Computer Society, 0-7695-0759-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Aamir A. Farooqui, Vojin G. Oklobdzija |
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 30-33, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Dinesh Somasekhar, Kaushik Roy 0001 |
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 573-577, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi |
DCT/IDCT processor for HDTV developed with dsp silicon compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(2-3), pp. 151-158, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Rajiv Jain, Alice C. Parker, Nohbyung Park |
Module Selection for Pipelined Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 542-547, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
16 | Jagan P. Agrawal, V. Umapathi Reddy |
Log-sum multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1976 National Computer Conference, 7-10 June 1976, New York, NY, USA, pp. 783-787, 1976, AFIPS Press, 978-1-4503-7917-5. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
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