Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
169 | Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee |
Prospect of ballistic CNFET in high performance applications: Modeling and analysis. |
ACM J. Emerg. Technol. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance |
169 | Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee |
Modeling and analysis of circuit performance of ballistic CNFET. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance |
123 | Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi |
Performance assessment of analog circuits with carbon nanotube FET (CNFET). |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
analog, circuits |
120 | Saurabh Sinha, Asha Balijepalli, Yu Cao |
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Schottky barrier, analog design metrics, modeling, CNT |
100 | Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong |
Carbon nanotube transistor compact model for circuit design and performance optimization. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
VerilogA, carbon nanotube FET, compact model, CNT, HSPICE |
87 | Nishant Patil, Albert Lin, Jie Zhang 0007, H.-S. Philip Wong, Subhasish Mitra |
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
CNFET, carbon nanotube transistor, carbon nanotubes |
80 | Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra |
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
80 | Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra |
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Hamidreza Hashempour, Fabrizio Lombardi |
Device Model for Ballistic CNFETs Using the First Conducting Band. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
CNFET, charge density, self-consistent voltage, drain-source current, CAD, approximation, carbon nanotube, closed-form |
67 | Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee |
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
RF performance, carbon nanotube FET (CNFET), modeling |
63 | Jie Zhang 0007, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra |
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
CNT correlation, carbon nanotube, yield optimization, CNT |
60 | Bao Liu 0001 |
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
60 | Jie Zhang 0007, Nishant Patil, Arash Hazeghi, Subhasish Mitra |
Carbon nanotube circuits in the presence of carbon nanotube density variations. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
CNT correlation, CNT density variation, carbon nanotube, CNT |
60 | Jie Zhang 0007, Nishant Patil, Subhasish Mitra |
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Wei Zhang 0012, Niraj K. Jha |
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
50 | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli |
Programmable logic circuits based on ambipolar CNFET. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
CNFET, FPGA, PLA, carbon nanotube |
47 | Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli |
Graphene based transistors: physics, status and future perspectives. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
cnfet, gnr-fet., graphene, carbon nanotubes |
23 | Ahmad Karimi, Keivan Navi |
The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology. |
Comput. Electr. Eng. |
2024 |
DBLP DOI BibTeX RDF |
|
23 | Zihao Yang, Minghui Yin, Yunxia You, Zhiqiang Li, Xin Liu, Weihua Zhang |
Design of a high performance CNFET 10T SRAM cell at 5nm technology node. |
IEICE Electron. Express |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda |
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. |
ASP-DAC |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Shivani Thakur, Srinivasu Bodapati |
Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor Technology. |
APCCAS |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain |
A new low-power Dynamic-GDI full adder in CNFET technology. |
Integr. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Mehdi Takbiri, Keivan Navi, Reza Faghih Mirzaee |
Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial |
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa, Sanjay Vidhyadharan |
High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. |
Circuits Syst. Signal Process. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Mostafa Parvizi, Rana Haratian |
A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET Technology. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications. |
Wirel. Pers. Commun. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian |
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. |
ACM J. Emerg. Technol. Comput. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001 |
Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. |
ISLPED |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Heshmatpour, Lihong Zhang, Howard M. Heys |
Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits. |
ISQED |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Heshmatpour, Lihong Zhang, Howard M. Heys |
Robust CNFET Circuit Sizing Optimization. |
VLSI-DAT |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Panasa Srikanth, B. Srinivasu |
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. |
VDAT |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Jihad Mohamad Jaam, Bilal N. Owaydat, Somaya Ali Al-Máadeed, Abdallah Kassem, Ali Massoud Haidar 0001 |
Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani |
Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. |
Circuits Syst. Signal Process. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan |
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. |
Circuits Syst. Signal Process. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Hamidreza Uoosefian, Keivan Navi, Reza Faghih Mirzaee, Mehdi Hosseinzadeh 0001 |
Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator. |
J. Circuits Syst. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani |
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Yuanqing Cheng, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last Level Cache Design. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
23 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
23 | Daniel Etiemble |
Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits". |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Akbar Doostaregan, Adib Abrishamifar |
Evaluating a Methodology for Designing CNFET-Based Ternary Circuits. |
Circuits Syst. Signal Process. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Amin Avan, Mojtaba Maleknejad, Keivan Navi |
High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4: 2 compressor design in CNFET technology. |
IET Circuits Devices Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey |
A 1-bit full adder using CNFET based dual chirality high speed domino logic. |
Int. J. Circuit Theory Appl. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Ahmad M. El-Hajj, Abdallah Kassem, Lina A. Nimri, Ali M. Haidar 0001 |
CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Trapti Sharma, Laxmi Kumre |
CNFET based design of unbalanced ternary circuits using efficient shifting literals. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Ahmad M. El-Hajj, Ali M. Haidar 0001, Abdallah Kassem |
A Novel CNFET-Based Ternary to Binary Converter Design in Data Transmission. |
ICM |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit. |
ISQED |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Abdallah Kassem, Ahmad M. El-Hajj, Lina A. Nimri, Ali Massoud Haidar 0001 |
High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits. |
IEEE Access |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Akbar Doostaregan, Adib Abrishamifar |
A New Method for Design of CNFET-Based Quaternary Circuits. |
Circuits Syst. Signal Process. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Sepehr Tabrizchi, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design. |
IET Circuits Devices Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. |
Comput. Electr. Eng. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad, Ali Bohlooli |
A new design method for imperfection-immune CNFET-based circuit design. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Soumitra Pal 0002, Vivek Gupta 0006, Aminul Islam 0002 |
Design of CNFET based power- and variability-aware nonvolatile RRAM cell. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Maryam Toulabinejad, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001 |
Exploring emerging CNFET for efficient last level cache design. |
ASP-DAC |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Li Jiang 0002, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang |
CNFET-Based High Throughput SIMD Architecture. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas |
Energy efficient design of CNFET-based multi-digit ternary adders. |
Microelectron. J. |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
Energy Efficient Tri-State CNFET Ternary Logic Gates. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
23 | A. Nagalakshmi, Ch. Sirisha, D. N. Madhusudana Rao |
Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
23 | Srinithya Nagiri, Sananya Majumder, Riya, Aminul Islam |
Design of low power RRAM cell using CNFET. |
RAIT |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate Circuits. |
ACM Great Lakes Symposium on VLSI |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Using approximate circuits to counter process imperfections in CNFET based circuits. |
VLSI-DAT |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Zhengyang He, Kai Ren 0003, Jiayan Chen, Xinyi Dai, Zhao Pan 0001, Yuejun Zhang |
Design of Delayed Ternary PUF Circuit Based on CNFET. |
APCC |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Mokhtar Mohammadi Ghanatghestani, Behnam Ghavami, Honeya Salehpour |
A CNFET full adder cell design for high-speed arithmetic units. |
Turkish J. Electr. Eng. Comput. Sci. |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi |
A novel high-performance and reliable multi-threshold CNFET full adder cell design. |
Int. J. High Perform. Syst. Archit. |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Mohan Krishna Gopi Krishna, Arman Roohi, Ramtin Zand, Ronald F. DeMara |
Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing. |
IET Circuits Devices Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Fazel Sharifi, Atiyeh Panahi, Mohammad Hossein Moaiyeri, Keivan Navi |
High Performance CNFET-based Ternary Full Adders. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
23 | Omid Khorgami, Alireza Saberkari, Javad Bagheri, Seyed Mohsen Hosseini-Golgoo, Eduard Alarcón-Cot |
Extracting a closed-form I-V equation and noise analysis for CNFET in analog/RF applications. |
NEWCAS |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Zizhao Liu, Tao Pan, Song Jia, Uan Wang |
Design of a novel ternary SRAM sense amplifier using CNFET. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li |
Design of ternary pulsed reversible counter based on CNFET. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Sushma Srivastava, Surendra S. Rathod |
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Atiyeh Panahi, Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi |
CNFET-based approximate ternary adders for energy-efficient image processing applications. |
Microprocess. Microsystems |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 |
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Shu-Jen Han, Lan Wei |
CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Li Jiang 0002, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang |
CNFET-based high throughput register file architecture. |
ICCD |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas |
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. |
iNIS |
2016 |
DBLP DOI BibTeX RDF |
|
23 | YoungBae Kim, Qiang Tong, Ken Choi, Yunsik Lee |
Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics. |
ISOCC |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Li Jiang 0002, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty |
Defect tolerance for CNFET-based SRAMs. |
ITC |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi |
A novel low-energy CNFET-based full adder cell using pass-transistor logic. |
Int. J. High Perform. Syst. Archit. |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. |
Circuits Syst. Signal Process. |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. |
Circuits Syst. Signal Process. |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. |
J. Circuits Syst. Comput. |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Carmen G. Almudéver, Antonio Rubio 0001 |
Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections. |
Microelectron. Reliab. |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, Li Jiang 0002 |
On microarchitectural modeling for CNFET-based circuits. |
SoCC |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Rishika Sethi, Gaurav Soni |
Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder. |
SocProS (1) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 |
Jump test for metallic CNTs in CNFET-based SRAM. |
DAC |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Mojtaba Maleknejad, Reza Faghih Mirzaee, Keivan Navi, Akbar Dargahi |
A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors. |
J. Circuits Syst. Comput. |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Jyoti Sharma, Mohammad Samar Ansari, Jankiballabh Sharma |
Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET. |
ISED |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Shailendra Kumar Tripathi, Mohammad Samar Ansari |
Tunable Active Biquad Filter in ±0.9V 32 Nm CNFET. |
ISED |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta 0001 |
Optimal Redundancy Designs for CNFET-Based Circuits. |
ATS |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. |
ICECS |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram |
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh |
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. |
Int. J. High Perform. Syst. Archit. |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Saravana Maruthamuthu |
Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. |
Microelectron. J. |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Isha Garg, Prakhar Sharma |
Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell. |
WISES |
2013 |
DBLP BibTeX RDF |
|