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Publication years (Num. hits)
2004-2009 (20) 2010-2012 (22) 2013-2015 (17) 2016-2017 (16) 2018-2019 (17) 2020-2021 (17) 2022-2023 (15) 2024 (1)
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article(63) inproceedings(61) phdthesis(1)
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Found 125 publication records. Showing 125 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
169Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee Prospect of ballistic CNFET in high performance applications: Modeling and analysis. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
169Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee Modeling and analysis of circuit performance of ballistic CNFET. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
123Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi Performance assessment of analog circuits with carbon nanotube FET (CNFET). Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF analog, circuits
120Saurabh Sinha, Asha Balijepalli, Yu Cao A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Schottky barrier, analog design metrics, modeling, CNT
100Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong Carbon nanotube transistor compact model for circuit design and performance optimization. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF VerilogA, carbon nanotube FET, compact model, CNT, HSPICE
87Nishant Patil, Albert Lin, Jie Zhang 0007, H.-S. Philip Wong, Subhasish Mitra Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CNFET, carbon nanotube transistor, carbon nanotubes
80Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
80Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
67Hamidreza Hashempour, Fabrizio Lombardi Device Model for Ballistic CNFETs Using the First Conducting Band. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CNFET, charge density, self-consistent voltage, drain-source current, CAD, approximation, carbon nanotube, closed-form
67Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF RF performance, carbon nanotube FET (CNFET), modeling
63Jie Zhang 0007, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF CNT correlation, carbon nanotube, yield optimization, CNT
60Bao Liu 0001 Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
60Jie Zhang 0007, Nishant Patil, Arash Hazeghi, Subhasish Mitra Carbon nanotube circuits in the presence of carbon nanotube density variations. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CNT correlation, CNT density variation, carbon nanotube, CNT
60Jie Zhang 0007, Nishant Patil, Subhasish Mitra Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
60Wei Zhang 0012, Niraj K. Jha ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
50M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli Programmable logic circuits based on ambipolar CNFET. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CNFET, FPGA, PLA, carbon nanotube
47Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli Graphene based transistors: physics, status and future perspectives. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cnfet, gnr-fet., graphene, carbon nanotubes
23Ahmad Karimi, Keivan Navi The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology. Search on Bibsonomy Comput. Electr. Eng. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
23Zihao Yang, Minghui Yin, Yunxia You, Zhiqiang Li, Xin Liu, Weihua Zhang Design of a high performance CNFET 10T SRAM cell at 5nm technology node. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. Search on Bibsonomy ASP-DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Shivani Thakur, Srinivasu Bodapati Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor Technology. Search on Bibsonomy APCCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
23Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain A new low-power Dynamic-GDI full adder in CNFET technology. Search on Bibsonomy Integr. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Mehdi Takbiri, Keivan Navi, Reza Faghih Mirzaee Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement. Search on Bibsonomy IEEE Access The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 Taming Process Variations in CNFET for Efficient Last-Level Cache Design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa, Sanjay Vidhyadharan High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Mostafa Parvizi, Rana Haratian A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET Technology. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Abhay S. Vidhyadharan, Sanjay Vidhyadharan CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications. Search on Bibsonomy Wirel. Pers. Commun. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001 Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. Search on Bibsonomy ISLPED The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Zahra Heshmatpour, Lihong Zhang, Howard M. Heys Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits. Search on Bibsonomy ISQED The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Zahra Heshmatpour, Lihong Zhang, Howard M. Heys Robust CNFET Circuit Sizing Optimization. Search on Bibsonomy VLSI-DAT The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Panasa Srikanth, B. Srinivasu High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. Search on Bibsonomy VDAT The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
23Ramzi A. Jaber, Jihad Mohamad Jaam, Bilal N. Owaydat, Somaya Ali Al-Máadeed, Abdallah Kassem, Ali Massoud Haidar 0001 Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Hamidreza Uoosefian, Keivan Navi, Reza Faghih Mirzaee, Mehdi Hosseinzadeh 0001 Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Abhay S. Vidhyadharan, Sanjay Vidhyadharan An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
23Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Yuanqing Cheng, Huawei Li 0001, Xiaowei Li 0001 Taming Process Variations in CNFET for Efficient Last Level Cache Design. Search on Bibsonomy CoRR The full citation details ... 2021 DBLP  BibTeX  RDF
23Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. Search on Bibsonomy CoRR The full citation details ... 2021 DBLP  BibTeX  RDF
23Daniel Etiemble Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits". Search on Bibsonomy IEEE Access The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Akbar Doostaregan, Adib Abrishamifar Evaluating a Methodology for Designing CNFET-Based Ternary Circuits. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Amin Avan, Mojtaba Maleknejad, Keivan Navi High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4: 2 compressor design in CNFET technology. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey A 1-bit full adder using CNFET based dual chirality high speed domino logic. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Ramzi A. Jaber, Ahmad M. El-Hajj, Abdallah Kassem, Lina A. Nimri, Ali M. Haidar 0001 CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators. Search on Bibsonomy Microelectron. J. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Trapti Sharma, Laxmi Kumre CNFET based design of unbalanced ternary circuits using efficient shifting literals. Search on Bibsonomy Microelectron. J. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Ramzi A. Jaber, Ahmad M. El-Hajj, Ali M. Haidar 0001, Abdallah Kassem A Novel CNFET-Based Ternary to Binary Converter Design in Data Transmission. Search on Bibsonomy ICM The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Kaship Sheikh, Lan Wei Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit. Search on Bibsonomy ISQED The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
23Ramzi A. Jaber, Abdallah Kassem, Ahmad M. El-Hajj, Lina A. Nimri, Ali Massoud Haidar 0001 High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits. Search on Bibsonomy IEEE Access The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Akbar Doostaregan, Adib Abrishamifar A New Method for Design of CNFET-Based Quaternary Circuits. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Sepehr Tabrizchi, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh Novel CNFET ternary circuit techniques for high-performance and energy-efficient design. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. Search on Bibsonomy Comput. Electr. Eng. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad, Ali Bohlooli A new design method for imperfection-immune CNFET-based circuit design. Search on Bibsonomy Microelectron. J. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Soumitra Pal 0002, Vivek Gupta 0006, Aminul Islam 0002 Design of CNFET based power- and variability-aware nonvolatile RRAM cell. Search on Bibsonomy Microelectron. J. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Maryam Toulabinejad, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology. Search on Bibsonomy Microelectron. J. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001 Exploring emerging CNFET for efficient last level cache design. Search on Bibsonomy ASP-DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Li Jiang 0002, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang CNFET-Based High Throughput SIMD Architecture. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas Energy efficient design of CNFET-based multi-digit ternary adders. Search on Bibsonomy Microelectron. J. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy Energy Efficient Tri-State CNFET Ternary Logic Gates. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
23A. Nagalakshmi, Ch. Sirisha, D. N. Madhusudana Rao Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
23Srinithya Nagiri, Sananya Majumder, Riya, Aminul Islam Design of low power RRAM cell using CNFET. Search on Bibsonomy RAIT The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Kaship Sheikh, Lan Wei Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate Circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Kaship Sheikh, Lan Wei Using approximate circuits to counter process imperfections in CNFET based circuits. Search on Bibsonomy VLSI-DAT The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Zhengyang He, Kai Ren 0003, Jiayan Chen, Xinyi Dai, Zhao Pan 0001, Yuejun Zhang Design of Delayed Ternary PUF Circuit Based on CNFET. Search on Bibsonomy APCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Mokhtar Mohammadi Ghanatghestani, Behnam Ghavami, Honeya Salehpour A CNFET full adder cell design for high-speed arithmetic units. Search on Bibsonomy Turkish J. Electr. Eng. Comput. Sci. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi A novel high-performance and reliable multi-threshold CNFET full adder cell design. Search on Bibsonomy Int. J. High Perform. Syst. Archit. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Mohan Krishna Gopi Krishna, Arman Roohi, Ramtin Zand, Ronald F. DeMara Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Fazel Sharifi, Atiyeh Panahi, Mohammad Hossein Moaiyeri, Keivan Navi High Performance CNFET-based Ternary Full Adders. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
23Omid Khorgami, Alireza Saberkari, Javad Bagheri, Seyed Mohsen Hosseini-Golgoo, Eduard Alarcón-Cot Extracting a closed-form I-V equation and noise analysis for CNFET in analog/RF applications. Search on Bibsonomy NEWCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Zizhao Liu, Tao Pan, Song Jia, Uan Wang Design of a novel ternary SRAM sense amplifier using CNFET. Search on Bibsonomy ASICON The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li Design of ternary pulsed reversible counter based on CNFET. Search on Bibsonomy ASICON The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Sushma Srivastava, Surendra S. Rathod Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology. Search on Bibsonomy VDAT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Mohammad Eshghi Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Atiyeh Panahi, Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi CNFET-based approximate ternary adders for energy-efficient image processing applications. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Kaship Sheikh, Shu-Jen Han, Lan Wei CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Tianjian Li, Li Jiang 0002, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang CNFET-based high throughput register file architecture. Search on Bibsonomy ICCD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. Search on Bibsonomy iNIS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23YoungBae Kim, Qiang Tong, Ken Choi, Yunsik Lee Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics. Search on Bibsonomy ISOCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Tianjian Li, Li Jiang 0002, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty Defect tolerance for CNFET-based SRAMs. Search on Bibsonomy ITC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi A novel low-energy CNFET-based full adder cell using pass-transistor logic. Search on Bibsonomy Int. J. High Perform. Syst. Archit. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Mohammad Eshghi A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Mohammad Eshghi Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Mohammad Eshghi High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Carmen G. Almudéver, Antonio Rubio 0001 Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, Li Jiang 0002 On microarchitectural modeling for CNFET-based circuits. Search on Bibsonomy SoCC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Rishika Sethi, Gaurav Soni Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder. Search on Bibsonomy SocProS (1) The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 Jump test for metallic CNTs in CNFET-based SRAM. Search on Bibsonomy DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
23Mojtaba Maleknejad, Reza Faghih Mirzaee, Keivan Navi, Akbar Dargahi A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Jyoti Sharma, Mohammad Samar Ansari, Jankiballabh Sharma Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET. Search on Bibsonomy ISED The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Shailendra Kumar Tripathi, Mohammad Samar Ansari Tunable Active Biquad Filter in ±0.9V 32 Nm CNFET. Search on Bibsonomy ISED The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta 0001 Optimal Redundancy Designs for CNFET-Based Circuits. Search on Bibsonomy ATS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. Search on Bibsonomy ICECS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
23Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
23Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. Search on Bibsonomy Int. J. High Perform. Syst. Archit. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
23Saravana Maruthamuthu Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. Search on Bibsonomy Microelectron. J. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
23Isha Garg, Prakhar Sharma Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell. Search on Bibsonomy WISES The full citation details ... 2013 DBLP  BibTeX  RDF
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