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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 38 occurrences of 31 keywords
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Results
Found 32 publication records. Showing 32 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
84 | Jin-Fu Li 0001, Chih-Chiang Hsu |
Efficient Test Methodologies for Conditional Sum Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 319-324, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Wen-Chang Yeh, Chein-Wei Jen |
Generalized Earliest-First Fast Addition Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(10), pp. 1233-1242, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Carry-propagation adder, final adder, conditional-sum, carry-lookahead |
43 | Wen-Chang Yeh, Chein-Wei Jen |
High-Speed Booth Encoded Parallel Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 692-701, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding |
38 | Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao |
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 233-236, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage |
34 | Johannes Grad, James E. Stine |
New algorithms for carry propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 396-399, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder |
34 | Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan |
Circuit/architecture for low-power high-performance 32-bit adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 74-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit |
29 | Bernd Becker 0001, Reiner Kolla |
On the Construction of Optimal Time Adders (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 88, 5th Annual Symposium on Theoretical Aspects of Computer Science, Bordeaux, France, February 11-13, 1988, Proceedings, pp. 18-28, 1988, Springer, 3-540-18834-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Peter Kornerup |
Digit-Set Conversions: Generalizations and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(5), pp. 622-629, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
conditional sum addition, digit set conversion, multiplier recoding, nonredundant representation, on-the-fly conversion, parallel prefix computation, carry-lookahead techniques, computer arithmetic, digital arithmetic, multiplying circuits, redundant representation |
24 | Akhilesh Tyagi |
A Reduced-Area Scheme for Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1163-1170, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders |
24 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(9), pp. 1113-1121, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder |
24 | Stephen H. Unger |
Tree Realizations of Iterative Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(4), pp. 365-383, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders |
18 | Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
On the generation of area-time optimal testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1049-1066, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1986, Bratislava, Czechoslovakia, August 25-29, 1996, Proceedings, pp. 218-229, 1986, Springer, 3-540-16783-8. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
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16 | Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting |
Conditional sum-product networks: Modular probabilistic circuits via gate functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Approx. Reason. ![In: Int. J. Approx. Reason. 140, pp. 298-313, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting |
Conditional Sum-Product Networks: Imposing Structure on Deep Probabilistic Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PGM ![In: International Conference on Probabilistic Graphical Models, PGM 2020, 23-25 September 2020, Aalborg, Hotel Comwell Rebild Bakker, Skørping, Denmark., pp. 401-412, 2020, PMLR. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
16 | Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting |
Conditional Sum-Product Networks: Imposing Structure on Deep Probabilistic Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1905.08550, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Atin Mukherjee 0001, Anindya Sundar Dhar |
Real-time fault-tolerance with hot-standby topology for conditional sum adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(3-4), pp. 704-712, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Hiroki Hayashi, Satoshi Obana |
Protocols for evaluating conditional sum on encrypted data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISITA ![In: International Symposium on Information Theory and its Applications, ISITA 2014, Melbourne, Australia, October 26-29, 2014, pp. 148-152, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
16 | Atin Mukherjee 0001, Anindya Sundar Dhar |
Design of a Fault-Tolerant Conditional Sum Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings, pp. 217-222, 2012, Springer, 978-3-642-31493-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Kuo-Hsing Cheng, Shun-Wen Cheng |
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 22(4), pp. 975-989, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
16 | Hans Lindkvist, Per Andersson |
Techniques for Fast CMOS-based Conditional Sum Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 626-635, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
On the implementation of an efficient performance driven generator for conditional-sum-adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 402-407, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Bernd Becker 0001, Paul Molitor |
A performance driven generator for efficient testable conditional-sum-adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 370-375, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Norman M. Martin, Stephen P. Hufnagel |
Conditional-Sum Early Completion Adder Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(8), pp. 753-756, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
16 | Dhirubhai V. Kanani, Kenneth H. O'Keefe |
A Note on Conditional-Sum Addition for Base - 2 Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 22(6), pp. 626, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
16 | Joseph F. Kruy |
A fast conditional sum adder using carry bypass logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS Fall Joint Computing Conference (1) ![In: Proceedings of the 1965 fall joint computer conference, part I, AFIPS 1965 (Fall, part I), Las Vegas, Nevada, USA, November 30 - December 1, 1965, pp. 695-703, 1965, ACM, 978-1-4503-7885-7. The full citation details ...](Pics/full.jpeg) |
1965 |
DBLP DOI BibTeX RDF |
|
16 | Jack Sklansky |
Conditional-Sum Addition Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 9(2), pp. 226-231, 1960. The full citation details ...](Pics/full.jpeg) |
1960 |
DBLP DOI BibTeX RDF |
|
9 | James E. Stine, Christopher R. Babb, Vibhuti B. Dave |
Constant addition utilizing flagged prefix structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 668-671, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Neil Burgess |
The Flagged Prefix Adder and its Applications in Integer Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(3), pp. 263-271, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
prefix adders, absolute difference, end-around carry, computer arithmetic |
9 | Kiwon Choi, Minkyu Song |
Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 701-704, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri |
Fault-Tolerant High-Performance Cordic Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 164-172, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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9 | Takao Miura, Isamu Shioya |
Learning Concepts From Databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA ![In: Database and Expert Systems Applications, 9th International Conference, DEXA '98, Vienna, Austria, August 24-28, 1998, Proceedings, pp. 826-840, 1998, Springer, 3-540-64950-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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