Search results for "conditional-sum"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
84	Jin-Fu Li 0001, Chih-Chiang Hsu	Efficient Test Methodologies for Conditional Sum Adders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
43	Wen-Chang Yeh, Chein-Wei Jen	Generalized Earliest-First Fast Addition Algorithm.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Carry-propagation adder, final adder, conditional-sum, carry-lookahead
43	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
38	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
34	Johannes Grad, James E. Stine	New algorithms for carry propagation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder
34	Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
29	Bernd Becker 0001, Reiner Kolla	On the Construction of Optimal Time Adders (Extended Abstract).	STACS	1988	DBLP DOI BibTeX RDF
24	Peter Kornerup	Digit-Set Conversions: Generalizations and Application.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	conditional sum addition, digit set conversion, multiplier recoding, nonredundant representation, on-the-fly conversion, parallel prefix computation, carry-lookahead techniques, computer arithmetic, digital arithmetic, multiplying circuits, redundant representation
24	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
24	Bernd Becker 0001	Efficient Testing of Optimal Time Adders.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder
24	Stephen H. Unger	Tree Realizations of Iterative Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders
18	Bernd Becker 0001, Rolf Drechsler, Paul Molitor	On the generation of area-time optimal testable adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
18	Bernd Becker 0001	Efficient Testing of Optimal Time Adders (Extended Abstract).	MFCS	1986	DBLP DOI BibTeX RDF
16	Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting	Conditional sum-product networks: Modular probabilistic circuits via gate functions.	Int. J. Approx. Reason.	2022	DBLP DOI BibTeX RDF
16	Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting	Conditional Sum-Product Networks: Imposing Structure on Deep Probabilistic Architectures.	PGM	2020	DBLP BibTeX RDF
16	Xiaoting Shao, Alejandro Molina 0001, Antonio Vergari, Karl Stelzner, Robert Peharz, Thomas Liebig, Kristian Kersting	Conditional Sum-Product Networks: Imposing Structure on Deep Probabilistic Architectures.	CoRR	2019	DBLP BibTeX RDF
16	Atin Mukherjee 0001, Anindya Sundar Dhar	Real-time fault-tolerance with hot-standby topology for conditional sum adder.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
16	Hiroki Hayashi, Satoshi Obana	Protocols for evaluating conditional sum on encrypted data.	ISITA	2014	DBLP BibTeX RDF
16	Atin Mukherjee 0001, Anindya Sundar Dhar	Design of a Fault-Tolerant Conditional Sum Adder.	VDAT	2012	DBLP DOI BibTeX RDF
16	Kuo-Hsing Cheng, Shun-Wen Cheng	Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.	J. Inf. Sci. Eng.	2006	DBLP BibTeX RDF
16	Hans Lindkvist, Per Andersson	Techniques for Fast CMOS-based Conditional Sum Adders.	ICCD	1994	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Rolf Drechsler, Paul Molitor	On the implementation of an efficient performance driven generator for conditional-sum-adders.	EURO-DAC	1993	DBLP DOI BibTeX RDF
16	Bernd Becker 0001, Paul Molitor	A performance driven generator for efficient testable conditional-sum-adders.	EURO-DAC	1992	DBLP DOI BibTeX RDF
16	Norman M. Martin, Stephen P. Hufnagel	Conditional-Sum Early Completion Adder Logic.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF
16	Dhirubhai V. Kanani, Kenneth H. O'Keefe	A Note on Conditional-Sum Addition for Base - 2 Systems.	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
16	Joseph F. Kruy	A fast conditional sum adder using carry bypass logic.	AFIPS Fall Joint Computing Conference (1)	1965	DBLP DOI BibTeX RDF
16	Jack Sklansky	Conditional-Sum Addition Logic.	IRE Trans. Electron. Comput.	1960	DBLP DOI BibTeX RDF
9	James E. Stine, Christopher R. Babb, Vibhuti B. Dave	Constant addition utilizing flagged prefix structures.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
9	Neil Burgess	The Flagged Prefix Adder and its Applications in Integer Arithmetic.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	prefix adders, absolute difference, end-around carry, computer arithmetic
9	Kiwon Choi, Minkyu Song	Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
9	Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri	Fault-Tolerant High-Performance Cordic Processors.	DFT	2000	DBLP DOI BibTeX RDF
9	Takao Miura, Isamu Shioya	Learning Concepts From Databases.	DEXA	1998	DBLP DOI BibTeX RDF