Search results for "crossbar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Gang Han, Robert H. Klenke, James H. Aylor	Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	crossbar interconnection networks, simulation, performance evaluation, modeling, Multicomputer systems
97	Deng Pan, Yuanyuan Yang 0001	Providing flow based performance guarantees for buffered crossbar switches.	IPDPS	2008	DBLP DOI BibTeX RDF
97	Trevor N. Mudge, B. A. Makrucki	Probabilistic analysis of a crossbar switch.	ISCA	1982	DBLP BibTeX RDF
93	Hongbing Fan, Yu-Liang Wu	Crossbar based design schemes for switch boxes and programmable interconnection networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
86	Srinivasan Murali, Giovanni De Micheli	An Application-Specific Design Methodology for STbus Crossbar Generation.	DATE	2005	DBLP DOI BibTeX RDF
86	Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
86	Brian Webb, Ahmed Louri	A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	scalability, networks, parallel architectures, hypercubes, wavelength division multiplexing, Optical interconnections, crossbars, multiprocessor interconnection
83	Michel N. Victor, Aris K. Silzars, Edward S. Davidson	A freespace crossbar for multi-core processors.	ICS	2008	DBLP DOI BibTeX RDF	freespace crossbar, interconnect
76	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
76	Tad Hogg, Greg Snider	Defect-tolerant Logic with Nanoscale Crossbar Circuits.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault modeling, nanotechnology, molecular electronics, circuit reliability
76	Mohammed A. S. Khalid, Jonathan Rose	A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.	FPGA	1998	DBLP DOI BibTeX RDF
73	Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi	Read-out schemes for a CNTFET-based crossbar memory.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	carbon nanotube field effect transistor, crossbar design, read-out circuit, noise margin
73	Deng Pan, Yuanyuan Yang 0001	Localized asynchronous packet scheduling for buffered crossbar switches.	ANCS	2006	DBLP DOI BibTeX RDF	100% throughput, buffered crossbar switches, priority encoders, packet scheduling
66	Lotfi Mhamdi	A Partially Buffered Crossbar packet switching architecture and its scheduling.	ISCC	2008	DBLP DOI BibTeX RDF
66	Bernhard Quatember	Modular crossbar switch for large-scale multiprocessor systems: structure and implementation.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF
65	Haitham S. Hamza, Jitender S. Deogun	WDM optical interconnects: a balanced design approach.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	wavelength exchange optical crossbar (WOC), optical interconnects, wavelength division multiplexing (WDM), Clos network, crossbar switch, wavelength converter
63	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design
63	Nikos Chrysos, Giorgos Dimitrakopoulos	Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	VOQ crossbar scheduler, backlog-aware, deterministic service guarantees, round-robin arbiters, ASIC design
63	Tejpal Singh, Alexander Taubin	A Highly Scalable GALS Crossbar Using Token Ring Arbitration.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	crossbar design, scalability, latency, arbitration, token rings
62	Mohammed A. S. Khalid, Jonathan Rose	A novel and efficient routing architecture for multi-FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
58	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
56	Deng Pan, Yuanyuan Yang 0001	Localized Independent Packet Scheduling for Buffered Crossbar Switches.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
56	Mian Dong, Lin Zhong 0001	Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration.	DATE	2008	DBLP DOI BibTeX RDF
56	Minje Jun, Sungjoo Yoo, Eui-Young Chung	Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.	ASP-DAC	2008	DBLP DOI BibTeX RDF
56	Daeho Seo, Mithuna Thottethodi	Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and Torus Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
56	Byung-Joo Hong, Koon-Shik Cho, Seung-Hyun Kang, Suk-Yoon Lee, Jun Dong Cho	On the Configurable Multiprocessor SoC Platform with Crossbar Switch.	APCCAS	2006	DBLP DOI BibTeX RDF
56	Ted H. Szymanski, Honglin Wu, Amir Gourgy	Power complexity of multiplexer-based optoelectronic crossbar switches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
56	Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen	Comparison of synthesized bus and crossbar interconnection architectures.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
56	Qiang Duan, Xinghe Li, Linjie Zhang	Delay Performance Analysis for the Buffered Crossbar Switch .	AINA	2003	DBLP DOI BibTeX RDF
56	Panduka Wijetunga	High-performance crossbar design for system-on-chip.	IWSOC	2003	DBLP DOI BibTeX RDF
52	Jonathan S. Turner	Strong performance guarantees for asynchronous buffered crossbar scheduler.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	asynchronous crossbars, crossbar schedulers, routers, switches, performance guarantees
52	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
52	Simin He 0001, Shutao Sun, Hong-Tao Guan, Qiang Zheng, Youjian Zhao, Wen Gao 0001	On guaranteed smooth switching for buffered crossbar switches.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	scheduling, smoothness, switches, buffered crossbar
52	Dianxun Shuai	Crossbar Composite Spring-Nets to Optimize Multi-Agent Systems and Computer Networks.	ICIC (2)	2008	DBLP DOI BibTeX RDF	crossbar composite spring nets, multi-agent system, artificial intelligence, distributed problem solving, elastic nets
52	Choudhury A. Al Sayeed, Ashraf Matrawy	Guaranteed Maximal Matching for Input Buffered Crossbar Switches.	CNSR	2006	DBLP DOI BibTeX RDF	Guaranteed maximal matching, iSLIP, MWM, scheduling, perfect matching, crossbar switches
52	Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis	A reconfigurable hardware based embedded scheduler for buffered crossbar switches.	FPGA	2006	DBLP DOI BibTeX RDF	buffered crossbar fabric, scheduling, reconfigurable hardware
52	Paul-Peter Sotiriadis	Information storage capacity of crossbar switching networks.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	nanotube, network, memory, capacity, information, storage, nanotechnology, switching, device, crossbar, nanowire
51	Mark Holland, Scott Hauck	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
51	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.	DFT	2004	DBLP DOI BibTeX RDF
51	José Carlos Sancho, José Flich, Antonio Robles, Pedro López 0001, José Duato	Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks.	IPDPS	2002	DBLP DOI BibTeX RDF	InfiniBand network, virtual lanes, performance evaluation, routing algorithms, irregular topologies
48	Mark Holland, Scott Hauck	Improving performance and robustness of domain-specific CPLDs.	FPGA	2006	DBLP DOI BibTeX RDF	computer-aided design, system-on-a-chip, reconfigurable logic, CPLD, sparse crossbar
48	Prashanth Pappu, Jonathan S. Turner, Kenneth Wong	Work-conserving distributed schedulers for Terabit routers.	SIGCOMM	2004	DBLP DOI BibTeX RDF	CIOQ switches, crossbar scheduling, high performance routers, distributed scheduling
48	Kenneth Prager, Michael Vahey, William Farwell, James Whitney, Jon Lieb	A Fault Tolerant Signal Processing Computer.	DSN	2000	DBLP DOI BibTeX RDF	distributed crossbar, Fault detection, voting, single event upset, configurable computing, fault recovery
48	Peter G. Harrison, Naresh M. Patel	The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems	J. ACM	1990	DBLP DOI BibTeX RDF	flow-equivalent server, performance evaluation, Markov process, multistage interconnection network, crossbar switch, closed queuing network, delta network
45	Lotfi Mhamdi	On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
45	Jian Wang, Ted H. Szymanski	Power analysis of Input-Queued and Crosspoint-Queued crossbar switches.	CCECE	2009	DBLP DOI BibTeX RDF
45	Rajat Subhra Chakraborty, Swarup Bhunia	Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.	ISQED	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, CMOSNano, Asynchronous design
45	Alexander Kesselman, Kirill Kogan, Michael Segal 0001	Best Effort and Priority Queuing Policies for Buffered Crossbar Switches.	SIROCCO	2008	DBLP DOI BibTeX RDF
45	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
45	Chih-Chieh Chou, Cheng-Shang Chang, Duan-Shin Lee, Jay Cheng	A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
45	Paul-Peter Sotiriadis	Information Capacity of Nanowire Crossbar Switching Networks.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
45	Yungho Choi, Timothy Mark Pinkston	Crossbar Analysis for Optimal Deadlock Recovery Router Architecture.	IPPS	1997	DBLP DOI BibTeX RDF
42	Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos	A buffered crossbar-based chip interconnection framework supporting quality of service.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar
42	Simin He 0001, Shutao Sun, Wei Zhao, Yanfeng Zheng, Wen Gao 0001	Smooth switching problem in buffered crossbar switches.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	CICQ, scheduling, smoothness, switch, buffered crossbar
42	Yuval Tamir, Hsin-Chou Chi	Symmetric Crossbar Arbiters for VLSI Communication Switches.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	VLSI communication switches, symmetric crossbar arbiters, multistage interconnectionnetwork, switch arbitration policy, worst-case latency, circuitsimulation, performance evaluation, VLSI, circuit analysis computing, network simulations, critical path, multiprocessorinterconnection networks, system clock
42	Hee Yong Youn, Calvin Ching-Yuen Chen	A Comprehensive Performance Evaluation of Crossbar Networks.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor acceptanceprobability, rejected request handling, home memory concept, performance evaluation, performance evaluation, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory bandwidth, crossbar networks, bus arbitration
41	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
41	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
41	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
41	Norbert Eicker, Thomas Lippert	Scalable Ethernet Clos-Switches.	Euro-Par	2006	DBLP DOI BibTeX RDF
41	Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping Wu, Ronny Nitzsche, Guang R. Gao	A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
41	Jiho Chang, JongSu Yi, JunSeong Kim	A Switch Wrapper Design for SNA On-Chip-Network.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
41	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A methodology for design, modeling, and analysis of networks-on-chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
41	Ziqian Dong, Roberto Rojas-Cessa	Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
41	James R. Heath	A systems approach to molecular electronics.	ISLPED	2003	DBLP DOI BibTeX RDF
41	Prashanth Pappu, Jonathan S. Turner	Stress Resistant Scheduling Algorithms for CIOQ Switches.	ICNP	2003	DBLP DOI BibTeX RDF
41	Vipul Gupta, Eugen Schenfeld	Performance analysis of a synchronous, circuit-switched interconnection cached network.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
38	Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne	Towards an efficient switch architecture for high-radix switches.	ANCS	2006	DBLP DOI BibTeX RDF	arbiter efficiency, partitioned crossbar, switch organization
38	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
38	Jens Kargaard Madsen, Stephen I. Long	A High-Speed Interconnect Network Using Ternary Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication
38	Imadeldin O. Mahgoub, Ahmed K. Elmagarmid	Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	hierarchical multiprocessor systems, system bandwidth, hierarchically nonuniform reference, local requests, m-level system, crossbar system, performance evaluation, performance analysis, probability, multiprocessing systems, multiprocessorinterconnection networks, memory modules, multiple-bus system
35	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
35	Can Emre Koksal	On the Speedup Required to Achieve 100% Throughput for Multicast Over Crossbar Switches.	IWQoS	2008	DBLP DOI BibTeX RDF
35	Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins 0001, Wladek Olesinski	High-radix crossbar switches enabled by proximity communication.	SC	2008	DBLP DOI BibTeX RDF
35	Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai	Fast Fair Crossbar Scheduler for On-chip Router.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Michael Rosenblum, Constantine Caramanis, Michel X. Goemans, Vahid Tarokh	Approximating fluid schedules in crossbar packet-switches and Banyan networks.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	scheduling, graph theory, packet-switching, network calculus, combinatorics
35	Shinji Sumimoto, Kazuichi Ooe, Kouichi Kumon, Taisuke Boku, Mitsuhisa Sato, Akira Ukawa	A scalable communication layer for multi-dimensional hyper crossbar network using multiple gigabit ethernet.	ICS	2006	DBLP DOI BibTeX RDF
35	Raymond R. Hoare, Zhu Ding, Alex K. Jones	Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches.	SC	2006	DBLP DOI BibTeX RDF
35	David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler	Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
35	B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali	Efficient power model for crossbar interconnects.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
35	Eryk Laskowski, Marek Tudruj	Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.	FPL	2003	DBLP DOI BibTeX RDF
35	Eryk Laskowski	Program Structuring Heuristics for Parallel Systems Based on Multiple Crossbar Switches.	PPAM	2003	DBLP DOI BibTeX RDF
35	Tamaree Nalin, Isobe Takashi, Hiroaki Morino, Hitoshi Aida, Tadao Saito	A Scalable and High Capacity Router on Multi-Dimension Crossbar Switch Principle.	LCN	2001	DBLP DOI BibTeX RDF
35	Joydeep Ghosh, Anujan Varma, Naveen Krishnamurthy	Distributed control schemes for fast arbitration in large crossbar networks.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
32	Rahul Ratan, A. Yavuz Oruç	Self-Routing Quantum Sparse Crossbar Packet Concentrators.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	quantum packet concentrator, quantum switching, self-routing switch, sparse crossbar concentrator, Quantum circuits
32	Lotfi Mhamdi, Kees Goossens, Iria Varela Senin	Buffered Crossbar Fabrics Based on Networks on Chip.	CNSR	2010	DBLP DOI BibTeX RDF	Buffered crossbar fabric, Scheduling
32	Mehdi Baradaran Tahoori	BISM: built-in self map for hybrid crossbar nano-architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crossbar array, emerging nanotechnologies, logic mapping
32	Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee, Jungbum Heo, Kwangki Ryoo	Design of Multimedia SoC Platform with a Crossbar On-Chip Bus for Embedded Systems.	NCM (1)	2008	DBLP DOI BibTeX RDF	SoC platform, crossbar, on-chip bus
32	Cyriel Minkenberg, François Abel, Peter Müller 0002, Raj Krishnamurthy, Mitchell Gusat, Peter Dill, Ilias Iliadis, Ronald P. Luijten, B. Roe Hemenway, Richard Grzybowski, Enrico Schiattarella	Designing a Crossbar Scheduler for HPC Applications.	IEEE Micro	2006	DBLP DOI BibTeX RDF	crossbar scheduler, interconnection network, high-performance computing
32	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Topology aware mapping of logic functions onto nanowire-based crossbar architectures.	DAC	2006	DBLP DOI BibTeX RDF	logic synthesis, PLA, nanoelectronic, crossbar
32	José G. Delgado-Frias, Girish B. Ratanpal	A VLSI wrapped wave front arbiter for crossbar switches.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	interconnection network, crossbar switch, arbiter, network router
32	Weiming Guo, A. Yavuz Oruç	Regular Sparse Crossbar Concentrators.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	crosspoint complexity, regular sparse crossbar, Bipartite graph, concentrator
32	Frank T. Hady, Bernard L. Menezes	The Performance of Crossbar-Based Binary Hypercubes.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Binary hypercube, throughput, latency, wormhole routing, crossbar, distributed queue
32	Mark A. Franklin	VLSI Performance Comparison of Banyan and Crossbar Communications Networks.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	space-time product, VLSI, communication networks, Banyan network, multiprocessor networks, crossbar networks
31	Yan Pan, Prabhat Kumar 0002, John Kim, Gokhan Memik, Yu Zhang 0034, Alok N. Choudhary	Firefly: illuminating future network-on-chip with nanophotonics.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, topology, hierarchical network, nanophotonics
31	Xiangjie Ma, Xiaozhuo Gu, Lei He 0008, Julong Lan, Baisheng Zhang	Performance Study on the MPMS Fabric: A Novel Parallel and Distributed Switching System Architecture.	HPCC	2008	DBLP DOI BibTeX RDF
31	Konstantin Likharev	Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
31	John E. Savage	Computing at the Nanoscale.	DFT	2008	DBLP DOI BibTeX RDF
31	Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan	Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm.	ANCS	2008	DBLP DOI BibTeX RDF	distributed scheduling algorithm, parallel bipartite matching, reconfigurable mesh, mesh-of-trees, input-queued switch
31	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.	DATE	2007	DBLP DOI BibTeX RDF