Search results for "decap"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
154	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	Effective decap insertion in area-array SoC floorplan design.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	decap insertion, floorplan, Power supply noise
130	Takashi Enami, Masanori Hashimoto, Takashi Sato	Decoupling capacitance allocation for timing with statistical noise model and timing analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
127	Xueqian Zhao, Yonghe Guo, Zhuo Feng, Shiyan Hu	Parallel hierarchical cross entropy optimization for on-chip decap budgeting.	DAC	2010	DBLP DOI BibTeX RDF	parallel computing, cross-entropy, decoupling capacitor
114	Sanjay Pant, David T. Blaauw	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
114	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
110	Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie 0001, Narayanan Vijaykrishnan, Rong Luo	Leakage Optimized DECAP Design for FPGAs.	APCCAS	2006	DBLP DOI BibTeX RDF
110	Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-based approach to fast on-chip decap budgeting and minimization.	DAC	2005	DBLP DOI BibTeX RDF	on-chi, power/grid networks, simulation, optimization, IR drop, decoupling capacitor
104	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
94	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
94	Cheng Zhuo, Jiang Hu, Min Zhao 0001, Kangsheng Chen	Fast decap allocation based on algebraic multigrid.	ICCAD	2006	DBLP DOI BibTeX RDF
81	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
81	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Decoupling capacitor planning and sizing for noise and leakage reduction.	ICCAD	2006	DBLP DOI BibTeX RDF	3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction
65	Po-Yuan Chen, Che-Yu Liu, TingTing Hwang	Transition-aware decoupling-capacitor allocation in power noise reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
65	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
65	Hailin Jiang, Malgorzata Marek-Sadowska	Power-Gating Aware Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
65	Hao Yu 0001, Chunta Chu, Lei He 0001	Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.	DAC	2007	DBLP DOI BibTeX RDF
65	Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan	On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.	DAC	2007	DBLP DOI BibTeX RDF
61	Xiongfei Meng, Resve A. Saleh	Active decap design considerations for optimal supply noise reduction.	ISQED	2009	DBLP DOI BibTeX RDF
49	Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron	A study of decoupling capacitor effectiveness in power and ground grid networks.	ISQED	2009	DBLP DOI BibTeX RDF
49	Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan	Statistical decoupling capacitance allocation by efficient numerical quadrature method.	ISQED	2009	DBLP DOI BibTeX RDF
49	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
49	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
49	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan	Voltage drop reduction for on-chip power delivery considering leakage current variations.	ICCD	2007	DBLP DOI BibTeX RDF
49	Xiongfei Meng, Karim Arabi, Resve A. Saleh	A Novel Active Decoupling Capacitor Design in 90nm CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
49	Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu	Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.	ISCAS	2007	DBLP DOI BibTeX RDF
49	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
45	Camilo Andres Perez-Romero, Bram Weytjens, Dries Decap, Toon Swings, Jan Michiels, Dries De Maeyer, Kathleen Marchal	IAMBEE: a web-service for the identification of adaptive pathways from parallel evolved clonal populations.	Nucleic Acids Res.	2019	DBLP DOI BibTeX RDF
45	Dieter De Witte, Jan Van de Velde, Dries Decap, Michiel Van Bel, Pieter Audenaert, Piet Demeester, Bart Dhoedt, Klaas Vandepoele, Jan Fostier	BLSSpeller: exhaustive comparative discovery of conserved cis-regulatory elements.	Bioinform.	2015	DBLP DOI BibTeX RDF
45	Dries Decap, Joke Reumers, Charlotte Herzeel, Pascal Costanza, Jan Fostier	Halvade: scalable sequence analysis with MapReduce.	Bioinform.	2015	DBLP DOI BibTeX RDF
45	Dries Decap, Joke Reumers, Charlotte Herzeel, Pascal Costanza, Jan Fostier	Performance Analysis of a Parallel, Multi-node Pipeline for DNA Sequencing.	PPAM (2)	2015	DBLP DOI BibTeX RDF
45	Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.	ISQED	2005	DBLP DOI BibTeX RDF
44	Sanjay Pant, Eli Chiprout, David T. Blaauw	Power Grid Physics and Implications for CAD.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	R, L(di/dt), decap, locality, resonance, power supply networks
44	Sanjay Pant, Eli Chiprout	Power grid physics and implications for CAD.	DAC	2006	DBLP DOI BibTeX RDF	Ldi/dt, decap, locality, IR, resonance, power supply networks
33	Bardia Bozorgzadeh, Ali Afzali-Kusha	Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies.	VLSI Design	2009	DBLP DOI BibTeX RDF
33	Hailin Jiang, Malgorzata Marek-Sadowska	Power gating scheduling for power/ground noise reduction.	DAC	2008	DBLP DOI BibTeX RDF	scheduling, power gating, power supply noise
33	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Timing-Aware Power-Noise Reduction in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
33	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Multi-Objective Module Placement For 3-D System-On-Package.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
33	Jie Gu 0003, John Keane 0001, Chris H. Kim	Modeling and analysis of leakage induced damping effect in low voltage LSIs.	ISLPED	2006	DBLP DOI BibTeX RDF	damping effect, supply noise, gate leakage, subthreshold leakage
33	Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh	3D module placement for congestion and power noise reduction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	3D module placement, power noise reduction, congestion, system-on-package
33	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.	ISQED	2005	DBLP DOI BibTeX RDF
33	Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda	DEPOGIT: dense power-ground interconnect architecture for physical design integrity.	ASP-DAC	2004	DBLP DOI BibTeX RDF
33	Haihua Su, Kaushik Gala, Sachin S. Sapatnekar	Analysis and optimization of structured power/ground networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
33	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
29	Daijoon Hyun, Younggwang Jung, Youngsoo Shin	Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
29	Zhen Wang, Jun Xiao, Tao Chen, Long Chen 0016	DECap: Towards Generalized Explicit Caption Editing via Diffusion Mechanism.	CoRR	2023	DBLP DOI BibTeX RDF
29	Shivam Sood, Ge Sun, Peizhuo Li, Guillaume Sartoretti	DecAP: Decaying Action Priors for Accelerated Learning of Torque-Based Legged Locomotion Policies.	CoRR	2023	DBLP DOI BibTeX RDF
29	Wei Li, Linchao Zhu, Longyin Wen, Yi Yang 0001	DeCap: Decoding CLIP Latents for Zero-Shot Captioning via Text-Only Training.	CoRR	2023	DBLP DOI BibTeX RDF
29	Wei Li, Linchao Zhu, Longyin Wen, Yi Yang 0001	DeCap: Decoding CLIP Latents for Zero-Shot Captioning via Text-Only Training.	ICLR	2023	DBLP BibTeX RDF
29	Md. Mehedi Hasan 0007, Seyedhamed Ghavamnia, Michalis Polychronakis	Decap: Deprivileging Programs by Reducing Their Capabilities.	RAID	2022	DBLP DOI BibTeX RDF
29	Moumita Chakraborty, Amlan Chakrabarti, Partha Mitra, Debasri Saha, Krishnendu Guha	Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC.	VDAT	2016	DBLP DOI BibTeX RDF
29	Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah	A fully integrated charge sharing active decap scheme for power supply noise suppression.	SoCC	2015	DBLP DOI BibTeX RDF
29	Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen	Cost-effective decap selection for beyond die power integrity.	DATE	2014	DBLP DOI BibTeX RDF
29	Sheldon Logan, Matthew R. Guthaus	A decap placement methodology for reducing joule heating and temperature in PSN interconnect.	MWSCAS	2013	DBLP DOI BibTeX RDF
29	Xueqian Zhao, Yonghe Guo, Xiaodao Chen, Zhuo Feng, Shiyan Hu	Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
29	Yiran Chen 0001, Hai Li 0001, Kaushik Roy 0001, Cheng-Kok Koh	Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
29	Kenji Shimazaki, Takaaki Okumura	A minimum decap allocation technique based on simultaneous switching for nanoscale SoC.	CICC	2009	DBLP DOI BibTeX RDF
29	Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton	Charge-borrowing decap: A novel circuit for removal of local supply noise violations.	CICC	2009	DBLP DOI BibTeX RDF
29	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.	J. Inf. Sci. Eng.	2008	DBLP BibTeX RDF
29	Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Random Walk Guided Decap Embedding for Power/Ground Network Optimization.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
29	Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo	Power/Ground Network Optimization Considering Decap Leakage Currents.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
29	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	VLSI on-chip power/ground network optimization considering decap leakage currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Yiran Chen 0001, Hai Li 0001, Kaushik Roy 0001, Cheng-Kok Koh	Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies.	CICC	2005	DBLP DOI BibTeX RDF
27	Eli Chiprout	On-die power grids: the missing link.	DAC	2010	DBLP DOI BibTeX RDF	decap, voltage, locality, power grid, resonance
16	Charbel El Kaed, François-Gaël Ottogalli, Yves Denneulin	CBay: encheres pour le redéploiement de composants sur l'internet des machines.	UbiMob	2009	DBLP DOI BibTeX RDF	Machine-To-Machine, software components, auction, deployment
16	Cheng Zhuo, Jiang Hu, Min Zhao 0001, Kangsheng Chen	Power Grid Analysis and Optimization Using Algebraic Multigrid.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim	A unified methodology for power supply noise reduction in modern microarchitecture design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
16	Karim Arabi, Resve A. Saleh, Xiongfei Meng	Power Supply Noise in SoCs: Metrics, Management, and Measurement.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	metrics, DFT, power supply noise, deep-submicron, production test, power integrity
16	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
16	Wanping Zhang, Chung-Kuan Cheng	Incremental Power Impedance Optimization Using Vector Fitting Modeling.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo	Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.	ISQED	2006	DBLP DOI BibTeX RDF
16	Ravi Arora, Sachin Shrivastava	Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint!	APCCAS	2006	DBLP DOI BibTeX RDF
16	Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif	Benefits and Costs of Power-Gating Technique.	ICCD	2005	DBLP DOI BibTeX RDF
16	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.	ASP-DAC	2004	DBLP DOI BibTeX RDF
16	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	Optimal decoupling capacitor sizing and placement for standard-cell layout designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
16	Eli Chiprout	Early electrical wire projections and implications.	SLIP	2003	DBLP DOI BibTeX RDF