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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 50 occurrences of 38 keywords
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Results
Found 56 publication records. Showing 56 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
205 | Aswath Oruganti, Nagarajan Ranganathan |
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 766-769, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
139 | Yu Ching Chang, King Ho Tam, Lei He 0001 |
Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 137-142, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, buffer insertion |
133 | Michael Liu, Wei-Shen Wang, Michael Orshansky |
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 2-7, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
variability, yield, power minimization |
112 | Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps |
Leakage optimization using transistor-level dual threshold voltage cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 62-67, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
85 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 783-787, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, power dissipation, multiple voltages |
74 | Min Ni, Seda Ogrenci Memik |
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 610-613, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-Vth, leakage power optimization, gate sizing, clock skew scheduling |
67 | Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal |
Leakage power reduction using stress-enhanced layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 912-917, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance, mobility, layout, leakage, stress |
65 | Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee |
Leakage power optimization with dual-Vth library in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 202-207, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-Vth, optimization, high-level synthesis, leakage power |
49 | Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw |
STEEL: a technique for stress-enhanced standard cell library design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 691-697, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Yen-Te Ho, TingTing Hwang |
Low power design using dual threshold voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 205-208, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Frank Sill, Jiaxi You, Dirk Timmermann |
Design of mixed gates for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 263-268, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mixed gates, leakage current, threshold voltage, gate leakage |
39 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
36 | Lih-Yih Chiou, Shien-Chun Luo |
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1157-1160, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Yuanlin Lu, Vishwani D. Agrawal |
Statistical Leakage and Timing Optimization for Submicron Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 439-444, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Kazuei Hironaka, Hideharu Amano |
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011, pp. 404-409, 2011, IEEE Computer Society, 978-1-4577-1734-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
31 | Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan |
A low power scheduling method using dual Vdd and dual Vth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 684-687, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
Low-power dual Vth pseudo dual Vdd domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 273-277, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages |
31 | Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger |
Sleepy Stack Reduction of Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 148-158, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Frank Sill, Frank Grassert, Dirk Timmermann |
Low power gate-level design with mixed-Vth (MVT) techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 278-282, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MVT, leakage currents, threshold voltage |
26 | Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi |
Low power scheduling in high-level synthesis using dual-Vth library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 507-511, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Anne Lorraine S. Luna, John Richard E. Hizon, Louis P. Alarcón |
Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014, pp. 312-315, 2014, IEEE, 978-1-4799-5230-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Mohammad Mirzaei, Mahdi Mosaffa, Siamak Mohammadi, Jelena Trajkovic |
Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 327-334, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Masoud Rostami, Kartik Mohanram |
Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3), pp. 337-349, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Sudhakar S. Mande, Saurabh A. Chandorkar, A. N. Chandorkar |
Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(12), pp. 2357-2365, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino |
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(11), pp. 1608-1620, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Saraju P. Mohanty, Dhiraj K. Pradhan |
ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 6(2), pp. 8:1-8:26, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Junbo Yu, Qiang Zhou 0001, Gang Qu 0001, Jinian Bian |
Behavioral level dual-vth design for reduced leakage power with thermal awareness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 1261-1266, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Meng Tie, Haiying Dong, Tong Wang, Xu Cheng |
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 520-525, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Masoud Rostami, Kartik Mohanram |
Novel dual-Vth independent-gate FinFET circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 867-872, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos |
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 99-104, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yu Wang 0002, Xukai Shen, Rong Luo, Huazhong Yang |
Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 18(7), pp. 1243-1261, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Weixiang Shen, Yici Cai, Xianlong Hong |
Leakage power optimization for clock network using dual-Vth technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2769-2772, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Canh Quang Tran, Hiroshi Kawaguchi 0001, Takayasu Sakurai |
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(3), pp. 280-286, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Wei-Shen Wang, Michael Liu, Michael Orshansky |
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 2(1), pp. 1-7, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Azadeh Davoodi, Ankur Srivastava 0001 |
Probabilistic dual-Vth leakage optimization under variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 143-148, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
optimization, process variations, leakage, automatic synthesis |
26 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Statistical optimization of leakage power considering process variations using dual-Vth and sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 773-778, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, variability, leakage |
26 | Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai |
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 283-286, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Liqiong Wei, Kaushik Roy 0001, Cheng-Kok Koh |
Power minimization by simultaneous dual-Vth assignment and gate-sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, pp. 413-416, 2000, IEEE, 0-7803-5809-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram |
Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 274-281, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Shrikanth Ganapathy, Ramon Canal, Antonio González 0001, Antonio Rubio 0001 |
MODEST: a model for energy estimation under spatio-temporal variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 129-134, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dsm scaling, spatio-temporal variability, cache design |
18 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 323-328, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
18 | Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi |
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 673-679, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Swarup Bhunia, Kaushik Roy 0001 |
Low power design under parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 389-390, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Charbel J. Akl, Magdy A. Bayoumi |
Self-Sleep Buffer for Distributed MTCMOS Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 673-678, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yu Cao, Lawrence T. Clark |
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1866-1873, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1614-1624, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001 |
Tolerance to Small Delay Defects by Adaptive Clock Stretching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 244-252, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Se Hun Kim, Vincent John Mooney |
Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 367-372, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 |
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 619-624, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 267, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 257-262, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing |
18 | Yu Cao, Lawrence T. Clark |
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 658-663, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay, process variations, variability |
18 | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 |
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 415-420, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Bipul Chandra Paul, Cassondra Neau, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1269-1275, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 149-154, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ARM processor, Low power design, CVS, Dual-Vt |
18 | Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout |
Architecture and Design of a High Performance SRAM for SOC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 447-451, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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