Search results for "dual-Vth"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
205	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
139	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
133	Michael Liu, Wei-Shen Wang, Michael Orshansky	Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.	ISLPED	2004	DBLP DOI BibTeX RDF	variability, yield, power minimization
112	Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps	Leakage optimization using transistor-level dual threshold voltage cell library.	ISQED	2009	DBLP DOI BibTeX RDF
85	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
74	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
67	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Leakage power reduction using stress-enhanced layouts.	DAC	2008	DBLP DOI BibTeX RDF	performance, mobility, layout, leakage, stress
65	Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee	Leakage power optimization with dual-Vth library in high-level synthesis.	DAC	2005	DBLP DOI BibTeX RDF	dual-Vth, optimization, high-level synthesis, leakage power
49	Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw	STEEL: a technique for stress-enhanced standard cell library design.	ICCAD	2008	DBLP DOI BibTeX RDF
49	Yen-Te Ho, TingTing Hwang	Low power design using dual threshold voltage.	ASP-DAC	2004	DBLP DOI BibTeX RDF
44	Frank Sill, Jiaxi You, Dirk Timmermann	Design of mixed gates for leakage reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	mixed gates, leakage current, threshold voltage, gate leakage
39	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
36	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
31	Kazuei Hironaka, Hideharu Amano	Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.	ReConFig	2011	DBLP DOI BibTeX RDF
31	Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan	A low power scheduling method using dual Vdd and dual Vth.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
31	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
31	Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger	Sleepy Stack Reduction of Leakage Power.	PATMOS	2004	DBLP DOI BibTeX RDF
31	Frank Sill, Frank Grassert, Dirk Timmermann	Low power gate-level design with mixed-Vth (MVT) techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
26	Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi	Low power scheduling in high-level synthesis using dual-Vth library.	ISQED	2015	DBLP DOI BibTeX RDF
26	Anne Lorraine S. Luna, John Richard E. Hizon, Louis P. Alarcón	Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices.	APCCAS	2014	DBLP DOI BibTeX RDF
26	Mohammad Mirzaei, Mahdi Mosaffa, Siamak Mohammadi, Jelena Trajkovic	Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches.	DSD	2013	DBLP DOI BibTeX RDF
26	Masoud Rostami, Kartik Mohanram	Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
26	Sudhakar S. Mande, Saurabh A. Chandorkar, A. N. Chandorkar	Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
26	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
26	Saraju P. Mohanty, Dhiraj K. Pradhan	ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
26	Junbo Yu, Qiang Zhou 0001, Gang Qu 0001, Jinian Bian	Behavioral level dual-vth design for reduced leakage power with thermal awareness.	DATE	2010	DBLP DOI BibTeX RDF
26	Meng Tie, Haiying Dong, Tong Wang, Xu Cheng	Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement.	DATE	2010	DBLP DOI BibTeX RDF
26	Masoud Rostami, Kartik Mohanram	Novel dual-Vth independent-gate FinFET circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
26	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos	A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO.	VLSI Design	2010	DBLP DOI BibTeX RDF
26	Yu Wang 0002, Xukai Shen, Rong Luo, Huazhong Yang	Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation.	J. Circuits Syst. Comput.	2009	DBLP DOI BibTeX RDF
26	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Canh Quang Tran, Hiroshi Kawaguchi 0001, Takayasu Sakurai	Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
26	Wei-Shen Wang, Michael Liu, Michael Orshansky	Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
26	Azadeh Davoodi, Ankur Srivastava 0001	Probabilistic dual-Vth leakage optimization under variability.	ISLPED	2005	DBLP DOI BibTeX RDF	optimization, process variations, leakage, automatic synthesis
26	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Statistical optimization of leakage power considering process variations using dual-Vth and sizing.	DAC	2004	DBLP DOI BibTeX RDF	optimization, variability, leakage
26	Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai	Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.	ISLPED	2001	DBLP DOI BibTeX RDF
26	Liqiong Wei, Kaushik Roy 0001, Cheng-Kok Koh	Power minimization by simultaneous dual-Vth assignment and gate-sizing.	CICC	2000	DBLP DOI BibTeX RDF
22	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
18	Shrikanth Ganapathy, Ramon Canal, Antonio González 0001, Antonio Rubio 0001	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
18	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
18	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi	A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems.	ISQED	2009	DBLP DOI BibTeX RDF
18	Swarup Bhunia, Kaushik Roy 0001	Low power design under parameter variations.	SoCC	2008	DBLP DOI BibTeX RDF
18	Charbel J. Akl, Magdy A. Bayoumi	Self-Sleep Buffer for Distributed MTCMOS Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Yu Cao, Lawrence T. Clark	Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
18	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.	ICCAD	2006	DBLP DOI BibTeX RDF
18	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
18	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
18	Yu Cao, Lawrence T. Clark	Mapping statistical process variations toward circuit performance variability: an analytical modeling approach.	DAC	2005	DBLP DOI BibTeX RDF	delay, process variations, variability
18	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
18	Bipul Chandra Paul, Cassondra Neau, Kaushik Roy 0001	Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.	ITC	2004	DBLP DOI BibTeX RDF
18	Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw	An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.	ISVLSI	2003	DBLP DOI BibTeX RDF	ARM processor, Low power design, CVS, Dual-Vt
18	Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout	Architecture and Design of a High Performance SRAM for SOC Design.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF