Search results for "dual-supply"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
54	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Low-swing clock domino logic incorporating dual supply and dual threshold voltages.	DAC	2002	DBLP DOI BibTeX RDF	low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
53	Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
53	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
49	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
49	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
40	Nestoras Tzartzanis, William W. Walker	A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.	ICCD	2003	DBLP DOI BibTeX RDF
36	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
36	Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.	ISLPED	2005	DBLP DOI BibTeX RDF	dual-Vt/Vcc, flip-flop, hot spot, level converter
36	Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang	Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs.	ARVLSI	1999	DBLP DOI BibTeX RDF
35	Chunhong Chen, Ankur Srivastava 0001, Majid Sarrafzadeh	On gate level power optimization using dual-supply voltages.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
34	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.	ISLPED	2003	DBLP DOI BibTeX RDF	dual threshold, sizing, dual supply voltage, simultaneous
33	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
33	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.	ISLPED	2004	DBLP DOI BibTeX RDF	DSM leakage control and scaling trends, dual supply ALU design, low power techniques
33	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
32	Torsten Mahnke, Walter Stechele, Wolfgang Hoeld	Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.	PATMOS	2002	DBLP DOI BibTeX RDF
32	Chunhong Chen, Majid Sarrafzadeh	Provably good algorithm for low power consumption with dual supply voltages.	ICCAD	1999	DBLP DOI BibTeX RDF
28	Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume	Energy-efficient FPGA interconnect architecture design (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
24	Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli	Embedded EEPROM Speed Optimization Using System Power Supply Resources.	PATMOS	2004	DBLP DOI BibTeX RDF
24	Zohreh Karimi, Majid Sarrafzadeh	Power aware placement for FPGAs with dual supply voltages.	ISQED	2009	DBLP DOI BibTeX RDF
23	Siyuan Zhang, Zhicheng Wang, Min Tan 0004	A Dual-Channel Switching-Linear Series-Connected Hybrid Dynamic Power Supply with Dual-Supply LDOs for Thermo-Optical Tuning.	ICTA	2021	DBLP DOI BibTeX RDF
21	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
20	Qadeer Ahmad Khan, G. K. Siddhartha	A sequence independent power-on-reset circuit for multi-voltage systems.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
20	Tim Schoenauer, Jörg Berthold, Christoph Heer	Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.	PATMOS	2003	DBLP DOI BibTeX RDF
18	Steffen Klosterhalfen, Stefan Minner, Sean P. Willems	Strategic Safety Stock Placement in Supply Networks with Static Dual Supply.	Manuf. Serv. Oper. Manag.	2014	DBLP DOI BibTeX RDF
17	Chien-Cheng Yu, Weiping Wang, Bin-Da Liu	A new level converter for low-power applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Sherif A. Tawfik, Volkan Kursun	Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
17	Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael	A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process.	ISSCC	2007	DBLP DOI BibTeX RDF
17	Stephanie Augsburger, Borivoje Nikolic	Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.	ICCD	2002	DBLP DOI BibTeX RDF
16	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
16	Shaoxiong Hua, Gang Qu 0001	Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee.	CASES	2004	DBLP DOI BibTeX RDF	(m, k)-firm, low-power, dynamic voltage scaling, soft real-time
16	Shu-Shin Chin, Sangjin Hong, Suhwan Kim	Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.	ISVLSI	2004	DBLP DOI BibTeX RDF
12	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.	HiPEAC	2007	DBLP DOI BibTeX RDF
12	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan	A low power scheduling method using dual Vdd and dual Vth.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	Kai-Chiang Wu, Diana Marculescu	Power-aware soft error hardening via selective voltage scaling.	ICCD	2008	DBLP DOI BibTeX RDF
12	Antonio J. López-Martín, Alfonso Carlosena, Jaime Ramírez-Angulo, Ramón González Carvajal	Rail-to-rail tunable CMOS V-I converter.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Pak Kwong Chan, Grani Adiwena Hanasusanto, Hendrata B. Tan, Vincent Keng Sian Ong	A Micropower CMOS Amplifier for Portable Surface EMG Recording.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Adrian Kneip, David Bol	A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Yael Perlman, Yaacov Ozinci, Sara Westrich	Pricing decisions in a dual supply chain of organic and conventional agricultural products.	Ann. Oper. Res.	2022	DBLP DOI BibTeX RDF
11	Cristian Raducan, Marius Neag, Adrian-Gabriel Bajenaru	Automotive Switched-Capacitor DC-DC Converter With High BW Power Mirror and Dual Supply Driver.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Siyuan Zhang, Ken Xingze Wang, Min Tan 0004	An Eight-Channel Switching-Linear Hybrid Dynamic Regulator With Dual-Supply LDOs for Thermo-Optic Tuning.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
11	Ersin Alaybeyoglu, Deniz Özenli	Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
11	Mehrdad Morsali, Mohammad Hossein Moaiyeri	Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
11	Zhibing Liu, Geni Xu, Chi Zhou 0001, Huiru Chen	Retailer's decision selection with dual supply uncertainties under different reliability levels of serving the market.	RAIRO Oper. Res.	2020	DBLP DOI BibTeX RDF
11	Maliang Liu, Dengquan Li, Zhangming Zhu	A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
11	Ersin Alaybeyoglu, Hakan Kuntman	On the Performance Improvement of OTA in Sub-Threshold Region with Dual Supply.	ECCTD	2020	DBLP DOI BibTeX RDF
11	Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.	ISCAS	2020	DBLP DOI BibTeX RDF
11	Teng Xu 0001, Miodrag Potkonjak	Circuit power optimization using pipelining and dual-supply voltage assignment.	Integr.	2019	DBLP DOI BibTeX RDF
11	Hung-Hsien Wu, Chi-Hsiang Huang 0001, Chia-Ling Wei, Jih-Sheng Lai 0001	Bidirectional Single-Inductor Dual-Supply Converter With Automatic State-Transition for IoT Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
11	Yunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, Xuan Zhang 0001	SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors.	DAC	2018	DBLP DOI BibTeX RDF
11	Taehyung Kim, Sangshin Kwak	A Flexible Voltage Bus Converter for the 48-/12-V Dual Supply System in Electrified Vehicles.	IEEE Trans. Veh. Technol.	2017	DBLP DOI BibTeX RDF
11	S. Rasool Hosseini, Mehdi Saberi, Reza Lotfi	A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
11	Amit Chhabra, Yagnesh Dineshbhai Vaderiya	Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
11	Freddy Forero, Andres F. Gomez, Víctor H. Champac	Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
11	Teng Xu 0001, Miodrag Potkonjak	Pipelining for dual supply voltages.	PATMOS	2016	DBLP DOI BibTeX RDF
11	Teng Xu 0001, Miodrag Potkonjak	Retiming and dual-supply voltage based energy optimization for DSP applications.	ICASSP	2016	DBLP DOI BibTeX RDF
11	Freddy Forero, Andres F. Gomez, Víctor H. Champac	A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage.	LATS	2016	DBLP DOI BibTeX RDF
11	Ji-Zhong Shen, Liang Geng, Guang-Ping Xiang, Jianwei Liang	Low-power level converting flip-flop with a conditional clock technique in dual supply systems.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
11	Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya	Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
11	Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin	Logic block and design methodology for via-configurable structured ASIC using dual supply voltages.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
11	Chao Wang 0016, Jun Zhou 0017, Xin Liu 0015, Muthukumaraswamy Annamalai Arasu, Minkyu Je	A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation.	A-SSCC	2014	DBLP DOI BibTeX RDF
11	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
11	Xu Bai, Michitaka Kameyama	Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI.	ISMVL	2013	DBLP DOI BibTeX RDF
11	Timothy N. Miller, Renji Thomas, Radu Teodorescu	Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units.	IEEE Comput. Archit. Lett.	2012	DBLP DOI BibTeX RDF
11	Sang-Keun Han, KeeChan Park, Young-Hyun Jun, Bai-Sun Kong	High-Speed Low-Power Boosted Level Converters for Dual Supply Systems.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
11	Hoi-Jin Lee, Jong-Woo Kim, Tae Hee Han, Jae-Cheol Son, Jeong-Taek Kong, Bai-Sun Kong	Low-power dual-supply clock networks with clock gating and frequency doubling.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
11	Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya	2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm.	ESSCIRC	2012	DBLP DOI BibTeX RDF
11	Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.	ISQED	2012	DBLP DOI BibTeX RDF
11	Hoi-Jin Lee, Youngmin Shin, Jae Cheol Son, Tae Hee Han, Bai-Sun Kong	An efficient dual-supply design for low-power mobile systems.	ISOCC	2012	DBLP DOI BibTeX RDF
11	Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.	ESSCIRC	2011	DBLP DOI BibTeX RDF
11	Chun-Yen Tseng, Li-Wen Wang, Po-Chiun Huang	An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
11	Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Shekhar Borkar	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
11	Deming Chen, Jason Cong, Chen Dong 0003, Lei He 0001, Fei Li 0003, Chi-Chen Peng	Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
11	Sang-Keun Han, KeeChan Park, Bai-Sun Kong, Young-Hyun Jun	High-speed low-power bootstrapped level converter for dual supply systems.	APCCAS	2010	DBLP DOI BibTeX RDF
11	Peiyi Zhao, Jason McNeely, Pradeep Kumar Golconda, Soujanya Venigalla, Nan Wang, Magdy A. Bayoumi, Weidong Kuang, Luke Downey	Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
11	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output.	DSD	2009	DBLP DOI BibTeX RDF
11	Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Shekhar Borkar	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
11	Joo-Seong Kim, Bai-Sun Kong	Self-Resetting Level-Conversion Flip-Flops with Direct Output Feedback for Dual-Supply SoCs.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
11	Jente B. Kuang, Abraham Mathews, John Barth 0001, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata	An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.	ESSCIRC	2008	DBLP DOI BibTeX RDF
11	Fatemeh Aezinia, Ali Afzali-Kusha	Low power high performance level converter for dual supply voltage systems.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
11	Brian Campbell 0004, James Burnette, Naveen Javarappa, Vincent von Kaenel	Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology.	CICC	2007	DBLP DOI BibTeX RDF
11	Jürgen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel	Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.	ISSCC	2007	DBLP DOI BibTeX RDF
11	Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama	Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
11	Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi	Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
11	K. Sadeghi, M. Emadi, Farzan Farbiz	Using Level Restoring Method for Dual Supply Voltage.	VLSI Design	2006	DBLP DOI BibTeX RDF
11	Sanu K. Mathew, Mark A. Anders 0001, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar	A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
11	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Pseudo Dual Supply Voltage Domino Logic Design.	J. Low Power Electron.	2005	DBLP DOI BibTeX RDF
11	Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic	A shared-well dual-supply-voltage 64-bit ALU.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
11	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
11	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Torsten Mahnke, Sebastian Panenka, Martin Embacher, Walter Stechele, Wolfgang Hoeld	Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness.	ICECS	2002	DBLP DOI BibTeX RDF
11	Torsten Mahnke, Walter Stechele, Martin Embacher, Wolfgang Hoeld	Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis.	ICECS	2002	DBLP DOI BibTeX RDF
11	Thomas Olsson 0001, Pontus Åström, Peter Nilsson 0001	Dual supply-voltage scaling for reconfigurable SoC's.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
11	Kimiyoshi Usami, Mutsunori Igarashi	Low-power design methodology and applications utilizing dual supply voltages.	ASP-DAC	2000	DBLP DOI BibTeX RDF
11	Chingwei Yeh, Yin-Shuin Kang	A simulated annealing based method supporting dual supply voltages in standard cell placement.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
11	Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone	Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.	DAC	1999	DBLP DOI BibTeX RDF