Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
90 | Igor Lemberski, M. Ratniece |
XILINX4000 Architecture-Driven Synthesis for Speed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 476-480, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
84 | Andreas Jakoby, Rüdiger Reischuk |
Average Case Complexity of Unbounded Fanin Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the 15th Annual IEEE Conference on Computational Complexity, Florence, Italy, July 4-7, 2000, pp. 170-, 2000, IEEE Computer Society, 0-7695-0674-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
72 | Noga Alon, Richard Beigel |
Lower Bounds for Approximations by Low Degree Polynomials Over Zm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the 16th Annual IEEE Conference on Computational Complexity, Chicago, Illinois, USA, June 18-21, 2001, pp. 184-187, 2001, IEEE Computer Society, 0-7695-1053-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
72 | Igor Lemberski |
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 242-243, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | Milos Hrkic, John Lillis, Giancarlo Beraudo |
An Approach to Placement-Coupled Logic Replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2539-2551, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Zhong-Zhen Wu, Shih-Chieh Chang |
Multiple wire reconnections based on implication flow graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 939-952, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG) |
54 | Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng |
Technology mapping of timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 138-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits |
51 | Manindra Agrawal, Eric Allender, Samir Datta |
On TC0, AC0, and Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the Twelfth Annual IEEE Conference on Computational Complexity, Ulm, Germany, June 24-27, 1997, pp. 134-148, 1997, IEEE Computer Society, 0-8186-7907-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
TC/sup 0/, AC/sup 0/, function classes, constant-depth polynomial-size arithmetic circuits, unbounded fanin addition, multiplication gates, constant-depth arithmetic circuits, computational complexity, normal forms, arithmetic circuits, closure properties |
36 | Ran Raz |
Tensor-rank and lower bounds for arithmetic formulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 42nd ACM Symposium on Theory of Computing, STOC 2010, Cambridge, Massachusetts, USA, 5-8 June 2010, pp. 659-666, 2010, ACM, 978-1-4503-0050-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
homogenous circuits, multilinear circuits, tensor rank, lower bounds, arithmetic circuits |
36 | Neeraj Kayal, Nitin Saxena 0001 |
Polynomial Identity Testing for Depth 3 Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Complex. ![In: Comput. Complex. 16(2), pp. 115-138, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
13P99, Subject classification. 68Q15 |
36 | Neeraj Kayal, Nitin Saxena 0001 |
Polynomial Identity Testing for Depth 3 Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 21st Annual IEEE Conference on Computational Complexity (CCC 2006), 16-20 July 2006, Prague, Czech Republic, pp. 9-17, 2006, IEEE Computer Society, 0-7695-2596-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Milos Hrkic, John Lillis, Giancarlo Beraudo |
An approach to placement-coupled logic replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 711-716, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
placement, timing optimization, programmable logic, logic replication |
36 | Valentina Ciriani |
Synthesis of SPP three-level logic networks using affine spaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), pp. 1310-1323, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Stasys Jukna |
Finite Limits and Monotone Computations: The Lower Bounds Criterion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the Twelfth Annual IEEE Conference on Computational Complexity, Ulm, Germany, June 24-27, 1997, pp. 302-313, 1997, IEEE Computer Society, 0-8186-7907-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
real gates, lower bounds, threshold gates, monotone circuits |
36 | Klaus-Jörn Lange, Rolf Niedermeier |
Data-Independences of Parallel Random Access Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, 13th Conference, Bombay, India, December 15-17, 1993, Proceedings, pp. 104-113, 1993, Springer, 3-540-57529-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
33 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija |
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 920-930, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders |
30 | Pranjal Dutta, Prateek Dwivedi 0001, Nitin Saxena 0001 |
Deterministic identity testing paradigms for bounded top-fanin depth-4 circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.11325, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Pranjal Dutta, Nitin Saxena 0001 |
Separated borders: Exponential-gap fanin-hierarchy theorem for approximative depth-3 circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 63rd IEEE Annual Symposium on Foundations of Computer Science, FOCS 2022, Denver, CO, USA, October 31 - November 3, 2022, pp. 200-211, 2022, IEEE, 978-1-6654-5519-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Roope Kaivola, Neta Bar Kama |
Timed Causal Fanin Analysis for Symbolic Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: 22nd Formal Methods in Computer-Aided Design, FMCAD 2022, Trento, Italy, October 17-21, 2022, pp. 99-107, 2022, IEEE, 978-3-85448-053-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Pranjal Dutta, Prateek Dwivedi 0001, Nitin Saxena 0001 |
Deterministic Identity Testing Paradigms for Bounded Top-Fanin Depth-4 Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 36th Computational Complexity Conference, CCC 2021, July 20-23, 2021, Toronto, Ontario, Canada (Virtual Conference)., pp. 11:1-11:27, 2021, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-193-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Ning Ding 0001, Yanli Ren, Dawu Gu |
PAC Learning Depth-3 $\textrm{AC}^0$ Circuits of Bounded Top Fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ALT ![In: International Conference on Algorithmic Learning Theory, ALT 2017, 15-17 October 2017, Kyoto University, Kyoto, Japan, pp. 667-680, 2017, PMLR. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
30 | Neeraj Kayal, Chandan Saha 0001 |
Lower Bounds for Depth-Three Arithmetic Circuits with small bottom fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Complex. ![In: Comput. Complex. 25(2), pp. 419-454, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Neeraj Kayal, Chandan Saha 0001 |
Lower Bounds for Depth Three Arithmetic Circuits with Small Bottom Fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 30th Conference on Computational Complexity, CCC 2015, June 17-19, 2015, Portland, Oregon, USA, pp. 158-208, 2015, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-939897-81-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Neeraj Kayal, Chandan Saha 0001 |
Lower Bounds for Depth Three Arithmetic Circuits with small bottom fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR14, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
30 | Mrinal Kumar 0001, Shubhangi Saraf |
Lower Bounds for Depth 4 Homogenous Circuits with Bounded Top Fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR13, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
30 | Hua Xiang 0001, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri |
Depth controlled symmetric function fanin tree restructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013, pp. 585-591, 2013, IEEE, 978-1-4799-1069-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis 0001 |
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 2549-2552, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Ankit Gupta 0001, Pritish Kamath, Neeraj Kayal, Ramprasad Saptharishi |
An exponential lower bound for homogeneous depth four arithmetic circuits with bounded bottom fanin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR12, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
30 | Nitin Saxena 0001, C. Seshadhri 0001 |
Blackbox Identity Testing for Bounded Top-Fanin Depth-3 Circuits: The Field Doesn't Matter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Comput. ![In: SIAM J. Comput. 41(5), pp. 1285-1298, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
30 | Ankit Gupta 0001, Neeraj Kayal, Satyanarayana V. Lokam |
Reconstruction of Depth-4 Multilinear Circuits with Top fanin 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR11, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
30 | Alessandro Murgia, Roberto Tonelli, Steve Counsell, Giulio Concas, Michele Marchesi |
An Empirical Study of Refactoring in the Context of FanIn and FanOut Coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCRE ![In: 18th Working Conference on Reverse Engineering, WCRE 2011, Limerick, Ireland, October 17-20, 2011, pp. 372-376, 2011, IEEE Computer Society, 978-1-4577-1948-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Nitin Saxena 0001, C. Seshadhri 0001 |
Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 43rd ACM Symposium on Theory of Computing, STOC 2011, San Jose, CA, USA, 6-8 June 2011, pp. 431-440, 2011, ACM, 978-1-4503-0691-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Nitin Saxena 0001, C. Seshadhri 0001 |
Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR10, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
30 | Nitin Saxena 0001, C. Seshadhri 0001 |
Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1011.3234, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
30 | Yoichi Tomioka, Atsushi Takahashi 0001 |
A semi-monotonic routing method for fanin type Ball Grid Array packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1550-1553, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Rüdiger Reischuk |
Can large fanin circuits perform reliable computations in the presence of faults? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theor. Comput. Sci. ![In: Theor. Comput. Sci. 240(2), pp. 319-335, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Rüdiger Reischuk |
Can Large Fanin Circuits Perform Reliable Computations in the Presence of Noise? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR98, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
30 | Rüdiger Reischuk |
Can Large Fanin Circuits Perform Reliable Computations in the Presence of Noise ? ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, Third Annual International Conference, COCOON '97, Shanghai, China, August 20-22, 1997, Proceedings, pp. 72-81, 1997, Springer, 3-540-63357-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Lukas P. P. P. van Ginneken |
Fanin Ordering in Multi-Slot Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 44-47, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri |
SAT-based ATPG using multilevel compatible don't-cares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 24:1-24:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares |
18 | Manindra Agrawal, V. Vinay |
Arithmetic Circuits: A Chasm at Depth Four. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 49th Annual IEEE Symposium on Foundations of Computer Science, FOCS 2008, October 25-28, 2008, Philadelphia, PA, USA, pp. 67-75, 2008, IEEE Computer Society, 978-0-7695-3436-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Vikraman Arvind, Partha Mukhopadhyay |
The Monomial Ideal Membership Problem and Polynomial Identity Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 18th International Symposium, ISAAC 2007, Sendai, Japan, December 17-19, 2007, Proceedings, pp. 800-811, 2007, Springer, 978-3-540-77118-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Andreas Jakoby, Maciej Liskiewicz, Rüdiger Reischuk, Christian Schindelhauer |
Improving the Average Delay of Sorting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAMC ![In: Theory and Applications of Models of Computation, 4th International Conference, TAMC 2007, Shanghai, China, May 22-25, 2007, Proceedings, pp. 330-341, 2007, Springer, 978-3-540-72503-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman |
Robust Energy-Efficient Adder Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 16-28, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi |
A radix-10 SRT divider based on alternative BCD codings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 280-287, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Youngsoo Shin, Hyung-Ock Kim |
Cell-Based Semicustom Design of Zigzag Power Gating Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 527-532, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma |
Crosstalk analysis using reconvergence correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 79-83, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Hosung (Leo) Kim, John Lillis, Milos Hrkic |
Techniques for improved placement-coupled logic replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 211-216, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placement, timing optimization, programmable logic, logic replication |
18 | Ken Tseng, Mark Horowitz |
False coupling exploration in timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11), pp. 1795-1805, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Guy G. Lemieux, David M. Lewis |
Circuit design of routing switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 19-28, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Eelco Rouw, Jaap Hoekstra, Arthur H. M. van Roermund |
Spike correlation based learning for unsupervised neural lattice structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 425-428, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001 |
Extraction of functional regularity in datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1279-1296, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau |
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 185-188, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Aiguo Lu, Guenter Stenz, Frank M. Johannes |
Technology Mapping for Minimizing Gate and Routing Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 664-669, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Routing, Technology Mapping, Area Optimization |
18 | Torben Hagerup |
Simpler and Faster Dictionaries on the AC0 RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 25th International Colloquium, ICALP'98, Aalborg, Denmark, July 13-17, 1998, Proceedings, pp. 79-90, 1998, Springer, 3-540-64781-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken |
Efficient orthonormality testing for synthesis with pass-transistor selectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 256-263, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|