Search results for "fanin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Igor Lemberski, M. Ratniece	XILINX4000 Architecture-Driven Synthesis for Speed.	FPL	1998	DBLP DOI BibTeX RDF
84	Andreas Jakoby, Rüdiger Reischuk	Average Case Complexity of Unbounded Fanin Circuits.	CCC	2000	DBLP DOI BibTeX RDF
72	Noga Alon, Richard Beigel	Lower Bounds for Approximations by Low Degree Polynomials Over Zm.	CCC	2001	DBLP DOI BibTeX RDF
72	Igor Lemberski	Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
54	Milos Hrkic, John Lillis, Giancarlo Beraudo	An Approach to Placement-Coupled Logic Replication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
54	Zhong-Zhen Wu, Shih-Chieh Chang	Multiple wire reconnections based on implication flow graph.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
54	Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
51	Manindra Agrawal, Eric Allender, Samir Datta	On TC0, AC0, and Arithmetic Circuits.	CCC	1997	DBLP DOI BibTeX RDF	TC/sup 0/, AC/sup 0/, function classes, constant-depth polynomial-size arithmetic circuits, unbounded fanin addition, multiplication gates, constant-depth arithmetic circuits, computational complexity, normal forms, arithmetic circuits, closure properties
36	Ran Raz	Tensor-rank and lower bounds for arithmetic formulas.	STOC	2010	DBLP DOI BibTeX RDF	homogenous circuits, multilinear circuits, tensor rank, lower bounds, arithmetic circuits
36	Neeraj Kayal, Nitin Saxena 0001	Polynomial Identity Testing for Depth 3 Circuits.	Comput. Complex.	2007	DBLP DOI BibTeX RDF	13P99, Subject classification. 68Q15
36	Neeraj Kayal, Nitin Saxena 0001	Polynomial Identity Testing for Depth 3 Circuits.	CCC	2006	DBLP DOI BibTeX RDF
36	Milos Hrkic, John Lillis, Giancarlo Beraudo	An approach to placement-coupled logic replication.	DAC	2004	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
36	Valentina Ciriani	Synthesis of SPP three-level logic networks using affine spaces.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
36	Stasys Jukna	Finite Limits and Monotone Computations: The Lower Bounds Criterion.	CCC	1997	DBLP DOI BibTeX RDF	real gates, lower bounds, threshold gates, monotone circuits
36	Klaus-Jörn Lange, Rolf Niedermeier	Data-Independences of Parallel Random Access Machines.	FSTTCS	1993	DBLP DOI BibTeX RDF
33	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
30	Pranjal Dutta, Prateek Dwivedi 0001, Nitin Saxena 0001	Deterministic identity testing paradigms for bounded top-fanin depth-4 circuits.	CoRR	2023	DBLP DOI BibTeX RDF
30	Pranjal Dutta, Nitin Saxena 0001	Separated borders: Exponential-gap fanin-hierarchy theorem for approximative depth-3 circuits.	FOCS	2022	DBLP DOI BibTeX RDF
30	Roope Kaivola, Neta Bar Kama	Timed Causal Fanin Analysis for Symbolic Circuit Simulation.	FMCAD	2022	DBLP DOI BibTeX RDF
30	Pranjal Dutta, Prateek Dwivedi 0001, Nitin Saxena 0001	Deterministic Identity Testing Paradigms for Bounded Top-Fanin Depth-4 Circuits.	CCC	2021	DBLP DOI BibTeX RDF
30	Ning Ding 0001, Yanli Ren, Dawu Gu	PAC Learning Depth-3 $\textrm{AC}^0$ Circuits of Bounded Top Fanin.	ALT	2017	DBLP BibTeX RDF
30	Neeraj Kayal, Chandan Saha 0001	Lower Bounds for Depth-Three Arithmetic Circuits with small bottom fanin.	Comput. Complex.	2016	DBLP DOI BibTeX RDF
30	Neeraj Kayal, Chandan Saha 0001	Lower Bounds for Depth Three Arithmetic Circuits with Small Bottom Fanin.	CCC	2015	DBLP DOI BibTeX RDF
30	Neeraj Kayal, Chandan Saha 0001	Lower Bounds for Depth Three Arithmetic Circuits with small bottom fanin.	Electron. Colloquium Comput. Complex.	2014	DBLP BibTeX RDF
30	Mrinal Kumar 0001, Shubhangi Saraf	Lower Bounds for Depth 4 Homogenous Circuits with Bounded Top Fanin.	Electron. Colloquium Comput. Complex.	2013	DBLP BibTeX RDF
30	Hua Xiang 0001, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri	Depth controlled symmetric function fanin tree restructure.	ICCAD	2013	DBLP DOI BibTeX RDF
30	Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis 0001	Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.	ISCAS	2013	DBLP DOI BibTeX RDF
30	Ankit Gupta 0001, Pritish Kamath, Neeraj Kayal, Ramprasad Saptharishi	An exponential lower bound for homogeneous depth four arithmetic circuits with bounded bottom fanin.	Electron. Colloquium Comput. Complex.	2012	DBLP BibTeX RDF
30	Nitin Saxena 0001, C. Seshadhri 0001	Blackbox Identity Testing for Bounded Top-Fanin Depth-3 Circuits: The Field Doesn't Matter.	SIAM J. Comput.	2012	DBLP DOI BibTeX RDF
30	Ankit Gupta 0001, Neeraj Kayal, Satyanarayana V. Lokam	Reconstruction of Depth-4 Multilinear Circuits with Top fanin 2.	Electron. Colloquium Comput. Complex.	2011	DBLP BibTeX RDF
30	Alessandro Murgia, Roberto Tonelli, Steve Counsell, Giulio Concas, Michele Marchesi	An Empirical Study of Refactoring in the Context of FanIn and FanOut Coupling.	WCRE	2011	DBLP DOI BibTeX RDF
30	Nitin Saxena 0001, C. Seshadhri 0001	Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter.	STOC	2011	DBLP DOI BibTeX RDF
30	Nitin Saxena 0001, C. Seshadhri 0001	Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter.	Electron. Colloquium Comput. Complex.	2010	DBLP BibTeX RDF
30	Nitin Saxena 0001, C. Seshadhri 0001	Blackbox identity testing for bounded top fanin depth-3 circuits: the field doesn't matter	CoRR	2010	DBLP BibTeX RDF
30	Yoichi Tomioka, Atsushi Takahashi 0001	A semi-monotonic routing method for fanin type Ball Grid Array packages.	APCCAS	2008	DBLP DOI BibTeX RDF
30	Rüdiger Reischuk	Can large fanin circuits perform reliable computations in the presence of faults?	Theor. Comput. Sci.	2000	DBLP DOI BibTeX RDF
30	Rüdiger Reischuk	Can Large Fanin Circuits Perform Reliable Computations in the Presence of Noise?	Electron. Colloquium Comput. Complex.	1998	DBLP BibTeX RDF
30	Rüdiger Reischuk	Can Large Fanin Circuits Perform Reliable Computations in the Presence of Noise ?	COCOON	1997	DBLP DOI BibTeX RDF
30	Lukas P. P. P. van Ginneken	Fanin Ordering in Multi-Slot Timing Analysis.	ICCD	1992	DBLP DOI BibTeX RDF
18	Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri	SAT-based ATPG using multilevel compatible don't-cares.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares
18	Manindra Agrawal, V. Vinay	Arithmetic Circuits: A Chasm at Depth Four.	FOCS	2008	DBLP DOI BibTeX RDF
18	Vikraman Arvind, Partha Mukhopadhyay	The Monomial Ideal Membership Problem and Polynomial Identity Testing.	ISAAC	2007	DBLP DOI BibTeX RDF
18	Andreas Jakoby, Maciej Liskiewicz, Rüdiger Reischuk, Christian Schindelhauer	Improving the Average Delay of Sorting.	TAMC	2007	DBLP DOI BibTeX RDF
18	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
18	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
18	Youngsoo Shin, Hyung-Ock Kim	Cell-Based Semicustom Design of Zigzag Power Gating Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
18	Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma	Crosstalk analysis using reconvergence correlation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
18	Hosung (Leo) Kim, John Lillis, Milos Hrkic	Techniques for improved placement-coupled logic replication.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
18	Ken Tseng, Mark Horowitz	False coupling exploration in timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
18	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
18	Eelco Rouw, Jaap Hoekstra, Arthur H. M. van Roermund	Spike correlation based learning for unsupervised neural lattice structures.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta 0001	Extraction of functional regularity in datapath circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
18	Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau	Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
18	Aiguo Lu, Guenter Stenz, Frank M. Johannes	Technology Mapping for Minimizing Gate and Routing Area.	DATE	1998	DBLP DOI BibTeX RDF	Routing, Technology Mapping, Area Optimization
18	Torben Hagerup	Simpler and Faster Dictionaries on the AC0 RAM.	ICALP	1998	DBLP DOI BibTeX RDF
18	Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken	Efficient orthonormality testing for synthesis with pass-transistor selectors.	ICCAD	1995	DBLP DOI BibTeX RDF