Search results for "gated-clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
124	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
116	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
96	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
90	Jaewon Oh, Massoud Pedram	Gated Clock Routing Minimizing the Switched Capacitance.	DATE	1998	DBLP DOI BibTeX RDF	gated clock routing, low power
78	Jaewon Oh, Massoud Pedram	Gated clock routing for low-power microprocessor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
73	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
68	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
65	Gaetano Palumbo, Francesco Pappalardo 0002, S. Sannella	Evaluation on power reduction applying gated clock approaches.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
65	Luca Benini, Giovanni De Micheli	Automatic synthesis of low-power gated-clock finite-state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
63	Nithya Raghavan, Venkatesh Akella, Smita Bakshi	Automatic Insertion of Gated Clocks at Register Transfer Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
51	Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
48	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
47	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
40	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
38	Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen	Pipelining technique for energy-aware datapaths.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
38	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.	ED&TC	1997	DBLP DOI BibTeX RDF
32	Christos A. Papachristou, Mehrdad Nourani, Mark Spining	A multiple clocking scheme for low-power RTL design.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
31	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira 0001, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
31	Luca Benini, Giovanni De Micheli	Synthesis of low-power selectively-clocked systems from high-level specification.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	low power, high-level synthesis, gated clock
31	Sumit Roy 0003, Prithviraj Banerjee, Majid Sarrafzadeh	Partitioning sequential circuits for low power.	VLSI Design	1998	DBLP DOI BibTeX RDF	low-power, gated-clock, sequential synthesis
31	Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh	Activity-driven clock design for low power circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
30	Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin	Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
30	Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan	Analysis and optimization of NBTI induced clock skew in gated clock trees.	DATE	2009	DBLP DOI BibTeX RDF
21	Alak Majumder	Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
21	Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura	Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering.	MWSCAS	2017	DBLP DOI BibTeX RDF
21	Bipasha Nath, Alak Majumder	Binary Counter Based Gated Clock Tree for Integrated CPU Chip.	iNIS	2017	DBLP DOI BibTeX RDF
21	Minghao Lin, Heming Sun, Shinji Kimura	Power-efficient and slew-aware three dimensional gated clock tree synthesis.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
21	Pritam Bhattacharjee, Alak Majumder	LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder.	iNIS	2016	DBLP DOI BibTeX RDF
21	Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin	Low-power gated clock tree optimization for three-dimensional integrated circuits.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
21	Ashutosh Chakraborty, David Z. Pan	Skew Management of NBTI Impacted Gated Clock Trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
21	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham	Fast Power- and Slew-Aware Gated Clock Tree Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
21	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
21	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
21	Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan	Synthesis of Anti-Aging Gated Clock Designs.	J. Inf. Sci. Eng.	2009	DBLP BibTeX RDF
21	Raymond E. Barnett, Jin Liu 0004	An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
21	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Low Power Gated Clock Tree Driven Placement.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
21	Walter Aloisi, Rosario Mita	Gated-Clock Design of Linear-Feedback Shift Registers.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
21	Raymond E. Barnett, Jin Liu 0004	An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control.	CICC	2007	DBLP DOI BibTeX RDF
21	Bengt Oelmann, Mattias O'Nils	Asynchronous control of low-power gated-clock finite-state machines.	ICECS	1999	DBLP DOI BibTeX RDF
21	Jaewon Oh, Massoud Pedram	Power Reduction in Microprocessor Chips by Gated Clock Routing.	ASP-DAC	1998	DBLP DOI BibTeX RDF
21	Michele Favalli, Luca Benini, Giovanni De Micheli	Design for Testability of Gated-Clock FSMs.	ED&TC	1996	DBLP DOI BibTeX RDF
21	Luca Benini, Giovanni De Micheli	Transformation and synthesis of FSMs for low-power gated-clock implementation.	ISLPD	1995	DBLP DOI BibTeX RDF
21	Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli	A Verification Technique for Gated Clock.	DAC	1993	DBLP DOI BibTeX RDF
19	Ke Xu 0014, Chiu-sing Choy	A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
19	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, design, verification
19	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai	3D graphics LSI core for mobile phone "Z3D".	Graphics Hardware	2003	DBLP DOI BibTeX RDF	graphics accelerator, graphics hardware, rendering hardware
19	Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi	Low power FSM design using Huffman-style encoding.	ED&TC	1997	DBLP DOI BibTeX RDF
15	Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu	Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
15	Philippe Grosse, Yves Durand, Paul Feautrier	Power Modeling of a NoC Based Design for High Speed Telecommunication Systems.	PATMOS	2006	DBLP DOI BibTeX RDF
15	Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen	Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.	ICME	2006	DBLP DOI BibTeX RDF
15	Yuichi Nakamura 0002, Takeshi Yoshimura	A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu	Behavioral-level partitioning for low power design in control-dominated application.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
15	Frank P. Higgins, Rajagopalan Srinivasan	BSM2: Next Generation Boundary-Scan Master.	VTS	2000	DBLP DOI BibTeX RDF