Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
124 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity and register placement aware gated clock network design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 182-189, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gated clock tree, low power, placement |
116 | Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 714-719, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
96 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Gate planning during placement for gated clock network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 128-133, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
90 | Jaewon Oh, Massoud Pedram |
Gated Clock Routing Minimizing the Switched Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 692-697, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
gated clock routing, low power |
78 | Jaewon Oh, Massoud Pedram |
Gated clock routing for low-power microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), pp. 715-722, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
73 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 383-388, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
68 | Wei-Chung Chao, Wai-Kei Mak |
Low-power gated and buffered clock network construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 20:1-20:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, buffer, clock gating, Clock tree, zero-skew |
65 | Gaetano Palumbo, Francesco Pappalardo 0002, S. Sannella |
Evaluation on power reduction applying gated clock approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 85-88, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
65 | Luca Benini, Giovanni De Micheli |
Automatic synthesis of low-power gated-clock finite-state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6), pp. 630-643, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
63 | Nithya Raghavan, Venkatesh Akella, Smita Bakshi |
Automatic Insertion of Gated Clocks at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 48-54, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers |
Low-Power Embedded Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 600-605, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles |
48 | Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
A Gated Clock Scheme for Low Power Testing of Logic Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 89-99, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test-per-scan, test-per-clock, low power design, low power test |
47 | Sanghyeon Baeg |
Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12), pp. 2215-2221, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 253-258, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
A Gated Clock Scheme for Low Power Scan-Based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 87-89, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1218-1221, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 514-520, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Christos A. Papachristou, Mehrdad Nourani, Mark Spining |
A multiple clocking scheme for low-power RTL design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(2), pp. 266-276, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira 0001, Marcelino B. Santos |
Low Power BIST by Filtering Non-Detecting Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 193-202, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low power BIST, low energy consumption, LFSR, gated clock |
31 | Luca Benini, Giovanni De Micheli |
Synthesis of low-power selectively-clocked systems from high-level specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 311-321, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low power, high-level synthesis, gated clock |
31 | Sumit Roy 0003, Prithviraj Banerjee, Majid Sarrafzadeh |
Partitioning sequential circuits for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 212-217, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low-power, gated-clock, sequential synthesis |
31 | Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh |
Activity-driven clock design for low power circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 62-65, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree |
30 | Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 283-288, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan |
Analysis and optimization of NBTI induced clock skew in gated clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 296-299, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Alak Majumder |
Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 13(4), pp. 576-579, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura |
Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 1200-1203, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Bipasha Nath, Alak Majumder |
Binary Counter Based Gated Clock Tree for Integrated CPU Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017, pp. 229-233, 2017, IEEE, 978-1-5386-1356-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Minghao Lin, Heming Sun, Shinji Kimura |
Power-efficient and slew-aware three dimensional gated clock tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Pritam Bhattacharjee, Alak Majumder |
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 250-254, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin |
Low-power gated clock tree optimization for three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-6275-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Ashutosh Chakraborty, David Z. Pan |
Skew Management of NBTI Impacted Gated Clock Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6), pp. 918-927, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham |
Fast Power- and Slew-Aware Gated Clock Tree Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(11), pp. 2094-2103, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(12), pp. 1639-1648, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Ashutosh Chakraborty, David Z. Pan |
Skew management of NBTI impacted gated clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 127-133, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock skew, clock gating, NBTI |
21 | Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan |
Synthesis of Anti-Aging Gated Clock Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 25(6), pp. 1651-1670, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
21 | Raymond E. Barnett, Jin Liu 0004 |
An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(8), pp. 1808-1815, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Low Power Gated Clock Tree Driven Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2), pp. 595-603, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Walter Aloisi, Rosario Mita |
Gated-Clock Design of Linear-Feedback Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 55-II(6), pp. 546-550, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Raymond E. Barnett, Jin Liu 0004 |
An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 393-396, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Bengt Oelmann, Mattias O'Nils |
Asynchronous control of low-power gated-clock finite-state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 915-918, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Jaewon Oh, Massoud Pedram |
Power Reduction in Microprocessor Chips by Gated Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 313-318, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Michele Favalli, Luca Benini, Giovanni De Micheli |
Design for Testability of Gated-Clock FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, pp. 589-597, 1996, IEEE Computer Society, 0-8186-7423-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Luca Benini, Giovanni De Micheli |
Transformation and synthesis of FSMs for low-power gated-clock implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPD ![In: Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, pp. 21-26, 1995, ACM, 0-89791-744-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli |
A Verification Technique for Gated Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 123-127, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Ke Xu 0014, Chiu-sing Choy |
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(3), pp. 363-374, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Kevin Camera, Robert W. Brodersen |
An integrated debugging environment for FPGA computing platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 260, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, FPGA, design, verification |
19 | Weixiang Shen, Yici Cai, Xianlong Hong |
Leakage power optimization for clock network using dual-Vth technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2769-2772, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai |
3D graphics LSI core for mobile phone "Z3D". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the 2003 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, San Diego, California, USA, July 26-27, 2003, pp. 60-67, 2003, Eurographics Association, 1-58113-739-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
graphics accelerator, graphics hardware, rendering hardware |
19 | Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi |
Low power FSM design using Huffman-style encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 521-525, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 489-500, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Philippe Grosse, Yves Durand, Paul Feautrier |
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 157-168, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen |
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 281-284, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yuichi Nakamura 0002, Takeshi Yoshimura |
A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 628-631, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu |
Behavioral-level partitioning for low power design in control-dominated application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 156-161, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Frank P. Higgins, Rajagopalan Srinivasan |
BSM2: Next Generation Boundary-Scan Master. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 67-72, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|