Search results for "hazard-free"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Michael Theobald, Steven M. Nowick	An Implicit Method for Hazard-Free Two-Level Logic Minimization.	ASYNC	1998	DBLP DOI BibTeX RDF	hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit
105	Steven M. Nowick, Charles W. O'Donnell	On the Existence of Hazard-Free Multi-Level Logic.	ASYNC	2003	DBLP DOI BibTeX RDF
88	Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Synthesis for testability techniques for asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
82	Bill Lin 0001, Srinivas Devadas	Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
77	Michael Theobald, Steven M. Nowick	Fast heuristic and exact algorithms for two-level hazard-free logic minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
68	Adit D. Singh, Gefu Xu	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.	VTS	2006	DBLP DOI BibTeX RDF	Hazard-Free, Test, Delay, Transition
68	J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren	An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization.	DATE	1998	DBLP DOI BibTeX RDF	exact minimization, two-level minimization, hazard free logic, divide and conquer, asynchronous logic
68	Ajay Khoche, Erik Brunvand	Critical hazard free test generation for asynchronous circuits.	VTS	1997	DBLP DOI BibTeX RDF	self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm
68	U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
65	Feng Shi	Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits.	ICCD	2008	DBLP DOI BibTeX RDF
65	Steven M. Nowick, David L. Dill	Exact two-level minimization of hazard-free logic with multiple-input changes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
63	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
58	Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick	Algorithms for the optimal state assignment of asynchronous state machines.	ARVLSI	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic
55	Chris J. Myers, Hans M. Jacobson	Efficient Exact Two-Level Hazard-Free Logic Minimization.	ASYNC	2001	DBLP DOI BibTeX RDF
55	Tam-Anh Chu	Synthesis of hazard-free control circuits from asynchronous finite state machines specifications.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
52	Hans M. Jacobson, Chris J. Myers	Efficient algorithms for exact two-level hazard-free logic minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
45	Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick	Symbolic hazard-free minimization and encoding of asynchronous finite state machines.	ICCAD	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, hazards, sequential synthesis, sequential optimization
45	Bill Lin 0001, Srinivas Devadas	Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.	ICCAD	1994	DBLP DOI BibTeX RDF
43	Tatsuo Higuchi 0001, Michitaka Kameyama	Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting
42	Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger	On Hazard-free Patterns for Fine-delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
42	Kenneth Y. Yun, David L. Dill	Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
42	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	Hazard-free implementation of speed-independent circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
42	Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli	Synthesis of hazard-free asynchronous circuits with bounded wire delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
42	Cho W. Moon, Paul R. Stephan, Robert K. Brayton	Specification, synthesis, and verification of hazard-free asynchronous circuits.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
40	Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin 0001	Externally hazard-free implementations of asynchronous control circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
38	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Design and Analysis of Dual-Rail Circuits for Security Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
38	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
38	Hon Fung Li, P. N. Lam	A protocol extraction strategy for control point insertion in design for test of transition signaling circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	protocol extraction strategy, control point insertion, transition signaling circuits, hazard-free test, safe behaviors, gap detection, gap matching, single input pad, protocols, logic testing, design for testability, asynchronous circuits, asynchronous circuits, design for test, test length, area overhead
38	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
38	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
38	Sunil D. Sherlekar, P. S. Subramanian	Conditionally robust two-pattern tests and CMOS design for testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
35	Sobeeh Almukhaizim, Yiorgos Makris	Concurrent Error Detection in Asynchronous Burst-Mode Controllers.	DATE	2005	DBLP DOI BibTeX RDF
30	Eric Senn, Bertrand Y. Zavidovique	Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
30	Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau	Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
28	Kenneth Y. Yun, David L. Dill	Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
26	Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton	Generalized Sensitization using Fault Tuples.	VTS	2004	DBLP DOI BibTeX RDF	multiple path sensitization, hazard-free test, fault model, Fault simulation, robust test
26	Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh	Estimation and bounding of energy consumption in burst-mode control circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	statistical energy estimation, hazard-free logic, N-valued simulation, low power design, asynchronous circuits
25	Kenneth Y. Yun, Bill Lin 0001, David L. Dill, Srinivas Devadas	BDD-based synthesis of extended burst-mode controllers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
25	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	On variable clock methods for path delay testing of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
25	Teresa H.-Y. Meng, Robert W. Brodersen, David G. Messerschmitt	Automatic synthesis of asynchronous circuits from high-level specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Sobeeh Almukhaizim, Yiorgos Makris	Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	asynchronous burst-mode machines, error-detecting codes, Concurrent error detection, Berger code
17	Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh	Karchmer-Wigderson Games for Hazard-Free Computation.	ITCS	2023	DBLP DOI BibTeX RDF
17	Johannes Bund, Christoph Lenzen 0001, Moti Medina	Small Hazard-Free Transducers.	ITCS	2022	DBLP DOI BibTeX RDF
17	Johannes Bund	Hazard-free clock synchronization.		2022	RDF
17	Stasys Jukna	Notes on Hazard-Free Circuits.	SIAM J. Discret. Math.	2021	DBLP DOI BibTeX RDF
17	Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh	Karchmer-Wigderson Games for Hazard-free Computation.	Electron. Colloquium Comput. Complex.	2021	DBLP BibTeX RDF
17	Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh	Karchmer-Wigderson Games for Hazard-free Computation.	CoRR	2021	DBLP BibTeX RDF
17	Alexander Kushnerov, Moti Medina, Alexandre Yakovlev	Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits.	ASYNC	2021	DBLP DOI BibTeX RDF
17	Stasys Jukna	Notes on Hazard-Free Circuits.	Electron. Colloquium Comput. Complex.	2020	DBLP BibTeX RDF
17	Stasys Jukna	Notes on Hazard-Free Circuits.	CoRR	2020	DBLP BibTeX RDF
17	Ankit Shah, Raman Nayyar, Arani Sinha	Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests.	IEEE Des. Test	2020	DBLP DOI BibTeX RDF
17	Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah	On the Complexity of Hazard-free Circuits.	J. ACM	2019	DBLP DOI BibTeX RDF
17	Ankit Shah, Raman Nayyar, Arani Sinha	Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests.	VTS	2019	DBLP DOI BibTeX RDF
17	Johannes Bund, Christoph Lenzen 0001, Moti Medina	Small Hazard-free Transducers.	CoRR	2018	DBLP BibTeX RDF
17	Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah	On the complexity of hazard-free circuits.	STOC	2018	DBLP DOI BibTeX RDF
17	Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah	On the complexity of hazard-free circuits.	CoRR	2017	DBLP BibTeX RDF
17	Sobeeh Almukhaizim, Ozgur Sinanoglu	Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
17	Cuong Pham-Quoc, Anh-Vu Dinh-Duc	Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA.	DELTA	2010	DBLP DOI BibTeX RDF
17	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes.	EURASIP J. Embed. Syst.	2009	DBLP DOI BibTeX RDF
17	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	Reply to "Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".	EURASIP J. Embed. Syst.	2009	DBLP DOI BibTeX RDF
17	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary	Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".	EURASIP J. Embed. Syst.	2009	DBLP DOI BibTeX RDF
17	Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi	A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling.	DSD	2009	DBLP DOI BibTeX RDF
17	Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal	Output Hazard-Free Transition Delay Fault Test Generation.	VTS	2009	DBLP DOI BibTeX RDF
17	Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
17	Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz	The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
17	Wayne D. Grover	Globally optimal distributed synchronous batch reconfiguration for efficient hazard-free dynamic provisioning: How an entire network can "think globally and act locally".	DRCN	2007	DBLP DOI BibTeX RDF
17	Lei Zhang 0033, Zhiping Yu, Xiangqing He	Hazard Free Sawtooth Oscillator and Its Application in Ultra Low Current Monitoring.	ICECS	2006	DBLP DOI BibTeX RDF
17	Eric Senn, Pietro Perona	Hazard-free self-timed design: methodology and application.	Integr. Comput. Aided Eng.	2000	DBLP DOI BibTeX RDF
17	Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan	Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines.	ICCAD	2000	DBLP DOI BibTeX RDF
17	J. W. J. M. Rutten, Michel R. C. M. Berkelaar	Efficient exact and heuristic minimization of hazard-free logic.	ICCD	1998	DBLP DOI BibTeX RDF
17	Martijn De Boer, A. Gröpl, Jürgen Hesser, Reinhard Männer	Latency- and hazard-free volume memory architecture for direct volume rendering.	Comput. Graph.	1997	DBLP DOI BibTeX RDF
17	Kuan-Jen Lin, Chi-Wen Kuo, Chen-Shang Lin	Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	hazard-freeness, characteristic graph, exact optimization, Asynchronous circuit, signal transition graph
17	Jennifer E. Walter, Jennifer L. Welch	Hazard-Free Connection Release.	PDPTA	1997	DBLP BibTeX RDF
17	Martijn De Boer, A. Gröpl, Jürgen Hesser, Reinhard Männer	Latency- and Hazard-Free Volume Memory Ar chitecture for Direct Volume Rendering.	Workshop on Graphics Hardware	1996	DBLP DOI BibTeX RDF
17	Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick	Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.	DAC	1996	DBLP DOI BibTeX RDF
17	Michael Theobald, Steven M. Nowick, Tao Wu	Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic.	DAC	1996	DBLP DOI BibTeX RDF
17	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	On hazard-free implementation of speed-independent circuits.	ASP-DAC	1995	DBLP DOI BibTeX RDF
17	Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin 0001	Externally Hazard-Free Implementations of Asynchronous Circuits.	DAC	1995	DBLP DOI BibTeX RDF
17	Md. Mozammel Huq Azad Khan	An Algorithm for Hazard-Free Minimization of Incompletely Specified Switching Function.	Inf. Process. Lett.	1994	DBLP DOI BibTeX RDF
17	Radhakrishna Nagalla, Graham R. Hellestrand	Signal Transition Graph Constraints for Synthesis of Hazard-Free Asynchronous Circuits with Unbounded-Gate Delays.	Formal Methods Syst. Des.	1994	DBLP DOI BibTeX RDF
17	Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin	Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
17	Enric Pastor, Jordi Cortadella	Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs.	ICCAD	1993	DBLP DOI BibTeX RDF
17	Tam Anh Chu	On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits.	ISCAS	1993	DBLP BibTeX RDF
17	Alexandre Yakovlev	Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs.	VLSI Design	1993	DBLP DOI BibTeX RDF
17	Meng-Lin Yu, P. A. Subrahmanyam	Hazard-Free Asynchronous Circuit Synthesis.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
17	Michael J. Bryan, Srinivas Devadas, Kurt Keutzer	Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
17	Steven M. Nowick, David L. Dill	Exact two-level minimization of hazard-free logic with multiple-input changes.	ICCAD	1992	DBLP DOI BibTeX RDF
17	Tam-Anh Chu	Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications.	ICCD	1992	DBLP DOI BibTeX RDF
17	Cho W. Moon, Paul R. Stephan, Robert K. Brayton	Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.	ICCAD	1991	DBLP DOI BibTeX RDF
17	Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli	Algorithms for Synthesis of Hazard-Free Asynchronous Circuits.	DAC	1991	DBLP DOI BibTeX RDF
17	Eskil Kjelkerud, Owe Thessén	Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulation.	DAC	1979	DBLP BibTeX RDF
17	Jon G. Bredeson	On Multiple Input Change Hazard-Free Combinatorial Switching Circuits without Feedback	SWAT	1973	DBLP DOI BibTeX RDF
17	David A. Huffman	The Design and Use of Hazard-Free Switching Networks.	J. ACM	1957	DBLP DOI BibTeX RDF
15	A. P. Shanthi, L. Karthik Singaram, Ranjani Parthasarathi	Evolution of Asynchronous Sequential Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
13	Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown	Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin	High-Level Synthesis for Self-Timed Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
13	Nikolai Starodoubtsev, Sergei Bystrov	Behavior and Synthesis of Two-Input Gate Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
13	Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.	SBCCI	2005	DBLP DOI BibTeX RDF	burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent
13	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
13	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Improving the Security of Dual-Rail Circuits.	CHES	2004	DBLP DOI BibTeX RDF