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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 54 occurrences of 41 keywords
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Results
Found 191 publication records. Showing 191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Aamer Jaleel, Matthew Mattina, Bruce L. Jacob |
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 88-98, 2006, IEEE Computer Society, 0-7803-9368-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
82 | Mainak Chaudhuri |
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 401-412, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
chip-multiprocessor, replacement policy, last-level cache |
79 | Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki |
Reactive NUCA: near-optimal block placement and replication in distributed caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 184-195, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache |
75 | Livio Soares, David K. Tam, Michael Stumm |
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 258-269, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 72-82, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
55 | Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez |
Scavenger: A New Last Level Cache Architecture with Global Block Priority. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 421-432, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Javier Lira, Carlos Molina, Antonio González 0001 |
The auction: optimizing banks usage in Non-Uniform Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 37-47, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP) |
44 | Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen |
L1 Collective Cache: Managing Shared Data for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 123-133, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMP, cache design, L1 cache |
43 | Tao Wang 0004, Qigang Wang, Dong Liu, Michael Liao, Kevin Wang, Lu Cao, Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, John Du, Liang Wang |
Hardware/Software Co-Simulation for Last Level Cache Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: International Conference on Networking, Architecture, and Storage, NAS 2009, 9-11 July 2009, Zhang Jia Jie, Hunan, China, pp. 371-378, 2009, IEEE Computer Society, 978-0-7695-3741-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Haakon Dybdahl, Per Stenström |
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 2-12, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Han Jun Bae, Lynn Choi |
Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 76(10), pp. 7521-7544, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
39 | Cesar Gomes, Mark Hempstead |
Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015, pp. 423-426, 2015, IEEE Computer Society, 978-1-4673-7166-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
38 | Jugash Chandarlapati, Mainak Chaudhuri |
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 423-430, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang |
SHARP control: controlled shared cache management in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 517-528, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Bijay Paikaray |
Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1307.6406, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
35 | Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer |
High performance cache replacement using re-reference interval prediction (RRIP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 60-71, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
scan resistance, thrashing, shared cache, replacement |
35 | Moinuddin K. Qureshi |
Adaptive Spill-Receive for robust high-performance caching in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 45-54, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Jaspinder Kaur, Shirshendu Das |
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-3475-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
31 | Anurag Agarwal, Jaspinder Kaur, Shirshendu Das |
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1691-1696, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
31 | Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das |
A Fairness Conscious Cache Replacement Policy for Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 695-700, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
31 | Ashutosh Dhar, Xiaohao Wang, Hubertus Franke, Jinjun Xiong, Jian Huang 0006, Wen-Mei W. Hwu, Nam Sung Kim, Deming Chen |
FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 102-117, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
31 | Fanfan Shen, Yanxiang He, Jun Zhang 0058, Qingan Li, Jianhua Li 0003, Chao Xu |
Reuse locality aware cache partitioning for last-level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 74, pp. 319-330, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong |
MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 16(3), pp. 26:1-26:26, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Gangyong Jia, Guangjie Han, Hao Wang 0047, Feng Wang |
Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Enterp. Inf. Syst. ![In: Enterp. Inf. Syst. 12(4), pp. 435-451, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Martin Rapp, Anuj Pathania, Jörg Henkel |
Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2018, Seattle, WA, USA, July 23-25, 2018, pp. 16:1-16:6, 2018, ACM, 978-1-4503-5704-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Fazal Hameed, Christian Menard, Jerónimo Castrillón |
Efficient STT-RAM last-level-cache architecture to replace DRAM cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017, pp. 141-151, 2017, ACM, 978-1-4503-5335-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Aswinkumar Sridharan, André Seznec |
Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, May 23-27, 2016, pp. 822-831, 2016, IEEE Computer Society, 978-1-5090-2140-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Seunghee Shin, Sihong Kim, Yan Solihin |
Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016, pp. 191-203, 2016, ACM, 978-1-4503-4305-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Ju Hee Choi, Jong Wook Kwak, Chu Shik Jhon |
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(8), pp. 2166-2169, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
31 | |
A Cache Energy Optimization Technique for STT-RAM Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1312.2207, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
31 | Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería |
The reuse cache: downsizing the shared last-level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 310-321, 2013, ACM, 978-1-4503-2638-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Tao Huang, Jing Wang 0055, Xuetao Guan, Qi Zhong, Keyi Wang |
Combining Process-Based Cache Partitioning and Pollute Region Isolation to Improve Shared Last Level Cache Utilization on Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom/ISPA/IUCC ![In: 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2013 / 11th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA-13 / 12th IEEE International Conference on Ubiquitous Computing and Communications, IUCC-2013, Melbourne, Australia, July 16-18, 2013, pp. 1153-1160, 2013, IEEE Computer Society, 978-0-7695-5022-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Yu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman |
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 45-50, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
31 | Deukhyeon Ahn, Jee-hong Kim, JungHyun Han, Young Ik Eom |
Reducing Last Level Cache Pollution in NUMA Multicore Systems for Improving Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2012 - 12th International Conference, Salvador de Bahia, Brazil, June 18-21, 2012, Proceedings, Part III, pp. 272-282, 2012, Springer, 978-3-642-31136-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
31 | Jiayuan Meng, Kevin Skadron |
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 27th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009, pp. 282-288, 2009, IEEE Computer Society, 978-1-4244-5029-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Jason Loew, Dmitry Ponomarev 0001 |
Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2008 International Conference on Parallel Processing, ICPP 2008, September 8-12, 2008, Portland, Oregon, USA, pp. 182-189, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tao Huang, Qi Zhong, Xuetao Guan, Xiaoyin Wang, Xu Cheng 0001, Keyi Wang |
Reducing last level cache pollution through OS-level software-controlled region-based partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the ACM Symposium on Applied Computing, SAC 2012, Riva, Trento, Italy, March 26-30, 2012, pp. 1779-1784, 2012, ACM, 978-1-4503-0857-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Yu Chen, Wenlong Li, Junmin Lin, Aamer Jaleel, Zhizhong Tang |
Data Sharing Analysis of Emerging Parallel Media Mining Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2008, 15th International Conference, Bangalore, India, December 17-20, 2008. Proceedings, pp. 87-96, 2008, Springer, 978-3-540-89893-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | William B. Langdon, David Clark 0001 |
Genetic Improvement of Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroGP ![In: Genetic Programming - 27th European Conference, EuroGP 2024, Held as Part of EvoStar 2024, Aberystwyth, UK, April 3-5, 2024, Proceedings, pp. 209-226, 2024, Springer, 978-3-031-56956-2. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Zirui Neil Zhao, Adam Morrison 0001, Christopher W. Fletcher, Josep Torrellas |
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS (2) ![In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024, pp. 582-600, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy |
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(4), pp. 1117-1128, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Daniel A. Jiménez, Elvira Teran, Paul V. Gratz |
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 22(1), pp. 17-20, January - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Alexandre Valentin Jamet, Lluc Alvarez, Marc Casas |
Characterizing the impact of last-level cache replacement policies on big-data workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.06696, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Gianluca Brilli, Paolo Burgio |
Interference analysis of shared last-level cache on embedded GP-GPUs with multiple CUDA streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.04848, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Fernando García-Redondo, S. Rao, M. Gupta, Manu Perumkunnil, Y. Xiang, D. Abdi, Simon Van Beek, S. Couet, Marie Garcia Bardon |
STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 97-100, 2023, IEEE, 979-8-3503-0423-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Marcelo Ruaro, Hadrien Barral, Matteo Bertolino, Rodrigo Cataldo, Roberto Medina 0001, Mohamed Karaoui, Etienne Borde |
The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 26th Euromicro Conference on Digital System Design, DSD 2023, Golem, Albania, September 6-8, 2023, pp. 351-358, 2023, IEEE, 979-8-3503-4419-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Probir Roy, Birhanu Eshete, Pengfei Su 0001 |
Designing Secure Performance Metrics for Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023, pp. 383-392, 2023, IEEE, 979-8-3503-1199-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Osang Kwon, Yongho Lee, Seokin Hong |
Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 114552-114565, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(4), pp. 418-431, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Fazal Hameed, Jerónimo Castrillón |
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12), pp. 5288-5298, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Tommaso Marinelli, José Ignacio Gómez Pérez, Christian Tenllado, Manu Komalan, Mohit Gupta 0004, Francky Catthoor |
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 21(1), pp. 3:1-3:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Zhuanhao Wu, Hiren D. Patel |
Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.01679, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Sina Darabi, Mohammad Sadrosadati, Joël Lindegger, Negar Akbarzadeh, Mohammad Hosseini, Jisung Park 0001, Juan Gómez-Luna, Hamid Sarbazi-Azad, Onur Mutlu |
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2209.10914, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals |
Forecasting lifetime and performance of a novel NVM last-level cache with compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.03512, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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24 | Sina Darabi, Mohammad Sadrosadati, Negar Akbarzadeh, Joël Lindegger, Mohammad Hosseini, Jisung Park 0001, Juan Gómez-Luna, Onur Mutlu, Hamid Sarbazi-Azad |
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 228-244, 2022, IEEE, 978-1-6654-6272-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy |
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 68-69, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Ya-Hui Yang, Shuo-Han Chen, Yuan-Hao Chang 0001 |
Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022, pp. 8:1-8:6, 2022, ACM, 978-1-4503-9354-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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24 | Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Jaume Abella 0001, Francisco J. Cazorla |
Contention Tracking in GPU Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022, pp. 76-79, 2022, IEEE, 978-1-6654-6186-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Yashika Verma, Biswabandan Panda |
Avenger: Punishing the Cross-Core Last-Level Cache Attacker and Not the Victim by Isolating the Attacker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEED ![In: 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), Storrs, CT, USA, September 26-27, 2022, pp. 1-12, 2022, IEEE, 978-1-6654-8526-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Zhuanhao Wu, Hiren D. Patel |
Predictable sharing of last-level cache partitions for multi-core safety-critical systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1273-1278, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki |
Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Commun. ![In: IEICE Trans. Commun. 104-B(2), pp. 149-157, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
24 | Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang |
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 70(9), pp. 1498-1510, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Qianqian Wu, Zhenzhou Ji |
A perceptron-based replication scheme for managing the shared last level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 85, pp. 104310, September 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Candace Walden, Devesh Singh, Meenatchi Jagasivamani, Shang Li 0001, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung |
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 18(4), pp. 48:1-48:26, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Yuanqing Cheng, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last Level Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.05023, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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24 | Sidharth Rao, Woojin Kim, Simon Van Beek, Shreya Kundu, Manu Perumkunnil, Stefan Cosemans, Farrukh Yasin, Sebastien Couet, Robert Carpenter, Barry J. O'Sullivan, Shamin H. Sharifi, N. Jossart, Laurent Souriau, Ludovic Goux, Dimitri Crotti, Gouri Sankar Kar |
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMW ![In: IEEE International Memory Workshop, IMW 2021, Dresden, Germany, May 16-19, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-8517-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Xiaoyang Lu, Rujia Wang, Xian-He Sun |
Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021, pp. 391-394, 2021, IEEE, 978-1-6654-3219-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Sukarn Agarwal, Shounak Chakraborty 0001 |
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 171-174, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Shahrad, Sameh Elnikety, Ricardo Bianchini |
Provisioning Differentiated Last-Level Cache Allocations to VMs in Public Clouds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: SoCC '21: ACM Symposium on Cloud Computing, Seattle, WA, USA, November 1 - 4, 2021, pp. 319-334, 2021, ACM, 978-1-4503-8638-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Mainak Chaudhuri |
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Virtual Event / Valencia, Spain, June 14-18, 2021, pp. 71-84, 2021, IEEE, 978-1-6654-3333-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki |
Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 59290-59304, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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24 | Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang 0001 |
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 16(3), pp. 29:1-29:18, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang 0094, Ying Wang 0001, Jianlei Yang 0001, Yuanqing Cheng, Dijun Liu, Youguang Zhang |
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1), pp. 108-120, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Xian-Shu Li, Su-Kyung Yoon, Jeong-Geun Kim, Bernd Burgstaller, Shin-Dug Kim |
Algorithm-Switching-Based Last-Level Cache Structure with Hybrid Main Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 63(1), pp. 123-136, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas |
Characterizing the impact of last-level cache replacement policies on big-data workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: IEEE International Symposium on Workload Characterization, IISWC 2020, Beijing, China, October 27-30, 2020, pp. 134-144, 2020, IEEE, 978-1-7281-7645-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Jiaheng Liu, Ryusuke Egawa, Mulya Agung, Hiroyuki Takizawa |
A Conflict-Aware Capacity Control Mechanism for Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR (Workshops) ![In: Eighth International Symposium on Computing and Networking Workshops, CANDAR 2020 Workshops, Naha, Japan, November 24-27, 2020, pp. 416-420, 2020, IEEE, 978-1-7281-9919-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Fazal Hameed, Jerónimo Castrillón |
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(10), pp. 2375-2386, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang |
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(12), pp. 1704-1719, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera |
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 125, pp. 31-44, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Yang Song 0006, Olivier Alavoine, Bill Lin 0001 |
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(1), pp. 5:1-5:27, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Biswabandan Panda |
Fooling the Sense of Cross-core Last-level Cache Eviction based Attacker by Prefetching Common Sense. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2019, pp. 391, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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24 | Sheela Kathavate, Lakshmi Rajesh, N. K. Srinath |
PR-LRU: partial random LRU technique for performance improvement of last level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Aided Eng. Technol. ![In: Int. J. Comput. Aided Eng. Technol. 11(1), pp. 111-121, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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24 | Anatoly Shusterman, Lachlan Kang, Yarden Haskal, Yosef Meltzer, Prateek Mittal, Yossi Oren, Yuval Yarom |
Website Fingerprinting - Last Level Cache Contention Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
DOI RDF |
|
24 | Biswabandan Panda |
Fooling the Sense of Cross-Core Last-Level Cache Eviction Based Attacker by Prefetching Common Sense. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019, pp. 138-150, 2019, IEEE, 978-1-7281-3613-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Jongwook Chung, Yuhwan Ro, Joonsung Kim, Jaehyung Ahn, Jangwoo Kim, John Kim, Jae W. Lee, Jung Ho Ahn |
Enforcing Last-Level Cache Partitioning through Memory Virtual Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019, pp. 97-109, 2019, IEEE, 978-1-7281-3613-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001 |
Exploring emerging CNFET for efficient last level cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, pp. 426-431, 2019, ACM, 978-1-4503-6007-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Ganghee Jang, Jean-Luc Gaudiot |
Data Shepherding: A Last Level Cache Design for Large Scale Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/SmartCity/DSS ![In: 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019, Zhangjiajie, China, August 10-12, 2019, pp. 1920-1927, 2019, IEEE, 978-1-7281-2058-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Swapnil Bhosale, Sudeep Pasricha |
SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: 15th IEEE International Conference on Embedded Software and Systems, ICESS 2019, Las Vegas, NV, USA, June 2-3, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-2437-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Pei-Yu Chen, Wei-Kuan Shih |
Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2954-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Raphael Durner, Christian Sieber, Wolfgang Kellerer |
Towards Reducing Last-Level-Cache Interference of Co-Located Virtual Network Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: 28th International Conference on Computer Communication and Networks, ICCCN 2019, Valencia, Spain, July 29 - August 1, 2019, pp. 1-9, 2019, IEEE, 978-1-7281-1856-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Alexander Hankin, Tomer Shapira, Karthik Sangaiah, Michael Lui, Mark Hempstead |
Evaluation of Non-Volatile Memory Based Last Level Cache Given Modern Use Case Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: IEEE International Symposium on Workload Characterization, IISWC 2019, Orlando, FL, USA, November 3-5, 2019, pp. 143-154, 2019, IEEE, 978-1-7281-4045-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Huanxing Shen, Cong Li |
Detecting Last-Level Cache Contention in Workload Colocation with Meta Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: IEEE International Symposium on Workload Characterization, IISWC 2019, Orlando, FL, USA, November 3-5, 2019, pp. 14-23, 2019, IEEE, 978-1-7281-4045-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Alireza Farshin, Amir Roozbeh, Gerald Q. Maguire Jr., Dejan Kostic |
Make the Most out of Last Level Cache in Intel Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, pp. 8:1-8:17, 2019, ACM, 978-1-4503-6281-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Jinsu Park, Seongbeom Park, Woongki Baek |
CoPart: Coordinated Partitioning of Last-Level Cache and Memory Bandwidth for Fairness-Aware Workload Consolidation on Commodity Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, pp. 10:1-10:16, 2019, ACM, 978-1-4503-6281-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Burak Sezin Ovant, Isa Ahmet Güney, Muhammed Emin Savas, Gürhan Küçük |
Last level cache partitioning via multiverse thread classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 26(1), pp. 220-233, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón |
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(6), pp. 1059-1072, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Lan Gao, Rui Wang 0014, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai |
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(7), pp. 3388-3414, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Jingyu Zhang, Minyi Guo, Chentao Wu, Yuanyi Chen |
Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 61(1), pp. 012105:1-012105:14, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Guan Wang, Chuanqi Zang, Lei Ju 0001, Mengying Zhao, Xiaojun Cai, Zhiping Jia |
Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 17(4), pp. 77:1-77:25, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Yumna Zahid, Hina Khurshid, Zulfiqar Ali Memon |
On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Technol. Control. ![In: Inf. Technol. Control. 47(3), pp. 588-607, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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