Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
118 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated energy/performance macromodeling of embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 99-102, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
data serialization, genetic programming, regression, embedded software, symbolic, macromodeling |
110 | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
High-level energy macromodeling of embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9), pp. 1037-1050, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
96 | Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos |
A multi-model power estimation engine for accuracy optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 280-285, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power macromodeling, powerSC, low power design, systemC, power estimation |
81 | Giuseppe Bernacchia, Marios C. Papaefthymiou |
Analytical macromodeling for high-level power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 280-283, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
66 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Automated Energy/Performance Macromodeling of Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 542-552, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos |
On the Limitations of Power Macromodeling Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 395-400, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Mengmeng Ding, Ranga Vemuri |
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1088-1089, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Min Zhao 0001, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu |
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 217-222, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sequence of linear programming, macromodeling, budgeting, decoupling capacitance |
59 | Yuantao Peng, Xun Liu |
Power macromodeling of global interconnects considering practical repeater insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 244-247, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, interconnect, macromodeling, repeater insertion |
59 | Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li 0001 |
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 196-201, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
stack effect, leakage current simulation, propagation of signal probability, macromodeling |
52 | Xiaolue Lai, Jaijeet S. Roychowdhury |
Advanced tools for simulation and design of oscillators/PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 442-449, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
jitter analysis, automated oscillator, macromodeling technique, amplitude macromodels, injection locking prediction, coupled oscillating systems, SPICE, PLL |
52 | Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, Madhavan Swaminathan, Wendemagegnehu T. Beyene, Chuck Yuan |
Modeling and Analysis of Power Distribution Networks for Gigabit Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 2(4), pp. 299-313, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
transmission matrix method, power bus, decoupling, macromodeling, Power distribution network |
51 | Hai Wang 0002, Hao Yu 0001, Sheldon X.-D. Tan |
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 379-384, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury |
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), pp. 56-64, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
Energy macromodeling of embedded operating systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(1), pp. 231-254, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Linux, energy consumption, characterization |
51 | Xun Liu, Marios C. Papaefthymiou |
Incorporation of input glitches into power macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 846-849, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Qinwei Xu, Pinaki Mazumder, Li Ding 0002 |
Novel macromodeling for on-chip RC/RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 189-192, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 375-383, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Qinwei Xu, Pinaki Mazumder |
Efficient Macromodeling for On-Chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 561-566, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated nonlinear Macromodelling of output buffers for high-speed digital applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 51-56, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
I/O buffer macromodeling, nonlinear macromodeling |
45 | Mirko Loghi, Luca Benini, Massimo Poncino |
Power macromodeling of MPSoC message passing primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(4), pp. 31, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiprocessor, system-on-chip, macromodeling, Communication primitives |
45 | Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy |
Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 355-360, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation |
45 | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
PRIMA: passive reduced-order interconnect macromodeling algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 58-65, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability |
45 | Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001 |
Fault macromodeling and a testing strategy for opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 225-235, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults |
44 | Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince |
A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8), pp. 1250-1261, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Mengmeng Ding, Ranga Vemuri |
A combined feasibility and performance macromodel for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 63-68, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
feasibility models, performance macromodeling, active learning |
37 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 433-438, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub |
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 574-578, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Chi-Un Lei, Hing-Kit Kwan, Yansong Liu, Ngai Wong |
Efficient linear macromodeling via least-squares response approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2993-2996, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Chi-Un Lei, Ngai Wong |
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 469-474, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo |
Efficient Power Macromodeling Technique for IP-Based Digital System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1145-1148, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Jian Wang, Xin Li 0001, Lawrence T. Pileggi |
Parameterized Macromodeling for Analog System-Level Design Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 940-943, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 667-671, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Mengmeng Ding, Ranga Vemuri |
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 553-556, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7), pp. 1048-1062, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Alper Demir 0001, Jaijeet S. Roychowdhury |
A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2), pp. 188-197, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Passive macromodeling of subnetworks characterized by measured data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 502-505, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 404-411, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino |
Power Macromodeling for a High Quality RT-Level Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 59-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Zhanping Chen, Kaushik Roy 0001 |
A Power Macromodeling Technique Based on Power Sensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 678-683, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconfigurable computing, event-driven simulation |
37 | Jianfeng Shao, Ramesh Harjani |
Macromodeling of analog circuits for hierarchical circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 656-663, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
37 | Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen |
Macromodeling CMOS circuits for timing simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12), pp. 1237-1249, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
37 | Mark D. Matson |
Macromodeling of digital MOS VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 141-151, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
29 | Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng 0001 |
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1571-1582, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 162-167, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
29 | Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha |
Hybrid Simulation for Energy Estimation of Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1843-1854, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Hao Yu 0001, Chunta Chu, Lei He 0001 |
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 618-621, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Hao Yu 0001, Joanna Ho, Lei He 0001 |
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 41:1-41:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Thermal and power integrity, parametric 3D-IC design, macromodeling |
23 | Rick Salay, John Mylopoulos, Steve M. Easterbrook |
Using Macromodels to Manage Collections of Related Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAiSE ![In: Advanced Information Systems Engineering, 21st International Conference, CAiSE 2009, Amsterdam, The Netherlands, June 8-12, 2009. Proceedings, pp. 141-155, 2009, Springer, 978-3-642-02143-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Modeling, Mappings, Metamodeling, Relationships, Macromodeling |
23 | Jorgen Peddersen, Sri Parameswaran |
Low-Impact Processor for Dynamic Runtime Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 52-62, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-impact processor, runtime power management, power estimation, energy aware, macromodeling, counters |
23 | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino |
Power Estimation of Behavioral Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 762-766, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Behavioral power estimation, macromodeling, design exploration |
22 | Fatemeh Charoosaei, Amin Faraji, Sayed Alireza Sadrossadat, Ali Mirvakili, Weicong Na, Feng Feng, Qi-Jun Zhang |
High-Speed Nonlinear Circuit Macromodeling Using Hybrid-Module Clockwork Recurrent Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(2), pp. 767-780, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Amin Faraji, Sayed Alireza Sadrossadat, Weicong Na, Feng Feng, Qi-Jun Zhang |
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(7), pp. 2904-2915, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Amin Faraji, Sayed Alireza Sadrossadat, Mahdi Yazdian Dehkordi, Morteza Nabavi, Yvon Savaria |
A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 127996-128006, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Faisal Siddiq, Yaseer Arafat Durrani |
Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 29(3), pp. 1368-1382, May 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Ning Wang, Shiyou Yang, Zhuoxiang Ren, Huifang Wang |
An Improved Structure-Preserving Reduced-Order Interconnect Macromodeling for Large-Scale Equation Sets of Transient Interconnect Circuit Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 132150-132157, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Harry Weber, Harun Baran, Fabian Utermöhlen, Christian Schuster |
Macromodeling of Mutual Inductance for Displaced Coils Based on Laplace's Equation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 70, pp. 1-11, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Nahid Mirzaie, Ron Rohrer |
A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12), pp. 5025-5031, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Manfredi, Stefano Grivet-Talocia |
Rational Polynomial Chaos Expansions for the Stochastic Macromodeling of Network Responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1), pp. 225-234, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Utkarsh R. Patel, Piero Triverio, Sean V. Hum |
A Fast Macromodeling Approach to Efficiently Simulate Inhomogeneous Electromagnetic Surfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1911.04576, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
22 | Aswini P. Reghu, R. V. Sanjika Devi, K. Vrinda, Dhanesh G. Kurup |
Macromodeling of High Frequency Interconnects Based on Accurate Delay Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2018 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2018, Bangalore, India, September 19-22, 2018, pp. 1636-1640, 2018, IEEE, 978-1-5386-5314-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Hao Yu 0001, Guoyong Shi |
Symbolic Circuit Reduction for Multistage Amplifier Macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 247-250, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Utkarsh R. Patel, Piero Triverio, Sean V. Hum |
A Macromodeling Approach to Efficiently Compute Scattering from Large Arrays of Complex Scatterers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1712.02443, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
22 | Marwan Kanaan, Roni Khazaka |
Nonlinear time-domain macromodeling using proper orthogonal decomposition and feedforward neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 30th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2017, Windsor, ON, Canada, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5538-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Leibin Ni, Sai Manoj P. D., Yang Song, Chenjie Gu, Hao Yu 0001 |
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6), pp. 1040-1051, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001, Y. Ye, Domenico Spina, Tom Dhaene |
Frequency-dependent parameterized macromodeling of integrated inductors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016, Lisbon, Portugal, June 27-30, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0490-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye, Tianshi Wang, Yang Li 0183 |
Domain-Alternated Optimization for Passive Macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(10), pp. 2244-2255, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | H. Herrmann, W. Horchler, S. Schwarz, Philipp Schröter, Frank Klotz, Marco Brignone, Franco Fiori |
Smart power IC macromodeling for DPI analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMC Compo ![In: 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2015, Edinburgh, UK, November 10-13, 2015, pp. 244-247, 2015, IEEE, 978-1-4673-7897-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li 0001, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi |
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, pp. 441-446, 2015, IEEE, 978-1-4799-7792-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ehsan Ali, Wenceslas Rahajandraibe, Fayrouz Haddad, Ndiogou Tall, Christian Hangmann, Christian Hedayat |
Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 878-881, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Yi Qing Xiao, Muhammad Kabir, Marco T. Kassis, Roni Khazaka |
Passive Reduced Order Macromodeling Based on Admittance Parameter Using Hamiltonian-Symplectic Matrix Pencil Perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUWB ![In: IEEE International Conference on Ubiquitous Wireless Broadband, ICUWB 2015, Montreal, QC, Canada, October 4-7, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-6555-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Chao Ma, Shuguo Xie, Yunfeng Jia, Guanyu Lin |
Macromodeling of the memristor using piecewise volterra series. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(3), pp. 325-329, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Ehsan Ali, Wenceslas Rahajandraibe, Fayrouz Haddad, Christian Hangmann, Christian Hedayat |
Simulations of 3rd order voltage switched CP-PLL using a fast event switching macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014, pp. 491-494, 2014, IEEE, 978-1-4799-4134-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Sai Manoj Pudukotai Dinakarrao, Hao Yu 0001, Chenjie Gu, Cheng Zhuo |
A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014, pp. 696-701, 2014, IEEE, 978-1-4799-6277-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye |
Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9), pp. 1435-1439, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Maffezzoni |
Nonlinear Phase-Domain Macromodeling of Injection-Locked Frequency Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11), pp. 2878-2887, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Alessandro Magnani, Vincenzo d'Alessandro, Niccolò Rinaldi, Massimiliano de Magistris, Klaus Aufinger |
Dynamic electrothermal macromodeling techniques for thermal-aware design of circuits and systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013, pp. 227-230, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Yang Zhang, Neric Fong, Ngai Wong |
Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, pp. 515-520, 2013, IEEE, 978-1-4673-3029-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Chenjie Gu |
Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013, pp. 1-8, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Elizabeth Rita Samuel, Luc Knockaert, Tom Dhaene |
Parametric Macromodeling using Interpolation of Sylvester based State-space Realizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICINCO (1) ![In: ICINCO 2013 - Proceedings of the 10th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Reykjavík, Iceland, 29 - 31 July, 2013, pp. 319-325, 2013, SciTePress, 978-989-8565-70-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Zuochang Ye |
Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-6415-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Bin Wu |
A statistically optimal macromodeling framework with application in process variation analysis of MEMS devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 10th IEEE International NEWCAS Conference, Montreal, QC, Canada, June 17-20, 2012, pp. 221-224, 2012, IEEE, 978-1-4673-0857-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001 |
Macromodeling a phase change memory (PCM) cell by HSPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, pp. 77-84, 2012, ACM, 978-1-4503-1671-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Joon Hyung Chung |
Efficient and physically consistent electromagnetic macromodeling of high-speed interconnects exhibiting geometric uncertainties ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
22 | Ting Zhu 0002, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon |
Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIMULTECH (Selected Papers) ![In: Simulation and Modeling Methodologies, Technologies and Applications - International Conference, SIMULTECH 2011 Noordwijkerhout, The Netherlands, July 29-31, 2011 Revised Selected Papers, pp. 255-269, 2011, Springer, 978-3-642-34335-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Yaseer Arafat Durrani |
Efficient power macromodeling technique for conventional MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEEI ![In: International Conference on Electrical Engineering and Informatics, ICEEI 2011, Bandung, Indonesia, 17-19 July, 2011, pp. 1-7, 2011, IEEE, 978-1-4577-0753-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Dimitri de Jonghe, Georges G. E. Gielen |
Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011, pp. 91-94, 2011, IEEE Computer Society, 978-1-4577-1399-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Hao Yu 0001, Chunta Chu, Yiyu Shi 0001, David Smart, Lei He 0001, Sheldon X.-D. Tan |
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(10), pp. 1399-1411, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Ádám Rák, György Cserey |
Macromodeling of the Memristor in SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4), pp. 632-636, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoda Pan, Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su |
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 1673-1676, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Chi-Un Lei, Ngai Wong |
VISA: versatile impulse structure approximation for time-domain linear macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 37-42, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Chenjie Gu, Jaijeet S. Roychowdhury |
Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010, pp. 284-291, 2010, IEEE, 978-1-4244-8192-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Paolo Maffezzoni, Dario D'Amore |
Compact Electrothermal Macromodeling of Photovoltaic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 56-II(2), pp. 162-166, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Ting Zhu 0002, Paul D. Franzon |
An enhanced macromodeling approach for differential output drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2009 IEEE International Behavioral Modeling and Simulation Workshop, BMAS 2009, San Jose, CA, USA, September 17-18, 2009, pp. 54-59, 2009, IEEE, 978-1-4244-5358-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Ying Wei 0002, Alex Doboli |
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4), pp. 712-725, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh |
Delay macromodeling and estimation for RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2430-2433, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid |
Accurate and reusable macromodeling technique using a fuzzy-logic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 508-511, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rick Salay, John Mylopoulos, Steve M. Easterbrook |
Managing Models through Macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 23rd IEEE/ACM International Conference on Automated Software Engineering (ASE 2008), 15-19 September 2008, L'Aquila, Italy, pp. 447-450, 2008, IEEE Computer Society, 978-1-4244-2187-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 287-293, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Zhigang Hao, Guoyong Shi |
New approaches to interconnect macromodeling with explicit delay extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1546-1549, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|