Search results for "modulo-scheduling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
119	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
116	Yosi Ben-Asher, Danny Meisler	Towards a Source Level Compiler: Source Level Modulo Scheduling.	Program Analysis and Compilation	2006	DBLP DOI BibTeX RDF
113	Daniel M. Lavery, Wen-mei W. Hwu	Modulo Scheduling of Loops in Control-intensive Non-numeric Programs.	MICRO	1996	DBLP DOI BibTeX RDF	control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling
91	Eric Stotzer, Ernst L. Leiss	Modulo scheduling without overlapped lifetimes.	LCTES	2009	DBLP DOI BibTeX RDF	instruction level parallelism, register allocation, software pipelining, modulo scheduling
72	Josep Llosa, Stefan M. Freudenberger	Reduced code size modulo scheduling in the absence of hardware support.	MICRO	2002	DBLP DOI BibTeX RDF
63	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.	EUC Workshops	2006	DBLP DOI BibTeX RDF
62	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
60	Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke	Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.	MICRO	2005	DBLP DOI BibTeX RDF
60	Josep M. Codina, Josep Llosa, Antonio González 0001	A comparative study of modulo scheduling techniques.	ICS	2002	DBLP DOI BibTeX RDF	instruction level parallel architectures, instruction scheduling, Modulo scheduling, comparative study, quantitative evaluation
57	B. Ramakrishna Rau	Iterative modulo scheduling: an algorithm for software pipelining loops.	MICRO	1994	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, modulo scheduling, loop scheduling
53	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-dimension software pipelining for multidimensional loops.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Software pipelining, loop transformation, modulo scheduling
51	D. V. Ravindra, Y. N. Srikant	Improved Preprocessing Methods for Modulo Scheduling Algorithms.	HiPC	2002	DBLP DOI BibTeX RDF
50	Daniel Kästner, Markus Pister 0002	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
50	Josep M. Codina, F. Jesús Sánchez, Antonio González 0001	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF	register allocation, Modulo scheduling, clustered architectures, spill code, cluster assignment
48	Hyunchul Park 0001, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
48	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
47	Nikola Vujic, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture.	LCPC	2008	DBLP DOI BibTeX RDF	Cell BE Architecture, Modulo Scheduling, Pre-fetching, Software Cache
46	Lin Gao 0002, Quan Hoang Nguyen 0001, Lian Li 0002, Jingling Xue, Tin-Fook Ngai	Thread-Sensitive Modulo Scheduling for Multicore Processors.	ICPP	2008	DBLP DOI BibTeX RDF
43	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.	CC	2007	DBLP DOI BibTeX RDF
39	Matthew C. Merten, Wen-mei W. Hwu	Modulo schedule buffers.	MICRO	2001	DBLP DOI BibTeX RDF
38	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
38	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
38	Erik Nystrom, Alexandre E. Eichenberger	Effective Cluster Assignment for Modulo Scheduling.	MICRO	1998	DBLP DOI BibTeX RDF	ILP, modulo scheduling, cluster architecture, cluster assignment
38	Daniel M. Lavery, Wen-mei W. Hwu	Unrolling-based optimizations for modulo scheduling.	MICRO	1995	DBLP DOI BibTeX RDF	optimization, instruction-level parallelism, software pipelining, modulo scheduling, loop unrolling
37	Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham	Minimum register requirements for a modulo schedule.	MICRO	1994	DBLP DOI BibTeX RDF
36	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.	DATE	2003	DBLP DOI BibTeX RDF
36	Satish Pillai, Margarida F. Jacome	Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling.	DATE	2003	DBLP DOI BibTeX RDF
36	Josep Llosa, Eduard Ayguadé, Antonio González 0001, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
36	Eric Stotzer, Ernst L. Leiss	Modulo Scheduling for the TMS320C6x VLIW DSP Architecture.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
36	Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli	Demystifying on-the-fly spill code.	PLDI	2005	DBLP DOI BibTeX RDF	register allocation, modulo scheduling, spill code
34	Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank	Applying Data Speculation in Modulo Scheduled Loops.	IEEE PACT	2000	DBLP DOI BibTeX RDF
33	Yuan Lin 0002, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge	Hierarchical coarse-grained stream compilation for software defined radio.	CASES	2007	DBLP DOI BibTeX RDF	MPSoC compilation, dataflow programming model, software defined radio, modulo scheduling
33	SangMin Shim, Soo-Mook Moon	Split-Path Enhanced Pipeline Scheduling.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling
31	Mattias V. Eriksson, Christoph W. Kessler	Integrated Modulo Scheduling for Clustered VLIW Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF
31	F. Jesús Sánchez, Antonio González 0001	The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures.	ICPP	2000	DBLP DOI BibTeX RDF
31	Peter Pfahler, Georg Piepenbrock	A Comparison of Modulo Scheduling Techniques for Software Pipelining.	CC	1996	DBLP DOI BibTeX RDF	Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors
31	Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli	Removing communications in clustered microarchitectures through instruction replication.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	instruction replication, statically scheduled processors, ILP, modulo-scheduling, Clustered microarchitectures
31	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
29	Alban Douillet, Hongbo Rong, Guang R. Gao	Multi-dimensional Kernel Generation for Loop Nest Software Pipelining.	Euro-Par	2006	DBLP DOI BibTeX RDF
29	Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee	A software pipelining algorithm in high-level synthesis for FPGA architectures.	ISQED	2009	DBLP DOI BibTeX RDF
29	Alexandre E. Eichenberger, Edward S. Davidson	Efficient Formulation for Optimal Modulo Schedulers.	PLDI	1997	DBLP DOI BibTeX RDF
29	Erik R. Altman, Guang R. Gao	Optimal Software Pipelining Through Enumeration of Schedules.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
29	Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Jason Xue	Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.	DIPES	2008	DBLP DOI BibTeX RDF
29	Akira Hatanaka, Nader Bagherzadeh	A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template.	IPDPS	2007	DBLP DOI BibTeX RDF
29	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham	Distributed Modulo Scheduling.	HPCA	1999	DBLP DOI BibTeX RDF
26	Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis	Resource constrained modulo scheduling for coarse-grained reconfigurable arrays.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Noureddine Chabini, Wayne H. Wolf	Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
24	Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao	A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors.	ASAP	2000	DBLP DOI BibTeX RDF
21	Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke	CGRA express: accelerating execution using dynamic operation fusion.	CASES	2009	DBLP DOI BibTeX RDF	latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture
21	Miao Wang, Rongcai Zhao, Jianmin Pang, Guoming Cai	Reconstructing Control Flow in Modulo Scheduled Loops.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	register rotation, modulo scheduling, decompilation, predication execution, conditional branches
21	Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson	Latency-tolerant software pipelining in a production compiler.	CGO	2008	DBLP DOI BibTeX RDF	latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
21	Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis	A unified evaluation framework for coarse grained reconfigurable array architectures.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable romputing, Modulo scheduling, architectural exploration
21	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration for coarse grained reconfigurable arrays.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable computing, modulo scheduling, architectural exploration
21	Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke	Increasing hardware efficiency with multifunction loop accelerators.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware
21	Hyunchul Park 0001, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
21	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	register requirements, register file organization, clustered organization, Modulo scheduling, spill code
21	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
21	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	An interleaved cache clustered VLIW processor.	ICS	2002	DBLP DOI BibTeX RDF	attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
21	Dean Batten, Sanjay Jinturkar, C. John Glossner, Michael J. Schulte, Paul D'Arcy	A New Approach to DSP Intrinsic Functions.	HICSS	2000	DBLP DOI BibTeX RDF	Speech coders, intrinsic functions, profile-directed function inlining, performance analysis, instruction-level parallelism, software pipelining, speedup, modulo scheduling, loop optimization, code growth
21	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
21	SangMin Shim, Soo-Mook Moon	Split-path Enhanced Pipeline Scheduling for Loops with Control Flows.	MICRO	1998	DBLP DOI BibTeX RDF	all-path pipelining, enhanced pipeline scheduling, initiation interval, multi-path loops, software pipelining, modulo scheduling
20	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-Dimension Software Pipelining for Multi-Dimensional Loops.	CGO	2004	DBLP DOI BibTeX RDF
20	Greg Snider	Performance-constrained pipelining of software loops onto reconfigurable hardware.	FPGA	2002	DBLP DOI BibTeX RDF
17	Miao Wang, Rongcai Zhao, Guoming Cai	Un-speculation in Modulo Scheduled Loops.	IMSCCS	2007	DBLP DOI BibTeX RDF
16	Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda Calero, David Atienza, Laura Pozzi	SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs.	CoRR	2024	DBLP DOI BibTeX RDF
16	Li Lin, Song Mu, Bo Wang	modulo scheduling.		2023	DOI RDF
16	Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi	SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.	DATE	2023	DBLP DOI BibTeX RDF
16	Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi	SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.	CF	2023	DBLP DOI BibTeX RDF
16	Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf	Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Hongli Zhong, Zhong Liu, Sheng Liu 0001, Sheng Ma, Chen Li 0015	Adaptive Low-Cost Loop Expansion for Modulo Scheduling.	NPC	2022	DBLP DOI BibTeX RDF
16	Nicolai Fiege, Patrick Sittel, Peter Zipf	Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals.	FPL	2022	DBLP DOI BibTeX RDF
16	Nicolai Fiege, Patrick Sittel, Peter Zipf	Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling.	FCCM	2022	DBLP DOI BibTeX RDF
16	Hongli Zhong, Zhong Liu	Long-life Sensitive Modulo Scheduling with Adaptive Loop Expansion.	ICPADS	2022	DBLP DOI BibTeX RDF
16	Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato	Non-iterative SDC modulo scheduling for high-level synthesis.	Microprocess. Microsystems	2021	DBLP DOI BibTeX RDF
16	Hanna Kruppe, Lukas Sommer, Lukas Weber, Julian Oppermann, Cristian Axenie, Andreas Koch 0001	Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs.	SAMOS	2021	DBLP DOI BibTeX RDF
16	Zhongyuan Zhao 0004, Weiguang Sheng, Qin Wang 0009, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao	Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
16	Mahesh Balasubramanian 0001, Aviral Shrivastava	CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
16	Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf	Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design.	ASP-DAC	2020	DBLP DOI BibTeX RDF
16	Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Andreas Koch 0001, Oliver Sinnen	Exact and Practical Modulo Scheduling for High-Level Synthesis.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
16	Leandro de Souza Rosa, Christos-Savvas Bouganis, Vanderlei Bonato	Scaling Up Modulo Scheduling for High-Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
16	Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf	Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.	ReConFig	2019	DBLP DOI BibTeX RDF
16	Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch 0001, Oliver Sinnen	Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.	Euro-Par	2019	DBLP DOI BibTeX RDF
16	Steve Dai, Zhiru Zhang	Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning.	DAC	2019	DBLP DOI BibTeX RDF
16	Julian Oppermann	Advances in ILP-based Modulo Scheduling for High-Level Synthesis.		2019	RDF
16	Onur Mutlu, Scott A. Mahlke, Thomas M. Conte, Wen-Mei W. Hwu	Iterative Modulo Scheduling.	IEEE Micro	2018	DBLP DOI BibTeX RDF
16	Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch 0001	ILP-Based Modulo Scheduling and Binding for Register Minimization.	FPL	2018	DBLP DOI BibTeX RDF
16	Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch 0001	Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.	FPL	2018	DBLP DOI BibTeX RDF
16	Julian Oppermann, Sebastian Vollbrecht, Melanie Reuter-Oppermann, Oliver Sinnen, Andreas Koch 0001	GeMS: a generator for modulo scheduling problems: work in progress.	CASES	2018	DBLP BibTeX RDF
16	Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei	Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
16	Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei	Memory fartitioning-based modulo scheduling for high-level synthesis.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei	Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Ricardo S. Ferreira 0001, Waldir Denver, Monica Magalhães Pereira, Stephan Wong, Carlos Arthur Lang Lisbôa, Luigi Carro	A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
16	Julian Oppermann, Andreas Koch 0001, Melanie Reuter-Oppermann, Oliver Sinnen	ILP-based modulo scheduling for high-level synthesis.	CASES	2016	DBLP DOI BibTeX RDF
16	Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich	Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.	ASAP	2016	DBLP DOI BibTeX RDF
16	Ricardo S. Ferreira 0001, Waldir Denver, Monica Magalhães Pereira, Jorge Quadros, Luigi Carro, Stephan Wong	A run-time modulo scheduling by using a binary translation mechanism.	ICSAMOS	2014	DBLP DOI BibTeX RDF
16	Mounir Bahtat, Said Belkouch, Philippe Elleaume, Phillipe Le Gall	Fast enumeration-based modulo scheduling heuristic for VLIW architectures.	ICM	2014	DBLP DOI BibTeX RDF
16	Nikolai Kim, Andreas Krall	Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture.	ODES@CGO	2014	DBLP DOI BibTeX RDF
16	Maria Ayala, Abir Benabid, Christian Artigues, Claire Hanen	The resource-constrained modulo scheduling problem: an experimental study.	Comput. Optim. Appl.	2013	DBLP DOI BibTeX RDF
16	Ricardo S. Ferreira 0001, Vinicius Duarte, Waldir Meireles, Monica Magalhães Pereira, Luigi Carro, Stephan Wong	A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures.	ICSAMOS	2013	DBLP DOI BibTeX RDF
16	Zhiru Zhang, Bin Liu 0006	SDC-based modulo scheduling for pipeline synthesis.	ICCAD	2013	DBLP DOI BibTeX RDF