Search results for "multiple-instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita	SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.	ISCA	1989	DBLP DOI BibTeX RDF
52	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
49	Michael Scherger, Johnnie W. Baker, Jerry L. Potter	Multiple Instruction Stream Control for an Associative Model of Parallel Computation.	IPDPS	2003	DBLP DOI BibTeX RDF	Multiple instruction streams, associative computing, parallel processing, system software
41	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP DOI BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
32	Juan E. Gilbert, Chia Y. Han 0001	Researching Adaptive Instruction.	AH	2000	DBLP DOI BibTeX RDF
31	Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto	Multiple instruction streams in a highly pipelined processor.	SPDP	1990	DBLP DOI BibTeX RDF
30	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
30	Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker	A Distributed Control Path Architecture for VLIW Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
29	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS (1)	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
27	Sanjay Ranka, Sartaj Sahni	Clustering on a Hypercube Multicomputer.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	square error, clustering problem, NMK processors, multiple-data, parallel algorithms, computational complexity, hypercube networks, single-instruction multiple-data, SIMD, MIMD, hypercube multicomputer, multiple-instruction
27	Mark R. Thistle, Burton J. Smith	A processor architecture for horizon.	SC	1988	DBLP DOI BibTeX RDF
24	Andrew R. Pleszkun, Gurindar S. Sohi	Multiple instruction issue and single-chip processors.	MICRO	1988	DBLP BibTeX RDF
24	Charles C. Weems, Christopher M. Brown, Jon A. Webb, Tomaso A. Poggio, John R. Kender	Parallel Processing in the DARPA Strategic Computing Vision Program.	IEEE Expert	1991	DBLP DOI BibTeX RDF
22	Matthew T. O'Keefe, Henry G. Dietz	Loop Coalescing and Scheduling for Barrier MIMD Architectures.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	barrier MIMD, multiple instruction stream, multiple datastream, loop coalescing, nested loop structures, compiler parallelization, static barrierMIMD, scheduling, scheduling, parallel programming, parallel architectures, compiler optimization, program compilers, asynchronous, loop transformations, barrier synchronization, linear scheduling
22	Paolo Cremonesi, Claudio Gennaro	Integrated Performance Models for SPMD Applications and MIMD Architectures.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	fork-join queues, mean value analysis (MVA), speedup surface, performance model, parallel I/O, multiple instruction multiple data (MIMD), Single program multiple data (SPMD), synchronization overhead, queuing network model
22	Paolo Cremonesi, Claudio Gennaro	Integrated Performance Models for SPMD Applications and MIMD Architectures.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	fork-join queues, mean value analysis (MVA), speedup surface, performance model, parallel I/O, multiple instruction multiple data (MIMD), Single program multiple data (SPMD), synchronization overhead, queuing network model
22	C. V. Ramakrishnan, S. Ramesh Kumar	Comparative Performance of Frontal (Direct) and PCG (Iterative) Solver Based Parallel Computations of Finite Element Analysis.	IPDPS	2002	DBLP DOI BibTeX RDF	Finite Element Analysis (FEA), Symmetric Multi-processor (SMP), Preconditioned Conjugate Gradient (PCG), degrees of freedom (dof), maximum bandwidth (mbwd), maximum frontwidth (mfwd), Number of processors (Numprocs), iterations (iter), Message Passing Interface (MPI), Single Instruction Multiple Data (SIMD), Multiple Instruction Multiple Data (MIMD)
22	Weijia Shang, José A. B. Fortes	Independent Partitioning of Algorithms with Uniform Dependencies.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	uniform dependence algorithms, index sets, maximal independent partitions, optimality, parallel algorithms, computational complexity, computational complexity, lower bounds, upper bounds, multiple instruction multiple data, cardinality, MIMD machines
22	Richard G. Cooper	The Distributed Pipeline.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer
21	Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven	Static instruction scheduling for the HARP multiple-instruction-issue architecture.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
21	Liang Wang 0016	Instruction scheduling for a family of multiple instruction issue architectures.		1993	RDF
21	James Phillips, Stamatis Vassiliadis	High-Performance 3-1 Interlock Collapsing ALU's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations
19	Stephen Hines, Gary S. Tyson, David B. Whalley	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.	MICRO	2005	DBLP DOI BibTeX RDF
19	Muhamed F. Mudawar	Scalable cache memory design for large-scale SMT architectures.	WMPI	2004	DBLP DOI BibTeX RDF	scalable multiported cache memory, simultaneous multithreaded architectures
19	Montserrat Ros, Peter Sutton	Compiler optimization and ordering effects on VLIW code compression.	CASES	2003	DBLP DOI BibTeX RDF	compiler optimizations, VLIW, code compression
18	Jaume Abella 0001, Antonio González 0001	SAMIE-LSQ: set-associative multiple-instruction entry load/store queue.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang 0003, John Paul Shen	Multiple Instruction Stream Processor.	ISCA	2006	DBLP DOI BibTeX RDF
18	Pradeep Rao, S. K. Nandy 0001, M. N. V. Satya Kiran	Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
18	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
18	Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso	Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors.	ASPLOS	1998	DBLP DOI BibTeX RDF
16	Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu	MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.	CoRR	2024	DBLP DOI BibTeX RDF
16	Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu	MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.	HPCA	2024	DBLP DOI BibTeX RDF
16	Esmaeil Amini, Zahra Jeddi, Ahmed K. F. Khattab, Magdy A. Bayoumi	Performance Evaluation and Design Optimization for Flexible Multiple Instruction Multiple Data Elliptic Curve Cryptography Crypto Architecture.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
16	Rolf Riesen, Arthur B. Maccabe	MIMD (Multiple Instruction, Multiple Data) Machines.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
16	Nick Bailey, Alan Purvis, Peter D. Manning, Ian Bowler, Durham Music Technology	Some observations on hierarchical, multiple-instruction-multiple-data computers.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
16	Martin R. Stytz	Three-dimensional medical image analysis using local dynamic algorithm selection on a multiple-instruction, multiple-data architecture.		1989	RDF
16	Charles H. Radoy, G. Jack Lipovski	Switched Multiple Instruction, Multiple Data Stream Processing.	ISCA	1974	DBLP DOI BibTeX RDF
15	Daniel R. Johnson, Matthew R. Johnson 0003, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Rigel: A 1, 024-Core Single-Chip Accelerator Architecture.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Multiple data-stream architectures (multiprocessors), multiple data processors, single-chip multiprocessors, parallel architectures, multicore, parallel processors, multiple instruction
15	Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, Adrian Florea	An alternative to branch prediction: pre-computed branches.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	complexity evaluations, multiple instruction issue, performance, pipelining, speculative execution, execution driven simulation, dynamic branch prediction
15	Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung	Design of Instruction Stream Buffer with Trace Support for X86 Processors.	ICCD	2000	DBLP DOI BibTeX RDF	instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache
15	Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte	MPS: Miss-Path Scheduling for Multiple-Issue Processors.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Multiple instruction issue, miss path scheduling, schedule cache, instruction level parallelism
15	Ramón D. Acosta, Jacob Kjelstrup, Hwa C. Torng	An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	processor performance enhancement, Dispatch stack, instruction issuing, instruction unit, multiple functional unit processors, multiple instruction dispatching, dynamic instruction scheduling
15	James T. Kuehn, Burton J. Smith	The horizon supercomputing system: architecture and software.	SC	1988	DBLP DOI BibTeX RDF
13	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003	Sequencer virtualization.	ICS	2007	DBLP DOI BibTeX RDF	virtualization, multi-cores, MIMD
13	Austin Rogers, Milena Milenkovic, Aleksandar Milenkovic	A low overhead hardware technique for software integrity and confidentiality.	ICCD	2007	DBLP DOI BibTeX RDF
13	Darrell R. Ulm, Michael Scherger	Stream PRAM.	IPDPS	2005	DBLP DOI BibTeX RDF
13	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
12		Multiple-Instruction Issue.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
12	Hussein Karaki, Haitham Akkary	Multiple instruction sets architecture (MISA).	ICEAC	2011	DBLP DOI BibTeX RDF
12	Wittaya Chantamas, Johnnie W. Baker, Michael Scherger	An Extension of the ASC Language Compiler to Support Multiple Instruction Streams in the MASC Model using the Manager-Worker Paradigm.	PDPTA	2006	DBLP BibTeX RDF
12	Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu	IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
12	Wen-mei W. Hwu	Retrospective: IMPACT: An Architectural Framework for Multiple-Instruction Issue.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
12	Simon A. Trainis	Modelling the hardware cost of full register bypassing in a multiple instruction issue processor.	J. Syst. Archit.	1997	DBLP BibTeX RDF
12	Darrell R. Ulm, Johnnie W. Baker	Virtual Parallelism by Self Simulation of the multiple Instruction Stream Associate Model.	PDPTA	1996	DBLP BibTeX RDF
12	Chung-Chi Jim Li, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	Compiler-Based Multiple Instruction Retry.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	compilers, fault-tolerant computing, rollback recovery, instruction retry
12	Neal J. Alewine, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Fault-tolerance, compilers, error recovery, instruction retry
12	Christine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn	Allocating registers in multiple instruction-issuing processors.	PACT	1995	DBLP BibTeX RDF
12	Yamin Li, Wanming Chu	Design and Implementation of a Multiple-Instruction-Stream.	Parallel and Distributed Computing and Systems	1995	DBLP BibTeX RDF
12	Shlomo Weiss	Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors.	HPCA	1995	DBLP DOI BibTeX RDF
12	Gary S. Tyson, Matthew K. Farrens	Code scheduling for multiple instruction stream architectures.	Int. J. Parallel Program.	1994	DBLP DOI BibTeX RDF
12	Shyh-Kwei Chen, Neal J. Alewine, W. Kent Fuchs, Wen-mei W. Hwu	Incremental Compiler Transformations for Multiple Instruction Retry.	Softw. Pract. Exp.	1994	DBLP DOI BibTeX RDF
12	Rod Adams, Sue M. Gray, Gordon B. Steven	Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler.	PDP	1994	DBLP DOI BibTeX RDF
12	Manoj Franklin, Mark Smotherman	A fill-unit approach to multiple instruction issue.	MICRO	1994	DBLP DOI BibTeX RDF	multiple operation issue, instruction-level parallelism, VLIW, superscalar
12	Mayan Moudgill	Implementing and Exploiting Static Speculation on Multiple Instruction Issue Processors.		1994	RDF
12	Soo-Mook Moon, Kemal Ebcioglu	A study on the number of memory ports in multiple instruction issue machines.	MICRO	1993	DBLP DOI BibTeX RDF	memory ports, speculative loads, ILP, static scheduling, memory disambiguation
12	Neal J. Alewine	Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer		1993	RDF
12	Neal J. Alewine, Shyh-Kwei Chen, Chung-Chi Jim Li, W. Kent Fuchs, Wen-mei W. Hwu	Branch Recovery with Compiler-Assisted Multiple Instruction Retry.	FTCS	1992	DBLP DOI BibTeX RDF
12	Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun	MISC: a Multiple Instruction Stream Computer.	MICRO	1992	DBLP DOI BibTeX RDF
12	Paul Spee, Weng-Fai Wong, Eiichi Goto	Effects of Multiple Instruction Stream Execution on Cache Performance.	Int. J. High Speed Comput.	1991	DBLP DOI BibTeX RDF
12	Masahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi	Parallel execution on the function-partitioned processor with multiple instruction streams.	Syst. Comput. Jpn.	1991	DBLP DOI BibTeX RDF
12	Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu	Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.	MICRO	1991	DBLP DOI BibTeX RDF
12	George E. Daddis Jr., Hwa C. Torng	The Concurrent Execution of Multiple Instruction Streams on Superscalar Processors.	ICPP (1)	1991	DBLP BibTeX RDF
12	Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu	IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.	ISCA	1991	DBLP DOI BibTeX RDF
12	Po-hua Chang	Compiler support for multiple-instruction-issue architectures		1991	RDF
12	Robert W. Horst, Richard L. Harris, Robert L. Jardine	Multiple Instruction Issue in the NonStop Cyclone Processor.	ISCA	1990	DBLP DOI BibTeX RDF
12	Michael D. Smith 0001, Mike Johnson, Mark Horowitz	Limits on Multiple Instruction Issue.	ASPLOS	1989	DBLP DOI BibTeX RDF
12	William Joseph Kaminsky Jr., Edward S. Davidson	Special Feature: Developing a Multiple-Instruction-Stream Single-Chip Processor.	Computer	1979	DBLP DOI BibTeX RDF
12	Joel S. Emer	Shared Resources for Multiple Instruction Stream Pipelined Processors		1979	RDF
12	William Joseph Kaminsky Jr.	Architecture for Multiple Instruction Stream Lsi Processors		1977	RDF
12	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen 0001, Tao Zhang	Supporting OpenMP on Cell.	IWOMP	2007	DBLP DOI BibTeX RDF
12	Olaf René Birkeland, O. Snøve, Arne Halaas, Magnar Nedland, Pål Sætrom	The Petacomp Machine: A MIMD Cluster for Parallel Pattern-mining.	CLUSTER	2006	DBLP DOI BibTeX RDF
12	Robert Allen, Luigi Cinque, Steven L. Tanimoto, Linda G. Shapiro, Dean Yasuda	A Parallel Algorithm for Graph Matching and Its MasPar Implementation.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	MasPar, combinatorial explosion, forward checking, parallel algorithm, load balancing, search, Graph, matching, branch-and-bound, SIMD
11	Darrell R. Ulm, Johnnie W. Baker, Michael C. Scherger	Solving a 2D Knapsack Problem Using a Hybrid Data-Parallel/Control Style of Computing.	IPDPS	2004	DBLP DOI BibTeX RDF
11	Dennis E. Shasha, Marc Snir	Efficient and Correct Execution of Parallel Programs that Share Memory.	ACM Trans. Program. Lang. Syst.	1988	DBLP DOI BibTeX RDF
9	Bernhard Fechner	A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.	PARELEC	2006	DBLP DOI BibTeX RDF
9	Won Woo Ro, Jean-Luc Gaudiot	A Low-Complexity Issue Queue Design with Speculative Pre-execution.	HiPC	2005	DBLP DOI BibTeX RDF
9	C. John Glossner, Stamatis Vassiliadis	Delft-Java Dynamic Translation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Guang R. Gao, Herbert H. J. Hum, Jean-Marc Monti	Towards an Efficient Hybrid Dataflow Architecture Model.	PARLE (1)	1991	DBLP DOI BibTeX RDF
9	David A. Carlson, John M. Conroy	The fast fourier transform and sparse matrix computations: a study of two applications on teh HORIZON supercomputer.	SC	1988	DBLP DOI BibTeX RDF
9	Edward E. E. Frietman, Ramon J. Ernst, Roy E. Crosbie, Masao Shimoji	Prospects for Optical Interconnects in Distributed, Shared-Memory Organized MIMD Architectures.	J. Supercomput.	1999	DBLP DOI BibTeX RDF	free space data distributing system, fully connected topology, multi-stage interconnection scheme, opto electronic logic elements, photonic integrated circuits, distributed-shared memory systems
9	Renbing Xiong, Theodore Brown	Parallel Median Splitting and k-Splitting with Application to Merging and Sorting.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	k-splitting, median splitting, parallel splitting, parallel algorithms, sorting, sorting, merging
8	Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke	Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications.	HPCA	2007	DBLP DOI BibTeX RDF
8	Arne Halaas, Børge Svingen, Magnar Nedland, Pål Sætrom, Ola R. Snøve Jr., Olaf René Birkeland	A recursive MISD architecture for pattern matching.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
8	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy	A Method for Register Allocation to Loops in Multiple Register File Architectures.	IPPS	1996	DBLP DOI BibTeX RDF
8	Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata	Cellular array processor CAP and applications.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
7	Gareth E. Evans, Jonathan M. Keith, Dirk P. Kroese	Parallel cross-entropy optimization.	WSC	2007	DBLP DOI BibTeX RDF
7	Thomas M. Keane, Richard Allen, Thomas J. Naughton, James O. McInerney, John Waldron	Distributed computing for DNA analysis.	PPPJ/IRE	2002	DBLP DOI BibTeX RDF	Java
7	Thomas M. Keane, Richard Allen, Thomas J. Naughton, James O. McInerney, John Waldron	Distributed Java Platform with Programmable MIMD Capabilities.	FIDJI	2002	DBLP DOI BibTeX RDF
7	Klaus Herrmann 0002, Jan Otterstedt, Hartwig Jeschke, M. Kuboschek	A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm2 monolithic implementation.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
7	James K. Ho, R. P. Sundarraj 0001	Distributed Nested Decomposition of Staircase Linear Programs.	ACM Trans. Math. Softw.	1997	DBLP DOI BibTeX RDF	computational linear programming, distributed computation