Search results for "multiply-add"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	David López 0001, Josep Llosa, Eduard Ayguadé, Mateo Valero	Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.	ICPP	1999	DBLP DOI BibTeX RDF	ILP limits, multiply-add fused, performance/cost evaluation, software pipelining, VLIW architectures, numerical code
82	Ahmed Sherif Zekri, Stanislav G. Sedukhin	Matrix Transpose on 2D Torus Array Processor.	CIT	2006	DBLP DOI BibTeX RDF
80	Yves Nievergelt	Scalar fused multiply-add instructions produce floating-point matrix arithmetic provably accurate to the penultimate digit.	ACM Trans. Math. Softw.	2003	DBLP DOI BibTeX RDF	Doubly compensated summation, fused multiply-add instruction, matrix arithmetic, provable accuracy, floating-point arithmetic, rounding error
66	Gongqiong Li, Zhaolin Li	Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit.	VLSI Design	2007	DBLP DOI BibTeX RDF
66	Romesh M. Jessani, Michael Putrino	Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	multiply-add fused, multiply array, alignment shifter, sign encoding, Floating-point unit, Booth encoding
64	Edwin A. Hakkennes, Stamatis Vassiliadis	Multimedia Execution Hardware Accelerator.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	multimedia architectures, multimedia instruction set, multimedia processors, compound instructions, multimedia, hardware accelerators, subword parallelism, SIMD processors, vector architectures
62	Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds	Bridge Floating-Point Fused Multiply-Add Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
59	David Raymond Lutz	Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add Pipelines.	IEEE Symposium on Computer Arithmetic	2011	DBLP DOI BibTeX RDF
57	Libo Huang, Li Shen 0007, Kui Dai, Zhiying Wang 0003	A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
57	Ahmed Sherif Zekri, Stanislav G. Sedukhin	The general matrix multiply-add operation on 2D torus.	IPDPS	2006	DBLP DOI BibTeX RDF
57	Arch D. Robison	N-Bit Unsigned Division via N-Bit Multiply-Add.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
53	Yevgen Voronenko, Markus Püschel	Mechanical Derivation of Fused Multiply-Add Algorithms for Linear Transforms.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
50	Mikio Takeuchi, Hideaki Komatsu, Toshio Nakatani	A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility.	ICS	2003	DBLP DOI BibTeX RDF	bit-by-bit reproducibility, floating-point speculation, fused multiply-add, reassociation, striding, Java, prefetching, accuracy, instruction-level parallelism, software pipelining, just-in-time compiler, loop unrolling, privatization, IA-64, IEEE 754
50	Julien Zory, Fabien Coelho	Using Algebraic Transformations to Optimize Expression Evaluation in Scientific Codes.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Algebraic transformation, Fused multiply-add operation, Instruction-Level Parallelism, Expression evaluation
45	Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei	A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating.	ASP-DAC	2021	DBLP DOI BibTeX RDF
45	Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi	Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding.	Integr.	2014	DBLP DOI BibTeX RDF
44	Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis	On the design of efficient modulo 2n+1 multiply-add-add units.	DTIS	2014	DBLP DOI BibTeX RDF
43	Zhaolin Li, Gongqiong Li	Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence.	ISVLSI	2007	DBLP DOI BibTeX RDF
43	Gongqiong Li, Zhaolin Li	Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.	ICCD	2007	DBLP DOI BibTeX RDF
43	Humberto Calderon, Stamatis Vassiliadis	Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit.	ASAP	2006	DBLP DOI BibTeX RDF
43	Christian Jacobi 0002, Kai Weber 0001, Viresh Paruthi, Jason Baumgartner	Automatic Formal Verification of Fused-Multiply-Add FPUs.	DATE	2005	DBLP DOI BibTeX RDF
43	Javier D. Bruguera, Tomás Lang	Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
43	Tomás Lang, Javier D. Bruguera	Floating-Point Multiply-Add-Fused with Reduced Latency.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
43	Tomás Lang, Javier D. Bruguera	Floating-Point Fused Multiply-Add with Reduced Latency.	ICCD	2002	DBLP DOI BibTeX RDF
43	Fred G. Gustavson, José E. Moreira, Robert F. Enenkel	The fused multiply-add instruction leads to algorithms for extended-precision floating point: applications to java and high-performance computing.	CASCON	1999	DBLP BibTeX RDF	Java
36	Ali Sentürk, Mustafa Gök	A Fast Modular Multiplication Method.	IIH-MSP	2010	DBLP DOI BibTeX RDF	modular multiplication method, multiply-add
36	Yves Nievergelt	Analysis and applications of Priest's distillation.	ACM Trans. Math. Softw.	2004	DBLP DOI BibTeX RDF	fused multiply-add instruction, matrix arithmetic, provable accuracy, interval arithmetic, Floating-point arithmetic, rounding error, complex arithmetic
36	Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang	Scientific computing on the Itanium processor.	SC	2001	DBLP DOI BibTeX RDF	fused multiply-add, itanium (TM) processor, linear algebra, Intel, EPIC, transcendental functions
36	Naofumi Takagi	A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	division subtraction, radix-4 modular multiplication hardware algorithm, residue calculation, repeated multiply-add, serial-parallel modular multiplier, cellular array structure, VLSI, cryptography, digital arithmetic, public-key cryptosystems, modular exponentiation, RSA cryptosystem, redundant representation, bit slice
32	Pavel Emeliyanenko	Efficient Multiplication of Polynomials on Graphics Hardware.	APPT	2009	DBLP DOI BibTeX RDF	large integer arithmetic, parallel computations, GPU, graphics hardware, CUDA
32	Akashi Satoh, Takeshi Sugawara 0001, Takafumi Aoki	High-Speed Pipelined Hardware Architecture for Galois Counter Mode.	ISC	2007	DBLP DOI BibTeX RDF
32	Akashi Satoh	High-Speed Parallel Hardware Architecture for Galois Counter Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Tianyi Zhang, Jonah Wonkyu Yi, Bowen Yao, Zhaozhuo Xu, Anshumali Shrivastava	NoMAD-Attention: Efficient LLM Inference on CPUs Through Multiply-add-free Attention.	CoRR	2024	DBLP DOI BibTeX RDF
30	Seunghwan Sung, Sujin Hur, Sungwoo Kim, Dongho Ha, Yunho Oh, Won Woo Ro	MAD MAcce: Supporting Multiply-Add Operations for Democratizing Matrix-Multiplication Accelerators.	MICRO	2023	DBLP DOI BibTeX RDF
30	Jongwook Sohn, David K. Dean, Eric Quintana, Wing Shek Wong	Enhanced Floating-Point Multiply-Add with Full Denormal Support.	ARITH	2023	DBLP DOI BibTeX RDF
30	Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon	A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
30	David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju	Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking.	ARITH	2022	DBLP DOI BibTeX RDF
30	Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon	A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees.	AICAS	2022	DBLP DOI BibTeX RDF
30	Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon	A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree.	ISSCC	2021	DBLP DOI BibTeX RDF
30	Pierre Blanchard, Nicholas J. Higham, Florent Lopez, Théo Mary, Srikara Pranesh	Mixed Precision Block Fused Multiply-Add: Error Analysis and Application to GPU Tensor Cores.	SIAM J. Sci. Comput.	2020	DBLP DOI BibTeX RDF
30	James You, Qi Zhang, Curtis D'Alves, Bill O'Farrell, Christopher Kumar Anand	Using z14 Fused-Multiply-Add Instructions to Accelerate Elliptic Curve Cryptography.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
30	Javier Hormigo, Julio Villalba-Moreno, Sonia Gonzalez-Navarro	Floating-Point Fused Multiply-Add under HUB Format.	ARITH	2020	DBLP DOI BibTeX RDF
30	Hao Zhang 0041, Dongdong Chen 0002, Seok-Bum Ko	Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support.	IEEE Trans. Computers	2019	DBLP DOI BibTeX RDF
30	Felix Kaiser, Stefan Kosnac, Ulrich Brüning 0001	Development of a RISC-V-Conform Fused Multiply-Add Floating-Point Unit.	Supercomput. Front. Innov.	2019	DBLP DOI BibTeX RDF
30	Kayode A. Sanni, Andreas G. Andreou	A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2019	DBLP DOI BibTeX RDF
30	Tongxin Yang, Toshinori Sato, Tomoaki Ukezono	A Low-Power Approximate Multiply-Add Unit.	ISDCS	2019	DBLP DOI BibTeX RDF
30	Alberto Nannarelli	Fused Multiply-Add for Variable Precision Floating-Point.	SoCC	2019	DBLP DOI BibTeX RDF
30	James You, Qi Zhang, Curtis D'Alves, Bill O'Farrell, Christopher Kumar Anand	Using z14 fused-multiply-add instructions to accelerate elliptic curve cryptography.	CASCON	2019	DBLP BibTeX RDF
30	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero	Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
30	Arunachalam Venkatesan, Alex Noel Joseph Raj, Naveen Hampannavar, C. B. Bidul	Efficient dual-precision floating-point fused-multiply-add architecture.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
30	Clothilde Jeangoudoux, Christoph Quirin Lauter	A Correctly Rounded Mixed-Radix Fused-Multiply-Add.	ARITH	2018	DBLP DOI BibTeX RDF
30	Ahmed A. Wahba, Hossam A. H. Fahmy	Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
30	Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi	Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units.	SIGARCH Comput. Archit. News	2016	DBLP DOI BibTeX RDF
30	Liu Han, Hao Zhang 0041, Seok-Bum Ko	Decimal floating-point fused multiply-add with redundant internal encodings.	IET Comput. Digit. Tech.	2016	DBLP DOI BibTeX RDF
30	Hyunpil Kim, Sangook Moon	Proxy Bits for Low Cost Floating-Point Fused Multiply-Add Unit.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
30	Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras	An efficient multiple precision floating-point Multiply-Add Fused unit.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
30	Yuri Stepchenkov, Victor N. Zakharov, Yuri Rogdestvenski, Yuri Diachenko, Nickolaj Morozov, Dmitri Stepchenkov	Speed-independent fused multiply add and subtract unit.	EWDTS	2016	DBLP DOI BibTeX RDF
30	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero	A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.	ISLPED	2016	DBLP DOI BibTeX RDF
30	Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras	Dynamic delay variation behaviour of RNS multiply-add architectures.	ISCAS	2016	DBLP DOI BibTeX RDF
30	Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re	Characterization of RNS multiply-add units for power efficient DSP.	MWSCAS	2015	DBLP DOI BibTeX RDF
30	Sandeep Kakde, Mithilesh Mahindra, Atish Khobragade, Nikit Shah	FPGA Implementation of 128-Bit Fused Multiply Add Unit for Crypto Processors.	SSCC	2015	DBLP DOI BibTeX RDF
30	Alexandru Amaricai, Oana Boncalo, Constantina-Elena Gavriliu	Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays.	IET Comput. Digit. Tech.	2014	DBLP DOI BibTeX RDF
30	Marc Lupon, Enric Gibert, Grigorios Magklis, Sridhar Samudrala, Raúl Martínez, Kyriakos Stavrou, David R. Ditzel	Speculative hardware/software co-designed floating-point multiply-add fusion.	ASPLOS	2014	DBLP DOI BibTeX RDF
30	Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi	On the design of modulo 2n + 1 dot product and generalized multiply-add units.	Comput. Electr. Eng.	2013	DBLP DOI BibTeX RDF
30	Kun-Yi Wu, Chih-Yuan Liang, Kee-Khuan Yu, Shiann-Rong Kuang	Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption.	ICIS	2013	DBLP DOI BibTeX RDF
30	Bin Xue, Prosenjit Chatterjee, Sandeep K. Shukla	Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models.	ASP-DAC	2013	DBLP DOI BibTeX RDF
30	Jun He, Biao Wang, Ying Zhu	Design of a Quadruple Precision Floating-Point Fused Multiply-Add Unit Based on 4-Way SIMD Device.	NAS	2013	DBLP DOI BibTeX RDF
30	Neil Burgess, David Raymond Lutz	Exhaustive testing of Fused Multiply-Add RTL.	ACSSC	2013	DBLP DOI BibTeX RDF
30	Björn Liebig, Jens Huthmann, Andreas Koch 0001	Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis.	IPDPS Workshops	2013	DBLP DOI BibTeX RDF
30	Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Steven Hsu, Amit Agarwal 0001, Farhana Sheikh, Ram Krishnamurthy 0001, Shekhar Borkar	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
30	Theo Drane, Wai-chuen Cheung, George A. Constantinides	Correctly rounded constant integer division via multiply-add.	ISCAS	2012	DBLP DOI BibTeX RDF
30	Ioannis Kouretas, Vassilis Paliouras	Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation.	ISCAS	2012	DBLP DOI BibTeX RDF
30	Ahmet Akkas, Michael J. Schulte	A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator.	ASAP	2011	DBLP DOI BibTeX RDF
30	Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Rodina Samy	Verification of decimal floating-point fused-multiply-add operation.	AICCSA	2011	DBLP DOI BibTeX RDF
30	Xiao Yan Zhang, Yiu-Hing Chan, Robert K. Montoye, Leon J. Sigal, Eric M. Schwarz, Michael Kelly	A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit.	J. Signal Process. Syst.	2010	DBLP DOI BibTeX RDF
30	Ioannis Kouretas, Vassilis Paliouras	Residue Arithmetic for Designing Low-Power Multiply-Add Units.	PATMOS	2010	DBLP DOI BibTeX RDF
30	Stanislav G. Sedukhin, Toshiaki Miyazaki	Rapid*Closure: Algebraic Extensions of a Scalar Multiply-add Operation.	CATA	2010	DBLP BibTeX RDF
30	Ioannis Kouretas, Vassilis Paliouras	RNS multi-voltage low-power multiply-add unit.	ICECS	2010	DBLP DOI BibTeX RDF
30	Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras	An efficient dual-mode floating-point Multiply-Add Fused Unit.	ICECS	2010	DBLP DOI BibTeX RDF
30	Kazuya Matsumoto, Stanislav G. Sedukhin	Matrix Multiply-Add in Min-plus Algebra on a Short-Vector SIMD Processor of Cell/B.E..	ICNC	2010	DBLP DOI BibTeX RDF
30	Zichu Qi, Qi Guo 0001, Ge Zhang 0007, Xiangku Li, Weiwu Hu	Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power.	VLSI Design	2010	DBLP DOI BibTeX RDF	FMA, dual-path FMA, low-power design
30	Sylvie Boldo, Marc Daumas, Ren-Cang Li	Formally Verified Argument Reduction with a Fused Multiply-Add.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
30	Ioannis Kouretas, Vassilis Paliouras	Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units.	PATMOS	2009	DBLP DOI BibTeX RDF
30	Jochen Preiss, Maarten Boersma, Silvia Melitta Müller	Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units.	IEEE Symposium on Computer Arithmetic	2009	DBLP DOI BibTeX RDF
30	Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis	A configurable length, Fused Multiply-Add floating point unit for a VLIW processor.	SoCC	2009	DBLP DOI BibTeX RDF
30	Sylvie Boldo, Marc Daumas, Ren-Cang Li	Formally Verified Argument Reduction with a Fused-Multiply-Add	CoRR	2007	DBLP BibTeX RDF
30	Ahmed Sherif Zekri, Stanislav G. Sedukhin	Fine-grained Matrix Multiply-Add on a Torus Array Processor.	CATA	2007	DBLP BibTeX RDF
30	Takahiro Nagai, Hitoshi Yoshida, Hisayasu Kuroda, Yasumasa Kanada	Fast Quadruple Precision Arithmetic for Multiply/Add Operations on SR11000/J2.	CSC	2007	DBLP BibTeX RDF
30	Jaafar Alghazo, Nazeih Botros	Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs.	CDES	2005	DBLP BibTeX RDF
30	Haiping Wu, Ziang Hu, Joseph B. Manzano, Yingping Zhang, Guang R. Gao	Identifying Multiply-Add Operations in Kylin Compiler.	ESA	2005	DBLP BibTeX RDF
30	Yevgen Voronenko, Markus Püschel	Automatic generation of implementations for DSP transforms on fused multiply-add architectures.	ICASSP (5)	2004	DBLP DOI BibTeX RDF
30	Daisuke Takahashi	A radix-16 FFT algorithm suitable for multiply-add instruction based on Goedecker method.	ICASSP (2)	2003	DBLP DOI BibTeX RDF
30	Hakob Sarukhanyan, Sos S. Agaian, Jaakko T. Astola, Karen O. Egiazarian	Binary matrices, decomposition and multiply-add architectures.	Image Processing: Algorithms and Systems	2003	DBLP DOI BibTeX RDF
30	Daisuke Takahashi	A radix-16 FFT algorithm suitable for multiply-add instruction based on Goedecker method.	ICME	2003	DBLP DOI BibTeX RDF
30	Vladik Kreinovich	Itanium's new basic operation of fused multiply-add: theoretical explanation and theoretical challenge.	SIGACT News	2001	DBLP DOI BibTeX RDF
30	Daisuke Takahashi	A new radix-6 FFT algorithm suitable for multiply-add instruction.	ICASSP	2000	DBLP DOI BibTeX RDF
30	Stefan Goedecker	Fast Radix 2, 3, 4, and 5 Kernels for Fast Fourier Transformations on Computers with Overlapping Multiply-Add Instructions.	SIAM J. Sci. Comput.	1997	DBLP DOI BibTeX RDF
30	Don Coppersmith, Ephraim Feig, Elliot N. Linzer	Hadamard transforms on multiply/add architectures.	IEEE Trans. Signal Process.	1994	DBLP DOI BibTeX RDF
30	Elliot N. Linzer, Ephraim Feig	Implementation of Efficient FFT Algorithms on Fused Multiply- Add Architectures.	IEEE Trans. Signal Process.	1993	DBLP DOI BibTeX RDF
30	Elliot N. Linzer, Ephraim Feig	New scaled DCT algorithms for fused multiply/add architectures.	ICASSP	1991	DBLP DOI BibTeX RDF