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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1003 occurrences of 375 keywords
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Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
116 | Jinwen Xi, Peixin Zhong |
A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 341-344, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, SystemC, energy model |
111 | Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo |
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 30-39, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
107 | Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
The Power of Priority: NoC Based Distributed Cache Coherency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 117-126, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
95 | Avinoam Kolodny |
Networks on chips: keeping up with Rent's rule and Moore's law. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 55-56, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, timing, interconnect, power, on-chip network, wires |
95 | Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar |
A methodology for design, modeling, and analysis of networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1778-1781, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
86 | Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah |
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 45-54, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
78 | Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Designing application-specific networks on chips with floorplan information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 355-362, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
networks on chips, topology, floorplan, deadlock-free routing |
73 | Mike Brugge, Mohammed A. S. Khalid |
Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 292, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, architecture, system-on-chip, network-on-chip, design space exploration, router |
73 | Thuan Le, Mohammed Khalid |
NoC prototyping on FPGAs: A case study using an image processing benchmark. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 441-445, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
73 | Lazaros Papadopoulos, Dimitrios Soudris |
System-Level Application-Specific NoC Design for Network and Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 1-9, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
72 | Jia Li 0022, Qiang Xu 0001, Yu Hu 0001, Xiaowei Li 0001 |
Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 26-31, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC channel utilization, test wrapper, interleaved test scheduling |
64 | Julien Delorme |
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 31-42, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
64 | Shan Tang, Qiang Xu 0001 |
A multi-core debug platform for NoC-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 870-875, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
63 | Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux |
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 129-132, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch |
63 | Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina |
xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 141-148, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques |
61 | Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Mazin S. Yousif, Chita R. Das |
Performance and power optimization through data compression in Network-on-Chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 215-225, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
61 | Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 869-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li 0018, Li-Shiuan Peh |
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 855-868, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Xin Wang, Tapani Ahonen, Jari Nurmi |
Applying CDMA Technique to Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1091-1100, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Prabhat Avasare, Vincent Nollet, Jean-Yves Mignolet, Diederik Verkest, Henk Corporaal |
Centralized end-to-end flow control in a best-effort network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 17-20, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
run-time communication management, network-on-chip |
61 | Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani |
A Network on Chip Architecture and Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 117-124, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
System on Chip, IP, Platform based design, On-chip communication |
59 | Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest |
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 139-153, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC) |
59 | Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach |
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 149-158, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous |
58 | Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano |
3-D NoC on Inductive Wireless Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 225-248, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
58 | Vasilis F. Pavlidis, Eby G. Friedman |
Physical Analysis of NoC Topologies for 3-D Integrated Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 89-114, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
55 | Jeremy Chan, Sri Parameswaran |
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 265-270, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park |
A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 607-610, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Chang Wu, Yubai Li, Song Chai, Zhongming Yang |
Lottery Router: A Customized Arbitral Priority NOC Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 411-414, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne |
On the Potential of NoC Virtualization for Multicore Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISIS ![In: Second International Conference on Complex, Intelligent and Software Intensive Systems (CISIS-2008), March 4th-7th, 2008, Technical University of Catalonia, Barcelona, Spain, pp. 801-807, 2008, IEEE Computer Society, 978-0-7695-3109-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit |
Fast, Accurate and Detailed NoC Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 323-332, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Théodore Marescaux, Erik Brockmeyer, Henk Corporaal |
The Impact of Higher Communication Layers on NoC Supported MP-SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 107-116, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris |
Application - specific NoC platform design based on System Level Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 311-316, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Graham Schelle, Jeff Fifield, Dirk Grunwald |
A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 177-182, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Balasubramanian Sethuraman, Ranga Vemuri |
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 419-426, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Érika F. Cota, Chunsheng Liu |
Constraint-Driven Test Scheduling for NoC-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2465-2478, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
55 | Edith Beigné, Pascal Vivet |
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 172-183, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
55 | Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli |
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(2), pp. 113-129, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
architecture, Systems-on-chip, mapping, networks on chip, synthesis |
55 | Wooyoung Jang, David Z. Pan |
Application-aware NoC design for efficient SDRAM access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 453-456, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
QoS, memory, flow control, router, NoC, on-chip communication |
54 | Pavel Ghosh, Arunabha Sen |
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 535-541, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding |
52 | Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri |
Modeling networking issues of network-on-chip: a coloured petri nets approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SimuTools ![In: Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2009, Rome, Italy, March 2-6, 2009, pp. 22, 2009, ICST/ACM, 978-963-9799-45-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modeling, network-on-chip, coloured petri nets |
52 | Vasilis F. Pavlidis, Eby G. Friedman |
3-D Topologies for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1081-1090, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Martin Schoeberl |
A Time-Triggered Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 377-382, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal |
Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 227-232, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Linear-programming-based techniques for synthesis of network-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 407-420, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli |
Mapping and configuration methods for multi-use-case networks on chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 146-151, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
guaranteed throughput, multiple application platforms, systems on chips, networks on chips, reconfiguration, dynamic, use-cases, voltage scaling, frequency scaling, best effort |
52 | Mário P. Véstias, Horácio C. Neto |
Area and performance optimization of a generic network-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 68-73, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, system-on-chip, network-on-chip |
52 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 1025-1040, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
52 | Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen |
An event-based monitoring service for networks on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 702-723, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
monitoring, debugging, Networks-on-Chip |
52 | Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha |
A Power and Performance Model for Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1250-1255, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde |
Operating-system controlled network on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 256-259, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
operating system, network on chip, MP-SoC |
52 | Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen |
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 143-148, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
application-specific designs, low-power, NOC, SOC |
51 | Shouyi Yin, Leibo Liu, Shaojun Wei |
Buffer planning for application-specific networks-on-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(4), pp. 547-558, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
buffer planning, optimization, design automation, networks-on-chip (NoC) |
51 | Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra |
Low power nanoscale buffer management for network on chip routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 245-250, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nanoscale technology noc, soc, noc, router, dynamic power management |
47 | Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson |
Challenges and Promising Results in NoC Prototyping Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(5), pp. 86-95, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGAs, interconnection network, network on chip, computer systems organization, computer system implementation |
47 | Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi |
Using the inter- and intra-switch regularity in NoC switch testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 361-366, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Ewerson Carvalho, Ney Calazans, Fernando Moraes 0001 |
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 34-40, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Mehdi Modarressi, Hamid Sarbazi-Azad |
Power-aware mapping for reconfigurable NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 417-422, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi |
An Analytical Model for Reliability Evaluation of NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 49-56, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua |
An Analytical Performance Model for the Spidergon NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), May 21-23, 2007, Niagara Falls, Canada, pp. 1014-1021, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa |
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 144-151, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu |
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 689-695, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
crosstalk avoidance codes, interconnect energy, networks on chip, crosstalk, wormhole switching |
47 | Rickard Holsmark, Maurizio Palesi, Shashi Kumar |
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 696-703, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Application Specific Routing, Networks on Chip, Routing Algorithms, Deadlock, Wormhole Switching |
47 | Krishnan Srinivasan, Karam S. Chatha |
Layout aware design of mesh based NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 136-141, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, automated design, mesh topology |
47 | Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten |
NoC monitoring: impact on the design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Catherine H. Gebotys, Robert J. Gebotys |
A Framework for Security on NoC Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 113-120, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara |
Dynamic thread and data mapping for NoC based CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 852-857, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mapping, dynamic, CMP, thread, NoC, data |
47 | Itamar Cohen, Ori Rottenstreich, Isaac Keslassy |
Statistical Approach to NoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 171-180, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
T-Plot, NoC, statistical approach, capacity allocation, traffic matrices |
47 | Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan |
A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 182-184, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
manycore chips, submesh allocation, algorithm, noc, temperature |
47 | Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva |
Cache coherency communication cost in a NoC-based MPSoC platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 288-293, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache coherence, MPSoC, NoC, directory |
47 | Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner |
A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 282-287, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
energy, MPSoC, NoC, task migration, memory organization |
47 | Samuel Evain, Jean-Philippe Diguet |
Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 457-460, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
guarantied traffic, path allocation, NOC, CAD tool |
46 | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
A new physical routing approach for robust bundled signaling on NoC links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 3-8, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing |
46 | Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano |
A data protection unit for NoC-based architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 167-172, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiprocessor system-on-chip (MPSoC), security, embedded systems, data protection, network-on-chip (NoC) |
45 | Ahmed Al-Maashri, Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Narayanan Vijaykrishnan |
Influence of Stacked 3D Memory/Cache Architectures on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 249-271, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Abbas Sheibanyrad, Frédéric Pétrot |
Asynchronous 3D-NoCs Making Use of Serialized Vertical Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 149-165, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Axel Jantsch, Matthew Grange, Dinesh Pamunuwa |
The Promises and Limitations of 3-D Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 27-44, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 193-223, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Shan Yan, Bill Lin 0001 |
Design of Application-Specific 3D Networks-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 167-191, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Brett Stanley Feero, Partha Pratim Pande |
Three-Dimensional Networks-on-Chip: Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 115-145, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Erik Jan Marinissen |
Testing 3D Stacked ICs Containing Through-Silicon Vias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 47-74, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Chuan Seng Tan |
Three-Dimensional Integration of Integrated Circuits - an Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 3-26, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
45 | Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson |
Design and Computer Aided Design of 3DIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3D Integration for NoC-based SoC Architectures ![In: 3D Integration for NoC-based SoC Architectures, pp. 75-88, 2011, Springer, 978-1-4419-7617-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
43 | Vincenzo Rana, Donatella Sciuto |
A novel design framework for the design of reconfigurable systems based on NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 1-2, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
network-on-chip, reconfigurable computing, design flow, mapping algorithm |
43 | Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng |
NTPT: on the end-to-end traffic prediction in the on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 449-452, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
end-to-end traffic prediction, network-on-chip, many-core |
43 | Brett Feero, Partha Pratim Pande |
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(1), pp. 32-45, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Shirish Bahirat, Sudeep Pasricha |
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 129-136, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic interconnect, network-on-chip, chip multiprocessor |
43 | Faizal Arya Samman, Thomas Hollstein, Manfred Glesner |
Flexible parallel pipeline network-on-chip based on dynamic packet identity management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi |
Quarc: A Novel Network-On-Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 705-712, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Shan Yan, Bill Lin 0001 |
Design of application-specific 3D Networks-on-Chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 142-149, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni |
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 31-40, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics |
43 | Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek |
Transaction-Based Communication-Centric Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 95-106, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 184-190, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud |
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 873-878, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 158-163, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis |
Networks on chips for high-end consumer-electronics TV system architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 148-153, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Calin Ciordas, Andreas Hansson 0001, Kees Goossens, Twan Basten |
A Monitoring-Aware Network-on-Chip Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 97-106, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Heikki Kariniemi, Jari Nurmi |
On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Krishnan Srinivasan, Karam S. Chatha |
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 352-357, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Luciano Ost, Aline Mello 0001, José Palma 0002, Fernando Gehm Moraes, Ney Calazans |
MAIA: a framework for networks on chip generation and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 49-52, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Stefano Santi, Bill Lin 0001, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti |
On the impact of traffic statistics on quality of service for networks on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2349-2352, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
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