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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3849 occurrences of 1991 keywords
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Results
Found 9295 publication records. Showing 9295 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Zhenpei Li, Ping Li, Ming Wu |
Digital oil and gas pipeline visualization using X3D. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web3D ![In: Proceeding of the 14th International Conference on 3D Web Technology, Web3D 2009, Darmstadt, Germany, June 16-17, 2009, pp. 191-196, 2009, ACM, 978-1-60558-432-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Java native interface (JNI), OLE for process control (OPC), digital oil and gas pipeline, scene access interface (SAI), visualization, interaction, 3D modeling, extensible 3D (X3D) |
85 | Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even |
Pipelined Packet-Forwarding Floating Point: II. An Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 148-155, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic |
81 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 1-8, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
73 | Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou |
A Low-Power Processor Architecture Optimized forWireless Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 185-190, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits |
69 | Zeshan Chishti, T. N. Vijaykumar |
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(1), pp. 69-81, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Power Management, Performance of Systems, Multithreaded processors |
69 | Hans M. Jacobson |
Improved clock-gating through transparent pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 26-31, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating |
68 | Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu |
ARAS: asynchronous RISC architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 210-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing |
60 | Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis |
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 173-, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller 0001 |
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 350-361, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Allan Hartstein, Thomas R. Puzak |
The Optimum Pipeline Depth for a Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 7-13, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
58 | Mark S. Squillante, David R. Kaeli, Himanshu Sinh |
Analytic Models of Workload Behavior and Pipeline Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 1997, Proceedings of the Fifth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, January 12-15, 1997 Haifa, Israel, pp. 91-, 1997, IEEE Computer Society, 0-8186-7758-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
58 | Svetlana P. Kartashev, Steven I. Kartashev |
Adaptable pipeline system with dynamic architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1981 National Computer Conference, 4-7 May 1981, Chicago, Illinois, USA, pp. 111-124, 1981, AFIPS Press, 978-1-4503-7921-2. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
57 | Arthur Abnous, Nader Bagherzadeh |
Pipelining and Bypassing in a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(6), pp. 658-664, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing |
56 | Ing-Jer Huang |
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(1), pp. 93-121, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis |
56 | Viswanathan Subramanian, Arun K. Somani |
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 9-16, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Sailesh Kumar, Michela Becchi, Patrick Crowley, Jonathan S. Turner |
CAMP: fast and efficient IP lookup architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006, pp. 51-60, 2006, ACM, 1-59593-580-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IP lookup, longest prefix match, internet router |
55 | Seongwoo Kim, Arun K. Somani |
SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 17-19 December 2001, Seoul, Korea, pp. 27-34, 2001, IEEE Computer Society, 0-7695-1414-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
53 | Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer |
Reliability Modeling and Assurance of Clockless Wave Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 442-450, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Ayman M. El-Khashab, Earl E. Swartzlander Jr. |
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 378-388, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Sang Ok Koo, Hyuk Don Kwon, Chang Geol Yoon, Won Seok Seo, Soon Ki Jung |
Visualization for a Multi-Sensor Data Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGIV ![In: Third International Conference on Computer Graphics, Imaging and Visualization (CGIV 2006), 26-28 July 2006, Sydney, Australia, pp. 57-63, 2006, IEEE Computer Society, 0-7695-2606-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Prabhat Mishra 0001, Nikil D. Dutt |
Modeling and validation of pipeline specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(1), pp. 114-139, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language |
49 | Masayuki Tsukisaka, Takashi Nanya |
A testable design for asynchronous fine-grain pipeline circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 148-155, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design |
48 | Shijing Wu, Qunli Li, Enyong Zhu, Jinjuan She, Ming Qin |
A Hybrid Intelligent System for Pipeline Robot Navigation in Unknown Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIRA (1) ![In: Intelligent Robotics and Applications, First International Conference, ICIRA 2008, Wuhan, China, October 15-17, 2008 Proceedings, Part I, pp. 189-198, 2008, Springer, 978-3-540-88512-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pipeline robot, neural network, navigation, fuzzy controller |
48 | John Biddiscombe, Berk Geveci, Ken Martin, Kenneth Moreland, David C. Thompson 0001 |
Time Dependent Processing in a Parallel Pipeline Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 13(6), pp. 1376-1383, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
data-parallel visualization pipeline, time-varying data |
48 | Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas |
ReCycle: : pipeline adaptation to tolerate process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 323-334, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pipeline, process variation, clock skew |
48 | Allan Hartstein, Thomas R. Puzak |
The optimum pipeline depth considering both power and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(4), pp. 369-388, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Pipeline Depth, Power and Performance, Workload Specificity, Simulation |
48 | Kerstin Eder, Geoff Barrett |
Achieving maximum performance: a method for the verification of interlocked pipeline control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 135-140, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interlock logic, pipeline stall, verification |
47 | Shinichi Yamagiwa, Leonel Sousa |
Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Sudsanguan Ngamsuriyaroj, Ekasit Kijsipongse |
Optimal Placement of Pipeline Applications on Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 245-252, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Wook-Shin Han, Soon Ki Jung, Jeyong Shin, Jinsoo Lee, Mina Yoon, Chang Geol Yoon, Won Seok Seo, Sang Ok Koo |
A Scalable Pipeline Data Processing Framework Using Database and Visualization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues, Third International Conference on Intelligent Computing, ICIC 2007, Qingdao, China, August 21-24, 2007, Proceedings, pp. 334-344, 2007, Springer, 978-3-540-74170-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Scalable processing, Intelligent PIGs, Time series data |
47 | Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh |
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 105-119, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Pipeline-Level Control of Self-Resetting Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 342-349, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy 0001 |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 926-931, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Self-resetting stage logic pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 174-177, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clockless, self-resetting, pipeline, asynchronous |
45 | Wei-keng Liao, Alok N. Choudhary, Donald D. Weiner, Pramod K. Varshney |
Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 655-662, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
space-time adaptive processing, parallel processing, parallel I/O, parallel file system, parallel pipeline |
44 | Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge |
Cache implications of aggressively pipelined high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 123-132, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov |
Designing an asynchronous pipeline token ring interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 32-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks |
43 | Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha |
Improving self-timed pipeline ring performance through the addition of buffer loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 218-223, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing |
42 | Amy S. Bruckman, Maureen Biggers, Barbara Ericson, Tom McKlin, Jill P. Dimond, Betsy James DiSalvo, Mike Hewner, Lijun Ni, Sarita Yardi |
"Georgia computes!": improving the computing education pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 40th SIGCSE Technical Symposium on Computer Science Education, SIGCSE 2009, Chattanooga, TN, USA, March 4-7, 2009, pp. 86-90, 2009, ACM, 978-1-60558-183-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computing education pipeline, summer camps, introductory courses |
42 | Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval |
Load balancing using work-stealing for pipeline parallelism in emerging applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 517-518, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
work-stealing, load imbalance, parallel pipeline |
42 | Wu Liu, Min Li, Yi Liu, Yuan Xu, Xinglan Yang |
Decision of optimal scheduling scheme for gas field pipeline network based on hybrid genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GEC Summit ![In: Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation, GEC Summit 2009, Shanghai, China, June 12-14, 2009, pp. 369-374, 2009, ACM, 978-1-60558-326-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
natural gas pipeline network, genetic algorithm, optimization, scheduling scheme, differential evolution algorithm |
42 | Nary Subramanian |
Improving Security of Oil Pipeline SCADA Systems Using Service-Oriented Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OTM Workshops ![In: On the Move to Meaningful Internet Systems: OTM 2008 Workshops, OTM Confederated International Workshops and Posters, ADI, AWeSoMe, COMBEK, EI2N, IWSSA, MONET, OnToContent + QSI, ORM, PerSys, RDDS, SEMELS, and SWWS 2008, Monterrey, Mexico, November 9-14, 2008. Proceedings, pp. 344-353, 2008, Springer, 978-3-540-88874-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
petroleum, security, architecture, pipeline, services, SCADA |
42 | Che-Wei Lin, Jeen-Shing Wang, Chun-Chang Yu, Ting-Yu Chen |
Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (2) ![In: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence, Third International Conference on Intelligent Computing, ICIC 2007, Qingdao, China, August 21-24, 2007, Proceedings, pp. 164-173, 2007, Springer, 978-3-540-74201-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Synchronous pipeline design, neuro-fuzzy circuit, FPGA |
42 | Arnab Roy 0001, Subrat Kumar Panda, Rajeev Kumar 0004, P. P. Chakrabarti 0001 |
A framework for systematic validation and debugging of pipeline simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(3), pp. 462-491, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Simulation-based verification, dataflow equivalence, pipeline validation, design space exploration, instruction scheduling, pipelined architectures |
42 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 12-17, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
42 | Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault tolerant clockless wave pipeline design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 350-356, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability |
42 | Jia Di, Jiann-Shiun Yuan |
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 64-67, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
2-D pipeline gating, power-awareness, array multiplier |
42 | Weirong Jiang, Qingbo Wang, Viktor K. Prasanna |
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 1786-1794, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 194-199, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A mesochronous pipeline scheme for high performance low power digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Bing-Fei Wu, Chung-Fu Lin |
A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 15(12), pp. 1615-1628, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Steve MacDonald, Duane Szafron, Jonathan Schaeffer |
Rethinking the Pipeline as Object-Oriented States with Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIPS ![In: 9th International Workshop on High-Level Programming Models and Supportive Environments (HIPS 2004), 26 April 2004, Santa Fe, NM, USA, pp. 12-21, 2004, IEEE Computer Society, 0-7695-2151-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge |
Reducing pipeline energy demands with local DVS and dynamic retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 319-324, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic retiming with global DVS, local DVS, razor |
42 | Chris Y. Chung, Ravi Managuli, Yongmin Kim 0001 |
Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 243-252, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Michael Golden, Trevor N. Mudge |
A comparison of two pipeline organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 153-161, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
pipelines, cache memory, RISC, memory system, interlocks |
40 | Sreeram Duvvuru, Siamak Arya |
Evaluation of a branch target address cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 173-180, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes |
40 | Shinichi Yamagiwa, Leonel Sousa, Tomás Brandão |
Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 6th International Symposium on Parallel and Distributed Computing (ISPDC 2007), Hagenberg, Austria, July 5-8, 2007, pp. 17-24, 2007, IEEE Computer Society, 0-7695-2936-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Kenneth Eguro, Scott Hauck |
Armada: timing-driven pipeline-aware routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 169-178, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipeline FPGA, pipeline routing, reconfigurable computing |
38 | Prathima Agrawal, Antony Ng |
Computing Network Flow on a Multiple Processor Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(6), pp. 653-658, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multiple processor pipeline, Goldberg-Tarjan algorithm, network graph, six processors, distributed algorithms, graph theory, network flow, pipeline processing, parallel implementations, performance estimates, maximum flow, partitioned algorithm, message-passing multicomputer |
37 | Kuan-Wei Cheng, Tzong-Yen Lin, Rong-Guey Chang |
Profile-based dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 48(2), pp. 210-226, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
DPS, Pipeline mode, Loop region, DVS, IPC |
37 | Allan MacKenzie-Graham, Arash Payan, Ivo D. Dinov, John D. Van Horn, Arthur W. Toga |
Neuroimaging Data Provenance Using the LONI Pipeline Workflow Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPAW ![In: Provenance and Annotation of Data and Processes, Second International Provenance and Annotation Workshop, IPAW 2008, Salt Lake City, UT, USA, June 17-18, 2008. Revised Selected Papers, pp. 208-220, 2008, Springer, 978-3-540-89964-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Grid, Workflow, Pipeline, Provenance, Neuroimaging |
37 | Ding Feng 0001, Chaobin Huang, Kui Zhou, Peng Wang, Jin Liu, Shouyong Li |
Crucial Technology Research on Pipeline Jet Cleaning Robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIRA (2) ![In: Intelligent Robotics and Applications, First International Conference, ICIRA 2008, Wuhan, China, October 15-17, 2008 Proceedings, Part II, pp. 1137-1144, 2008, Springer, 978-3-540-88516-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
crucial technology, robot, pipeline, cleaning |
37 | Mahmoud Lotfi Anhar, Mohammad Ali Jabraeil Jamali |
The Optimum Location of Delay Latches Between Dynamic Pipeline Stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 14-17, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Minimum, MAL, Pipeline, Latency, Collision, Table, Reservation, Latch, Average |
37 | Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho |
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 39-48, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive pipeline, processor, Asynchronous design |
37 | Jian Ruan, Zhiying Wang 0003, Kui Dai, Yong Li 0006 |
Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV, pp. 251-258, 2007, Springer, 978-3-540-72589-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Asynchronous Pipeline, Timed Event Graph, Evolution Equation, Latency Estimation, Max-Plus Algebra |
37 | Stavros Souravlas, Manos Roumeliotis |
A Pipeline Technique for Dynamic Data Transfer on a Multiprocessor Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 32(5), pp. 361-388, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Block-cyclic redistribution, processor classes, pipeline tasks, High Performance Fortran |
37 | Nianmin Yao, Ming-Yang Zheng, Jiu-bin Ju |
Pipeline: a new architecture of high performance servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 36(4), pp. 55-64, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
architecture, web, pipeline, high performance, server |
37 | Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller |
Advances of the Counterflow Pipeline Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 230-236, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
counterflow, CFPP, virtual register, architecture, pipeline, dataflow, VRP |
37 | Val Donaldson, Jeanne Ferrante |
Determining Asynchronous Acyclic Pipeline Execution Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 568-572, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling |
36 | Peng Zhou, JiangHe Yao, JiuLing Pei |
Implementation of an energy-efficient scheduling scheme based on pipeline flux leak monitoring networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(9), pp. 1632-1639, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic modulation scaling, reclaiming scheme, sensor networks, real-time scheduling, EDF |
36 | Rama Sangireddy, Jatan P. Shah |
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(4), pp. 529-544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Mohammad Ghasemazar, Massoud Pedram |
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 155-160, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Huaqing Mao, Fuling Bian |
Research on Constructing 3-D Pipeline Connection Model By Using OpenGL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (2) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 2: Software Engineering, December 12-14, 2008, Wuhan, China, pp. 1008-1011, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Zhongli Ma, Hongda Liu |
Pipeline defect detection and sizing based on MFL data using immune RBF neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 3399-3403, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Jinhai Liu, Huaguang Zhang, Jian Feng 0001, Heng Yue |
A New Fault Detection and Diagnosis Method for Oil Pipeline Based on Rough Set and Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2007, 4th International Symposium on Neural Networks, ISNN 2007, Nanjing, China, June 3-7, 2007, Proceedings, Part III, pp. 561-569, 2007, Springer, 978-3-540-72394-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Pingli Huang, Yun Chiu |
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1241-1244, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Abdel Ejnioui, Abdelhalim Alsharqawi |
Pipeline Design Based on Self-Resetting Stage Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 254-257, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu |
Static statistical timing analysis for latch-based pipeline designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 468-472, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Allan Hartstein, Thomas R. Puzak |
Optimum Power/Performance Pipeline Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 117-128, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Brian A. Wandell |
Color Appearance and the Digital Imaging Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR ![In: 15th International Conference on Pattern Recognition, ICPR'00, Barcelona, Spain, September 3-8, 2000., pp. 1183-1190, 2000, IEEE Computer Society, 0-7695-0750-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon |
Bounding Pipeline and Instruction Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(1), pp. 53-70, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache |
35 | Kai Hwang 0001, Zhiwei Xu |
Multipipeline Networking for Compound Vector Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(1), pp. 33-47, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
compound vector processing, multipipeline networking, pipeline chaining, pipeline nets, run-time techniques, Livermore loops, performance evaluation, performance analysis, parallel programming, compilation, parallel architectures, programming, program compilers, pipeline processing, scientific programs, vector-processing, systolization |
34 | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 |
A mechanistic performance model for superscalar out-of-order processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 27(2), pp. 3:1-3:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling |
34 | David W. Matula, Asger Munk Nielsen |
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 140-147, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations |
34 | Zbigniew M. Wójcik, Barbara E. Wójcik |
Rough Grammar For Efficient and Fault-Tolerant Computing on a Distributed System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(7), pp. 652-668, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
global load balancing, dynamic task scheduling, multiprocessor machine, rough grammar, rough grammar production rules, pipeline fashion, statically scheduled multiprocessor, decentralized methodology, scheduling, fault tolerance, parallel processing, distributed computation, fault-tolerant computing, fault tolerant computing, concurrent program, grammars, pipeline processing |
34 | Weirong Jiang, Viktor K. Prasanna |
Multi-terabit ip lookup using parallel bidirectional pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 241-250, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ip lookup, terabit, pipeline, sram, bidirectional |
34 | Reuven Bar-Yehuda, Craig Gotsman |
Time/Space Tradeoffs for Polygon Mesh Rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 15(2), pp. 141-152, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
rendering, polygons, graphics pipeline |
33 | Praveen Jayachandran, Tarek F. Abdelzaher |
Delay composition in preemptive and non-preemptive real-time pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 40(3), pp. 290-320, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pipelined distributed systems, Delay composition, Schedulability, End-to-end delay |
33 | Montek Singh, Steven M. Nowick |
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(6), pp. 684-698, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Praveen Jayachandran, Tarek F. Abdelzaher |
A Delay Composition Theorem for Real-Time Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 19th Euromicro Conference on Real-Time Systems, ECRTS'07, 4-6 July 2007, Pisa, Italy, Proceedings, pp. 29-38, 2007, IEEE Computer Society, 978-0-7695-2914-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai |
Perceptron-Based Branch Confidence Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 265-275, 2004, IEEE Computer Society, 0-7695-2053-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Christopher W. Milner, Jack W. Davidson |
Quick piping: a fast, high-level model for describing processor pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 175-184, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded systems, pipelines, modeling of computer architecture |
33 | Oswaldo Cadenas, Graham M. Megson |
Pipelining Considerations for an FPGA Case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 276-285, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Daniel Pak-Kong Lun, Wan-Chi Siu |
A Pipeline Design for the Realization of the Prime Factor Algorithm Using the Extended Diagonal Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(10), pp. 1232-1237, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
pipeline design, prime factor algorithm, input data sequenc, data loading, parallel algorithms, parallel architectures, signal processing, digital signal processing, retrieval, Chinese Remainder Theorem, pipeline architecture, multidimensional array |
32 | Veljko M. Milutinovic, David A. Fura, Walter A. Helbig |
Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(11), pp. 1214-1224, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide |
32 | Richard G. Cooper |
The Distributed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(11), pp. 1123-1132, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer |
31 | Sherif Ghali |
Sense and sidedness in the graphics pipeline via a passage through a separable space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 25(4), pp. 367-375, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Oriented projective geometry, Separability, Projective geometry, Homogeneous coordinates, Graphics pipeline |
31 | Jarkko Ylipaavalniemi, Jyri Soppela |
Arabica: Robust ICA in a Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA ![In: Independent Component Analysis and Signal Separation, 8th International Conference, ICA 2009, Paraty, Brazil, March 15-18, 2009. Proceedings, pp. 379-386, 2009, Springer, 978-3-642-00598-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
pipeline, ICA, bootstrapping, fMRI, Toolbox |
31 | Álvaro García-Sánchez, Luis Miguel Arreche Bedia, Miguel Ortega-Mier |
Combining Simulation and Tabu Search for Oil-derivatives Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Metaheuristics for Scheduling in Industrial and Manufacturing Applications ![In: Metaheuristics for Scheduling in Industrial and Manufacturing Applications, pp. 301-325, 2008, Springer, 978-3-540-78984-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multi-commodity Pipeline, Real World Instances, Simulation, Scheduling, Tabu Search |
31 | John Giacomoni, Tipp Moseley, Manish Vachharajani |
FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2008, Salt Lake City, UT, USA, February 20-23, 2008, pp. 43-52, 2008, ACM, 978-1-59593-795-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fastforward, multiprocessors, multicore, queue, lock-free, linearizability, nonblocking synchronization, pipeline parallel |
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