Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
104 | Andrew B. Kahng, Qinke Wang |
Implementation and extensibility of an analytic placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5), pp. 734-747, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
90 | Andrew B. Kahng, Qinke Wang |
Implementation and extensibility of an analytic placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 18-25, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
I/O-Core co-placement, hierarchical placement, congestion, geometric constraints, analytical placement |
81 | David A. Papa, Saurabh N. Adya, Igor L. Markov |
Constructive benchmarking for placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 113-118, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
placer, performance, evaluation, benchmark, comparison |
79 | Andrew B. Kahng, Sherief Reda |
Evaluation of placer suboptimality via zero-change netlist transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 208-215, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, wirelength |
66 | Peter Spindler, Frank M. Johannes |
Fast and accurate routing demand estimation for efficient routability-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1226-1231, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Saurabh N. Adya, Igor L. Markov |
Combinatorial techniques for mixed-size placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 58-90, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, placement, floorplanning |
55 | Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten |
Performance driven standard-cell placement using the genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 124-127, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement |
53 | Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar |
A network-flow approach to timing-driven incremental placement for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 375-382, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Peter Spindler, Frank M. Johannes |
Fast and robust quadratic placement combined with an exact linear net model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 179-186, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Dilvan de Abreu Moreira, Les T. Walczowski |
AGENTS a distributed client-server system for leaf cell generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(1), pp. 42-61, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
genetic algorithms, software agents, client/server model |
51 | Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli |
Engineering details of a stable force-directed placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 573-580, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang 0012 |
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.08682, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
49 | Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang 0012 |
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021, pp. 1-9, 2021, IEEE, 978-1-6654-4507-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
49 | Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat |
Eh?Placer: A High-Performance Modern Technology-Driven Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(3), pp. 37:1-37:27, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
40 | Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu |
Towards scalable placement for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 147-156, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, convex optimization, quadratic placement, bipartite matching |
40 | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu |
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1621-1634, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu |
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 447-452, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Andrew B. Kahng, Sherief Reda |
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2806-2819, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Multilevel fixed-point-addition-based VLSI placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8), pp. 1188-1203, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim |
Placement for configurable dataflow architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1127-1130, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Fine granularity clustering-based placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 527-536, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich |
Task scheduling for heterogeneous reconfigurable computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 22-27, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration |
40 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Multilevel expansion-based VLSI placement with blockages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 558-564, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Pak K. Chan, Martine D. F. Schlag |
Parallel placement for field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 43-50, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
parallel placement, FPGAs, timing-driven placement, analytical placement |
40 | Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska |
Wire length prediction in constraint driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 99-105, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
wire length prediction, clustering |
40 | Bill Halpin, Naresh Sehgal, C. Y. Roger Chen |
Detailed Placement with Net Length Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 22-27, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
Routability driven white space allocation for fixed-die standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 42-47, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
placement, physical design, routability |
39 | Pedro Soto-Acosta, Emilio Placer-Maruri, Daniel Perez González |
A case analysis of a product lifecycle information management framework for SMEs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Manag. ![In: Int. J. Inf. Manag. 36(2), pp. 240-244, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Mitja Placer, Stanislav Kovacic |
Enhancing Indoor Inertial Pedestrian Navigation Using a Shoe-Worn Marker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 13(8), pp. 9836-9859, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
39 | Cástor Mariño, Manuel G. Penedo, Simón Pena Placer, F. González |
Crest Line and Correlation Filter Based Location of the Macula in Digital Retinal Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIOSIGNALS (2) ![In: Proceedings of the First International Conference on Biomedical Electronics and Devices, BIOSIGNALS 2008, Funchal, Madeira, Portugal, January 28-31, 2008, Volume 2, pp. 521-527, 2008, INSTICC - Institute for Systems and Technologies of Information, Control and Communication. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
39 | John Placer, Assim Sagahyroon |
Design and Implementation of a VSL System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intell. Autom. Soft Comput. ![In: Intell. Autom. Soft Comput. 13(2), pp. 197-210, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | John Placer, C. N. Slobodchikoff |
Developing New Metrics for the Investigation of Animal Vocalizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intell. Autom. Soft Comput. ![In: Intell. Autom. Soft Comput. 7(4), pp. 249-258, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Jordi Atserias Batalla, Josep Carmona Vargas, Irene Castellón Masalles, Sergi Cervell, Montserrat Civit Torruella, Lluís Màrquez, Maria Antònia Martí Antonín, Lluís Padró Cirera, Roberto Placer, Horacio Rodríguez Hontoria, Mariona Taulé Delor, Jordi Turmo |
Morphosyntactic analysis and parsing of unrestricted Spanish text. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LREC ![In: Proceedings of the First International Conference on Language Resources and Evaluation, LREC 1998, May 28-30, 1998, Granada, Spain, pp. 1267-1272, 1998, European Language Resources Association. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
39 | Josep Carmona Vargas, Sergi Cervell, Lluís Màrquez, Maria Antònia Martí, Lluís Padró Cirera, Roberto Placer, Horacio Rodríguez, Mariona Taulé Delor, Jordi Turmo |
An environment for mophosyntactic processing of unrestricted Spanish text. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LREC ![In: Proceedings of the First International Conference on Language Resources and Evaluation, LREC 1998, May 28-30, 1998, Granada, Spain, pp. 915-922, 1998, European Language Resources Association. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
39 | John Placer |
The Promise of Multiparadigm Languages as Pedagogical Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the ACM 21th Conference on Computer Science, CSC '93, Indianapolis, IN, USA, February 16-18, 1993, pp. 81-86, 1993, ACM, 0-89791-558-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
39 | John Placer |
Integrating destructive assignment and lazy evaluation in the multiparadigm language G-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 27(2), pp. 65-74, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
39 | John Placer |
Multiparadigm research: a new direction of language design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 26(3), pp. 9-17, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
39 | John Placer |
The Multiparadigm Language G. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Lang. ![In: Comput. Lang. 16(3/4), pp. 235-258, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
37 | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1228-1240, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 195-200, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
NTUplace2: a hybrid placer using partitioning and analytical techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 215-217, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placement, physical design, legalization |
37 | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 187-192, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Andrew B. Kahng, Qinke Wang |
An analytic placer for mixed-size placement and timing-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 565-572, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin |
An Adaptive Interconnect-Length Driven Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 393-398, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |
A Timing-Driven Block Placer Based on Sequence Pair Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 249-252, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
timing-driven, building block placement, sequence pair, simulated annealing algorithm |
28 | Andrew B. Kahng, Sherief Reda |
A tale of two nets: studies of wirelength progression in physical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 17-24, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, consistency, similarity, wirelength |
28 | Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden |
Benchmarking for large-scale placement and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 95-103, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength |
26 | Zigang Xiao, Evangeline F. Y. Young |
Droplet-routing-aware module placement for cross-referencing biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 193-199, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cross-referencing, dmfb, synthesis, placement, microfluidics, biochip |
26 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu |
ITOP: integrating timing optimization within placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 83-90, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
placement, timing optimization, physical synthesis |
26 | Jason Cong, Guojie Luo |
A multilevel analytical placement for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 361-366, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Hangpei Tian, Deyuan Gao, Wu Wei, Xiaoya Fan, Yian Zhu |
Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 263-264, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Guiding global placement with wire density. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 212-217, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang |
Constraint graph-based macro placement for modern mixed-size circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 218-223, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden |
Routability-Driven Placement and White Space Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 858-871, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001 |
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 67-72, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Andrew A. Kennings, Kristofer Vorwerk |
Force-Directed Methods for Generic Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2076-2087, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Andrew B. Kahng, Qinke Wang |
A faster implementation of APlace. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 218-220, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
lens aberration, supply voltage degradation, scalability, analytical placement |
26 | Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004 |
mPL6: enhanced multilevel mixed-size placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 212-214, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
mixed-size placement, legalization, Helmholtz equation, force-directed placement, multilevel optimization |
26 | Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov |
Early research experience with OpenAccess gear: an open source development environment for physical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 94-100, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
database, timing, open source, placement, physical design, EDA |
26 | Qinghua Liu, Malgorzata Marek-Sadowska |
A congestion-driven placement framework with local congestion prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 488-493, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cell padding, congestion prediction, placement migration |
26 | Andrew B. Kahng, Igor L. Markov, Sherief Reda |
Boosting: Min-Cut Placement with Improved Signal Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1098-1103, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Satrajit Chatterjee, Robert K. Brayton |
A new incremental placement algorithm and its application to congestion-aware divisor extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 541-548, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Bo Hu 0006, Malgorzata Marek-Sadowska |
Fine granularity clustering for large scale placement problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 67-74, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clustering, placement |
26 | Saurabh N. Adya, Igor L. Markov, Paul Villarrubia |
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 311-319, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 12-17, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
A Standard-Cell Placement Tool for Designs with High Row Utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 45-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna 0001 |
A Transistor Level Placement Tool for Custom Cell Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 254-257, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
simulated annealing, placement |
26 | Shigetoshi Nakatake, Yoji Kajitani |
Channel-driven global routing with consistent placement (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 350-355, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
24 | Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang |
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5), pp. 1552-1565, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Pranav Jain, Gagandeep, Sneh Saurabh |
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 55-60, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Zhili Xiong, Rachel Selina Rajarathnam, Zhixing Jiang, Hanqing Zhu, David Z. Pan |
DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.08582, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang |
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.11761, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Josef Grus, Zdenek Hanzálek, Dalibor Barri, Patrik Vacula |
Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICORES ![In: Proceedings of the 12th International Conference on Operations Research and Enterprise Systems, ICORES 2023, Lisbon, Portugal, February 19-21, 2023., pp. 106-116, 2023, SCITEPRESS, 978-989-758-627-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan |
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 300-306, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Christos Georgakidis, Stavros Simoglou, Christos P. Sotiriou |
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Karim Malik, Colin Robertson, Douglas Braun, Clara Greig |
U-Net convolutional neural network models for detecting and quantifying placer mining disturbances at watershed scales. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Appl. Earth Obs. Geoinformation ![In: Int. J. Appl. Earth Obs. Geoinformation 104, pp. 102510, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai |
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021, pp. 1-8, 2021, IEEE, 978-1-6654-4507-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Mohamed Ayman, Mahmoud Soliman |
Robust pole-placer power system stabilisers design via complex Kharitonov's theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Model. Identif. Control. ![In: Int. J. Model. Identif. Control. 34(3), pp. 197-207, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Frédéric Gessler, Philip Brisk, Mirjana Stojilovic |
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020, pp. 78-83, 2020, IEEE, 978-1-7281-5701-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu 0010, Jianli Chen |
Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Prasun Datta, Shyamapada Mukherjee |
Architecture-aware routability-driven placer for large-scale mixed-size designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(8), pp. 1209-1220, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu |
Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019, pp. 122-131, 2019, ACM, 978-1-4503-6137-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Wuxi Li, Shounak Dhar, David Z. Pan |
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4), pp. 869-882, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany |
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3), pp. 669-681, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Ziad Abuowaimer, Dani Maarouf, Timothy Martin, Jérémy Foxcroft, Gary Gréwal, Shawki Areibi, Anthony Vannelli |
GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 23(5), pp. 66:1-66:33, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Hisham M. Soliman, Ashraf Saleem, Tarek A. Tutunji, Serein Al Ratrout |
Robust digital pole-placer for electric drives based on uncertain diophantine equation and interval mathematics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Inst. Meas. Control ![In: Trans. Inst. Meas. Control 40(8), pp. 2546-2559, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Renaud De Landtsheer, Jean-Christophe Deprez, Christophe Ponsard |
Optimal mapping of task-based computation models over heterogeneous hardware using placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoDELS (Companion) ![In: Proceedings of the 21st ACM/IEEE International Conference on Model Driven Engineering Languages and Systems: Companion Proceedings, MODELS 2018, Copenhagen, Denmark, October 14-19, 2018, pp. 17-21, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Yu-Min Lee, Kuan-Te Pan, Chun Chen |
NaPer: A TSV Noise-Aware Placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(5), pp. 1703-1713, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Xu He, Yao Wang 0002, Yang Guo 0003, Sorin Cotofana |
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017, pp. 29-34, 2017, ACM, 978-1-4503-4972-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen |
An analytical placer for heterogeneous FPGAs via rough-placed packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-3969-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Wuxi Li, Shounak Dhar, David Z. Pan |
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016, pp. 66, 2016, ACM, 978-1-4503-4466-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Tao Lin 0007, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev |
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3), pp. 447-459, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Endre Csóka, Attila Deák |
A macro placer algorithm for chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1509.01867, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
24 | Yu-Min Lee, Chun Chen, JiaXing Song, Kuan-Te Pan |
A TSV noise-aware 3-D placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 1653-1658, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
24 | John Krumm, Dany Rouhana, Ming-Wei Chang |
Placer++: Semantic place labels beyond the visit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: 2015 IEEE International Conference on Pervasive Computing and Communications, PerCom 2015, St. Louis, MO, USA, 23-27 March, 2015, pp. 11-19, 2015, IEEE Computer Society, 978-1-4799-8033-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Yande Jiang, Xu He, Chang Liu 0019, Yang Guo 0003 |
An effective analytical 3D placer in monolithic 3D IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Sameer Pawanekar, Gaurav Trivedi |
Net weighing based timing driven standard cell placer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Ka-Ming Keung, Swamy D. Ponpandi, Akhilesh Tyagi |
A placer for composable FPGA with 2D mesh network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 6(4), pp. 289-302, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Xin Yu, Xuanhua Shi, Hai Jin 0001, Xiaofei Liao, Song Wu 0001, Xiaoming Li |
Page Classifier and Placer: A Scheme of Managing Hybrid Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing - 11th IFIP WG 10.3 International Conference, NPC 2014, Ilan, Taiwan, September 18-20, 2014. Proceedings, pp. 10-22, 2014, Springer, 978-3-662-44916-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Fubing Mao, Yi-Chung Chen, Wei Zhang 0012, Hai Li 0001 |
BMP: a fast B*-tree based modular placer for FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014, pp. 248, 2014, ACM, 978-1-4503-2671-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|