Search results for "pre-silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor	Bridging pre-silicon verification and post-silicon validation.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon, pre-silicon, verification, validation
70	Sandip Ray, Warren A. Hunt Jr.	Connecting pre-silicon and post-silicon verification.	FMCAD	2009	DBLP DOI BibTeX RDF
54	Jagannath Keshava, Nagib Hakim, Chinna Prudvi	Post-silicon validation challenges: how EDA and academia can help.	DAC	2010	DBLP DOI BibTeX RDF	design, verification, test, validation, emulation
52	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
44	Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak	On Silicon-Based Speed Path Identification.	VTS	2005	DBLP DOI BibTeX RDF
44	Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng	A path-based methodology for post-silicon timing validation.	ICCAD	2004	DBLP DOI BibTeX RDF
43	Pradip Bose	Pre-Silicon Modeling and Analysis: Impact On Real Design.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Pre-silicon modeling, performance modeling, CMOS
39	Robert P. Colwell, Bob Brennan	Intel's Formal Verification Experience on the Willamette Development.	TPHOLs	2000	DBLP DOI BibTeX RDF
38	Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici	Post-silicon validation opportunities, challenges and recent advances.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon validation
38	Miron Abramovici	In-System Silicon Validation and Debug.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
38	Ilya Wagner, Valeria Bertacco	Reversi: Post-silicon validation system for modern microprocessors.	ICCD	2008	DBLP DOI BibTeX RDF
36	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
34	Soohong P. Kim	Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors.	MTV	2005	DBLP DOI BibTeX RDF
34	Pradip Bose	Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation.	DSN	2001	DBLP DOI BibTeX RDF
33	Lin Xie, Azadeh Davoodi, Kewal K. Saluja	Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon diagnosis, process variations
31	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	An Approach for Pre-Silicon Power Modeling.	ICCTA	2007	DBLP DOI BibTeX RDF
30	Eli Chiprout	On-die power grids: the missing link.	DAC	2010	DBLP DOI BibTeX RDF	decap, voltage, locality, power grid, resonance
30	Mahesh Ketkar, Eli Chiprout	A microarchitecture-based framework for pre- and post-silicon power delivery analysis.	MICRO	2009	DBLP DOI BibTeX RDF
30	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Vijay Degalahal, Tim Tuan	Methodology for high level estimation of FPGA power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
27	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Post-silicon verification for cache coherence.	ICCD	2008	DBLP DOI BibTeX RDF
25	Anala, S. Gayathri, Ramesh Ramaswamy, Chetan Waghmare	An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment.	SN Comput. Sci.	2020	DBLP DOI BibTeX RDF
25	Cheng Zhuo, Bei Yu 0001, Di Gao	Accelerating chip design with machine learning: From pre-silicon to post-silicon.	SoCC	2017	DBLP DOI BibTeX RDF
25	Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra	Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
25	Fa Wang	Efficient Pre-Silicon Validation and Post-Silicon Tuning of Self-Healing Analog/RF Integrated Circuits.		2015	DOI RDF
25	Xin Li 0001, Fa Wang, Shupeng Sun, Chenjie Gu	Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits.	ICCAD	2013	DBLP DOI BibTeX RDF
25	Prasanjeet Das, Sandeep K. Gupta 0001	Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning.	VTS	2013	DBLP DOI BibTeX RDF
25	Mehdi Dehbashi	Debug automation from pre-silicon to post-silicon.		2013	RDF
25	Mehdi Dehbashi, Görschwin Fey	Automated debugging from pre-silicon to post-silicon.	DDECS	2012	DBLP DOI BibTeX RDF
25	Allon Adir, Shady Copty, Shimon Landa, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	A unified methodology for pre-silicon verification and post-silicon validation.	DATE	2011	DBLP DOI BibTeX RDF
25	Allon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann	Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor.	DAC	2011	DBLP DOI BibTeX RDF
25	Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen 0024, George Bakewell	A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.	DAC	2011	DBLP DOI BibTeX RDF
22	Sofiane Takarabt	Pre-silicon evaluation of secured circuit against side-channel attacks. (Évaluation pré-silicium de circuits sécurisés face aux attaques par canal auxiliaire).		2021	RDF
22	Pradip Bose	Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	performance test cases, bounds modeling, performance validation, integrated methodology, test generation, microprocessor testing
21	Walid Ibrahim	A Novel EDA Tool for VLSI Test Vectors Management.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Test vectors selection, Genetic algorithms, Verification, VLSI, EDA tools
21	K. Uday Bhaskar, M. Prasanth, V. Kamakoti 0001, Kailasnath Maneparambil	A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Kaiyu Chen, Sharad Malik, Priyadarsan Patra	Runtime validation of memory ordering using constraint graph checking.	HPCA	2008	DBLP DOI BibTeX RDF
16	Elias Perdomo, Alexander Kropotov, Francelly Cano, Syed Zafar, Teresa Cervero, Xavier Martorell, Behzad Salami 0001	Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.	CoRR	2024	DBLP DOI BibTeX RDF
16	Yanbin Li, Jiajie Zhu, Zhe Liu 0001, Ming Tang 0002, Shougang Ren	Deep Learning Gradient Visualization-Based Pre-Silicon Side-Channel Leakage Location.	IEEE Trans. Inf. Forensics Secur.	2024	DBLP DOI BibTeX RDF
16	Elias Perdomo, Alexander Kropotov, Francelly Katherine Cano Ladino, Syed Zafar, Teresa Cervero, Xavier Martorell Bofill, Behzad Salami 0001	Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.	RAPIDO@HiPEAC	2024	DBLP DOI BibTeX RDF
16	Farimah Farahmandi, Ankur Srivastava 0001, Giorgio Di Natale, Mark M. Tehranipoor	Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.	ACM J. Emerg. Technol. Comput. Syst.	2023	DBLP DOI BibTeX RDF
16	Haocheng Ma, Max Panoff, Jiaji He, Yiqiang Zhao, Yier Jin	EMSim: A Fast Layout Level Electromagnetic Emanation Simulation Framework for High Accuracy Pre-Silicon Verification.	IEEE Trans. Inf. Forensics Secur.	2023	DBLP DOI BibTeX RDF
16	Dillibabu Shanmugam, Patrick Schaumont	Improving Side-channel Leakage Assessment Using Pre-silicon Leakage Models.	COSADE	2023	DBLP DOI BibTeX RDF
16	Abdullah Aljuffri, Mudit Saxena, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil	A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks.	DSD	2023	DBLP DOI BibTeX RDF
16	Moein Ghaniyoun, Kristin Barber, Yuan Xiao 0001, Yinqian Zhang, Radu Teodorescu	TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments.	ISCA	2023	DBLP DOI BibTeX RDF
16	Dima Nikiforov, Shengjun Chris Dong, Chengyi Lux Zhang, Seah Kim, Borivoje Nikolic, Yakun Sophia Shao	RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation.	ISCA	2023	DBLP DOI BibTeX RDF
16	Jasper Van Woudenberg, Peter Grossmann, Avinash Varna 0001, Joseph Friel, Daniel Dinu, Ronnie Lindsay, Steve J. Brown	Invited: Pre-silicon Side Channel and Fault Analysis.	DAC	2023	DBLP DOI BibTeX RDF
16	Saranyu Chattopadhyay, Keerthikumara Devarajegowda, Bihan Zhao, Florian Lonsing, Brandon A. D'Agostino, Ioanna Vavelidou, Vijay Deep Bhatt, Sebastian Prebeck, Wolfgang Ecker, Caroline Trippel, Clark W. Barrett, Subhasish Mitra	G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.	DAC	2023	DBLP DOI BibTeX RDF
16	Kristin Barber, Moein Ghaniyoun, Yinqian Zhang, Radu Teodorescu	A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
16	Ashish Sharma 0005, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi, Manoj Gupta	Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
16	Pantea Kiaei, Zhenyuan Liu, Patrick Schaumont	Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment.	CoRR	2022	DBLP DOI BibTeX RDF
16	Pascal Nasahl, Miguel Osorio, Pirmin Vogel, Michael Schaffner, Timothy Trippel, Dominic Rizzo, Stefan Mangard	SYNFI: Pre-Silicon Fault Analysis of an Open-Source Secure Element.	CoRR	2022	DBLP DOI BibTeX RDF
16	Pascal Nasahl, Miguel Osorio, Pirmin Vogel, Michael Schaffner, Timothy Trippel, Dominic Rizzo, Stefan Mangard	SYNFI: Pre-Silicon Fault Analysis of an Open-Source Secure Element.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2022	DBLP DOI BibTeX RDF
16	A. V. Lakshmy, Chester Rebeiro, Swarup Bhunia	FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs.	ASP-DAC	2022	DBLP DOI BibTeX RDF
16	Javad Bahrami, Mohammad Ebrahimabadi, Sofiane Takarabt, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi	On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis.	SECRYPT	2022	DBLP DOI BibTeX RDF
16	Tessil Thomas, Bharath Venkatasubramanian, Dinesh Sthapit, Christopher Gray, Atresh Gummadavelly, Janick Bergeron, Pankaj Mehta, Prabu Thangamuthu	Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips.	ISPASS	2022	DBLP DOI BibTeX RDF
16	Dmitry Utyamishev, Inna Partin-Vaisband	Knowledge Graph Embedding and Visualization for Pre-Silicon Detection of Hardware Trojans.	ISCAS	2022	DBLP DOI BibTeX RDF
16	Pantea Kiaei, Zhenyuan Liu, Patrick Schaumont	Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
16	Nitin Pundir, Henian Li, Lang Lin, Norman Chang, Farimah Farahmandi, Mark M. Tehranipoor	Security Properties Driven Pre-Silicon Laser Fault Injection Assessment.	HOST	2022	DBLP DOI BibTeX RDF
16	Umer Farooq 0001, Habib Mehrez	Pre-Silicon Verification Using Multi-FPGA Platforms: A Review.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
16	Karthik Ganesan 0001, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra	Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection.	CoRR	2021	DBLP BibTeX RDF
16	Yuan Yao, Tuna B. Tufan, Tarun Kathuria, Baris Ege, Ulkuhan Guler 0001, Patrick Schaumont	Pre-silicon Architecture Correlation Analysis (PACA): Identifying and Mitigating the Source of Side-channel Leakage at Gate-level.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
16	Víctor Fernández 0001, Carlos Abad, Ángel Álvarez, Íñigo Ugarte, Pablo Sánchez	Pre-Silicon FEC Decoding Verification on SoC FPGAs.	IEEE Commun. Lett.	2021	DBLP DOI BibTeX RDF
16	Alexander Hepp, Georg Sigl	Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability.	CF	2021	DBLP DOI BibTeX RDF
16	Yi Xu, Zhenyi Chen, Binhong Huang, Ximeng Liu, Chen Dong 0002	HTtext: A TextCNN-based pre-silicon detection for hardware Trojans.	ISPA/BDCloud/SocialCom/SustainCom	2021	DBLP DOI BibTeX RDF
16	Bikash Kumar Moharana, Anirudh S. Koushik, Kahkeshan Naz	Top-Down analysis based performance failure bucketing for Pre-Silicon simulation.	ICCCNT	2021	DBLP DOI BibTeX RDF
16	Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu	INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities.	ISCA	2021	DBLP DOI BibTeX RDF
16	Keerthikumara Devarajegowda	Model-based Generation of Assertions for Pre-silicon Verification.		2021	RDF
16	Yanbin Li, Ming Tang 0002, Yuguang Li, Huanguo Zhang	A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs.	Integr.	2020	DBLP DOI BibTeX RDF
16	Fern Nee Tan, Jia Yun Chuah	Pre-silicon Noise to Timing Test Methodology.	ATS	2020	DBLP DOI BibTeX RDF
16	Rajat Sadhukhan, Paulson Mathew, Debapriya Basu Roy, Debdeep Mukhopadhyay	Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
16	Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan 0001, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra	Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.	CoRR	2019	DBLP BibTeX RDF
16		Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores.	CoRR	2019	DBLP BibTeX RDF
16	Annachiara Ruospo, Ernesto Sánchez 0001	On the Detection of Always-On Hardware Trojans Supported by a Pre-Silicon Verification Methodology.	MTV	2019	DBLP DOI BibTeX RDF
16	Sebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille	Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows.	ISVLSI	2019	DBLP DOI BibTeX RDF
16	Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan 0001, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra	Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.	DATE	2019	DBLP DOI BibTeX RDF
16	Elena-Diana Sandru, Emilian David, Georg Pelz	Pre-Silicon Yield Estimation using Machine Learning Regression.	ICECS	2019	DBLP DOI BibTeX RDF
16	Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, Yier Jin	QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.	HOST	2019	DBLP DOI BibTeX RDF
16	Pratheema Mohandoss, Archana Rengaraj	Pre-Silicon DFT Verification on SOC Slim Model.	MTV	2018	DBLP DOI BibTeX RDF
16	Keerthikumara Devarajegowda, Wolfgang Ecker	Meta-model Based Automation of Properties for Pre-Silicon Verification.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
16	Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz	Symbolic quick error detection using symbolic initial state for pre-silicon verification.	DATE	2018	DBLP DOI BibTeX RDF
16	Ipsita Biswas Mahapatra, S. K. Nandy 0001	An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification.	ISED	2018	DBLP DOI BibTeX RDF
16	Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi	Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification.	IVSW	2018	DBLP DOI BibTeX RDF
16	Jing Ye 0001, Yipei Yang, Yue Gong, Yu Hu 0001, Xiaowei Li 0001	Grey Zone in Pre-Silicon Hardware Trojan Detection.	ITC-Asia	2018	DBLP DOI BibTeX RDF
16	Nicole Fern, Kwang-Ting (Tim) Cheng	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security.	ITC	2018	DBLP DOI BibTeX RDF
16	Sebastian Simon, Jérôme Kirscher, Alexander W. Rath, Zhiqiang Zhang, Linus Maurer	Pre-silicon Verification of an Automotive Battery Management System in the Context of the Application.	MBMV	2017	DBLP BibTeX RDF
16	Senwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak	A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor.	MTV	2016	DBLP DOI BibTeX RDF
16	Gabriel A. G. Andrade, Marleson Graf, Luiz C. V. dos Santos	Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems.	ICCD	2016	DBLP DOI BibTeX RDF
16	Xiaolong Guo, Raj Gautam Dutta, Yier Jin	Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance.	MTV	2015	DBLP DOI BibTeX RDF
16	Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd	A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology.	CICC	2015	DBLP DOI BibTeX RDF
16	Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, Prabhat Mishra 0001	Pre-silicon security verification and validation: a formal perspective.	DAC	2015	DBLP DOI BibTeX RDF
16	Qi Guo 0001, Tianshi Chen 0002, Yunji Chen, Rui Wang 0022, Huanhuan Chen, Weiwu Hu, Guoliang Chen 0001	Pre-Silicon Bug Forecast.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
16	Parijat Mukherjee, Peng Li 0001	Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits.	DAC	2014	DBLP DOI BibTeX RDF
16	Raghudeep Kannavara	Towards a unified framework for pre-silicon validation.	IISA	2013	DBLP DOI BibTeX RDF
16	Olav P. Henschel, Luiz C. V. dos Santos	Pre-silicon verification of multiprocessor SoCs: The case for on-the-fly coherence/consistency checking.	ICECS	2013	DBLP DOI BibTeX RDF
16	Sergii Berdyshev, Vladimir Boykov, Yuri Gimpilevich, Yuri Iskiv, Gilad Keren, Denis Muratov, Igor Smirnov 0002, Valeriy Vertegel	Methodology of the pre-silicon verification of the processor core.	EWDTS	2011	DBLP DOI BibTeX RDF
16	Xu Guo 0001, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont	Pre-silicon Characterization of NIST SHA-3 Final Round Candidates.	DSD	2011	DBLP DOI BibTeX RDF
16	Frederic Risacher, Kenneth J. Schultz	Software agnostic approaches to explore pre-silicon system performance.	HLDVT	2011	DBLP DOI BibTeX RDF
16	Mainak Banga, Michael S. Hsiao	Trusted RTL: Trojan Detection Methodology in Pre-silicon Designs.	HOST	2010	DBLP DOI BibTeX RDF