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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 242 occurrences of 204 keywords
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Results
Found 226 publication records. Showing 226 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
57 | Prabhat Mishra 0001, Mahesh Mamidipaka, Nikil D. Dutt |
Processor-memory coexploration using an architecture description language. |
ACM Trans. Embed. Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Processor-memory codesign, memory exploration, design space exploration, architecture description language |
47 | Minsu Choi, Nohpill Park, Fabrizio Lombardi |
Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy |
44 | Prabhat Mishra 0001, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Xi Chen 0068, Robert P. Dick, Alok N. Choudhary |
Operating System Controlled Processor-Memory Bus Encryption. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron |
Memory-miser: a performance-constrained runtime system for power-scalable clusters. |
Conf. Computing Frontiers |
2007 |
DBLP DOI BibTeX RDF |
resource allocation, control, power management, memory |
35 | Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen |
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA |
35 | Ashley Saulsbury, Fong Pong, Andreas Nowatzyk |
Missing the Memory Wall: The Case for Processor/Memory Integration. |
ISCA |
1996 |
DBLP DOI BibTeX RDF |
|
29 | Sajal K. Das 0001, Sanjoy K. Sen |
Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. |
IPPS |
1996 |
DBLP DOI BibTeX RDF |
buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time |
27 | Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt |
A new approach to parallelising tracing algorithms. |
ISMM |
2009 |
DBLP DOI BibTeX RDF |
memory-centric tracing algorithm, parallel |
27 | Trishul M. Chilimbi, Mark D. Hill, James R. Larus |
Making Pointer-Based Data Structures Cache Conscious. |
Computer |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl |
Processor/Memory Co-Exploration on Multiple Abstraction Levels. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Keun Soo Yim, Jang-Soo Lee, Jihong Kim 0001, Shin-Dug Kim, Kern Koh |
A Space-Efficient On-Chip Compressed Cache Organization for High Performance Computing. |
ISPA |
2004 |
DBLP DOI BibTeX RDF |
processor-memory performance gap, on-chip compressed cache, fine-grained management, internal fragmentation problem, Parallel processing |
25 | Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee |
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
processor-memory, VLSI, performance modeling, three dimensional, 3D ICs, vertical integration, thermal analysis |
24 | Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou |
Cross-component energy management: Joint adaptation of processor and memory. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
low-power design, memory, adaptive systems, processor, Energy management, performance guarantee, control algorithms |
24 | Nathan Fisher, James H. Anderson, Sanjoy K. Baruah |
Task Partitioning upon Memory-Constrained Multiprocessors. |
RTCSA |
2005 |
DBLP DOI BibTeX RDF |
Memory-constrained systems, Utilization-based schedulability tests, Multiprocessor systems, Partitioned scheduling |
23 | Prasad Krishna Saravu |
Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker. |
MTV |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Shuo-Hsien Hsiao, C. Y. Roger Chen |
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. |
IEEE Trans. Parallel Distributed Syst. |
1992 |
DBLP DOI BibTeX RDF |
message size, circuit switched multistage interconnection networks, hold strategy, processor-memory communications, processor processing time, closed queuing network model, performance evaluation, performance evaluation, multiprocessor interconnection networks, queueing theory, multiprocessor systems, switching theory, memory access |
21 | Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang |
Chip Multithreaded Consistency Model. |
J. Comput. Sci. Technol. |
2008 |
DBLP DOI BibTeX RDF |
Godson-2, computer architecture, multithreading, memory consistency model, event ordering |
21 | Hans M. Mulder |
Data Buffering: Run-Time Versus Compile-Time Support. |
ASPLOS |
1989 |
DBLP DOI BibTeX RDF |
|
20 | Taskin Koçak, Jacob Engel |
Performance evaluation of wormhole routed network processor-memory interconnects. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ali El-Haj-Mahmoud, Eric Rotenberg |
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, multithreading, worst-case execution time, memory latency, schedulability test |
20 | Per Stenström |
The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. |
HiPEAC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Lory D. Molesky, Krithi Ramamritham |
Recovery Protocols for Shared Memory Database Systems. |
SIGMOD Conference |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Hans Eberle |
Analysis of processor-memory communication by the NS 32000 processor family. |
Microprocess. Microprogramming |
1988 |
DBLP DOI BibTeX RDF |
|
19 | I. K. Hetherington, P. Kusulas |
The 3B20D Processor & DMERT operating system: 3B20D Processor memory systems. |
Bell Syst. Tech. J. |
1983 |
DBLP DOI BibTeX RDF |
|
19 | Shankar Mahadevan, Michael Storgaard, Jan Madsen, Kashif Virk |
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. |
MASCOTS |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam |
Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Cociorva, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam |
Memory-Constrained Communication Minimization for a Class of Array Computations. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Karl-Erwin Großpietsch, Tanya A. Silayeva |
A Combined Safety/Security Approach for Co-Operative Distributed Systems. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Low-Cost Software-Based Self-Testing of RISC Processor Cores. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Rony Ghattas, Gregory S. Parsons, Alexander G. Dean |
Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2007 |
DBLP DOI BibTeX RDF |
|
17 | William Leinberger, George Karypis, Vipin Kumar 0001 |
Memory Management Techniques for Gang Scheduling. |
Euro-Par |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Bruce R. Childers, Tarun Nakra |
Reordering Memory Bus Transactions for Reduced Power Consumption. |
LCTES |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. |
NCA |
2003 |
DBLP DOI BibTeX RDF |
Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy |
16 | Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf |
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. |
HPCA |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jaehyun Park 0006, Byeongho Kim, Sungmin Yun, Eojin Lee, Minsoo Rhu, Jung Ho Ahn |
TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory. |
MICRO |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. |
PDP |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski |
Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy. |
J. Syst. Archit. |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Philip Jacob 0001, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald 0001, Kerry Bernstein |
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. |
Proc. IEEE |
2009 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Using Cache Memory to Reduce Processor-Memory Traffic. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Using Cache Memory to Reduce Processor-Memory Traffic |
ISCA |
1983 |
DBLP DOI BibTeX RDF |
|
16 | Li Chen, Sujit Dey |
Software-based self-testing methodology for processor cores. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Easwaran Raman, David I. August |
Recursive data structure profiling. |
Memory System Performance |
2005 |
DBLP DOI BibTeX RDF |
RDS, dynamic shape graph, list linearization, memory profiling, shape profiling |
15 | Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen |
Enhanced Configurable Parallel Memory Architecture. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Abhaya Asthana, Nandit Soparkar, H. V. Jagadish, Paul Krzyzanowski |
Logic-enhanced memory for high performance databases. |
KES (2) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Daniel H. Linder, James C. Harden |
Access Graphs: A Model for Investigating Memory Consistency. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
access pipelining, synchronization, caches, computer architecture, computer architectures, synchronisation, shared memory systems, memory consistency, massively parallel systems |
15 | Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon |
Analytic Evaluation of Shared-Memory Architectures. |
IEEE Trans. Parallel Distributed Syst. |
2003 |
DBLP DOI BibTeX RDF |
performance evaluation, heterogeneity, Analytical model, shared memory multiprocessor, mean value analysis |
15 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security |
15 | Pyrrhos Stathis, Dmitry Cheresiz, Stamatis Vassiliadis, Ben H. H. Juurlink |
Sparse Matrix Transpose Unit. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Martti Forsell, Martti Penttonen, Ville Leppänen |
Efficient Two-Level Mesh based Simulation of PRAMs. |
ISPAN |
1996 |
DBLP DOI BibTeX RDF |
time-processor optimal, simulation, interconnection network, mesh, PRAM, shared memory machine |
15 | Joseph P. Heid |
A hybrid computer interface for microprocessors. |
AFIPS National Computer Conference |
1977 |
DBLP DOI BibTeX RDF |
|
14 | Eduardo Braulio Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet |
A Code Compression Method to Cope with Security Hardware Overheads. |
SBAC-PAD |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Dennis Abts, Abdulla Bataineh, Steve Scott, Greg Faanes, Jim Schwarzmeier, Eric Lundberg, Tim Johnson, Mike Bye, Gerald Schwoerer |
The Cray BlackWidow: a highly scalable vector multiprocessor. |
SC |
2007 |
DBLP DOI BibTeX RDF |
high-radix, architecture, multiprocessor, shared memory, distributed shared memory, vector, fat-tree, MPP |
14 | Uzi Vishkin |
Two techniques for reconciling algorithm parallelism with memory constraints. |
SPAA |
2002 |
DBLP DOI BibTeX RDF |
memory systems constraints, parallel algorithms, prefetching |
14 | Krishna Kant 0001, Youjip Won |
Server Capacity Planning for Web Traffic Workload. |
IEEE Trans. Knowl. Data Eng. |
1999 |
DBLP DOI BibTeX RDF |
caching/proxy server, band-width requirements, Web server, self-similarity, symmetric multiprocessors, traffic characterization |
14 | Neil C. Audsley, Konstantinos Bletsas |
Fixed Priority Timing Analysis of Real-Time Systems with Limited Parallelism. |
ECRTS |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
Embedded hardware and software self-testing methodologies for processor cores. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Kris Venstermans, Lieven Eeckhout, Koen De Bosschere |
Java object header elimination for reduced memory consumption in 64-bit virtual machines. |
ACM Trans. Archit. Code Optim. |
2007 |
DBLP DOI BibTeX RDF |
64-bit implementation, Java object model, implicit typing, typed virtual addressing, Virtual machine |
14 | Tushar Mohan, Bronis R. de Supinski, Sally A. McKee, Frank Mueller 0001, Andy Yoo, Martin Schulz 0001 |
Identifying and Exploiting Spatial Regularity in Data Memory References. |
SC |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis |
Algorithmic foundations for a parallel vector access memory system. |
SPAA |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schlatter Ellis |
Power Aware Page Allocation. |
ASPLOS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Arnold Neville Pears, Rhys S. Francis |
Barrier Semantics in Very Weak Memory. |
PARLE |
1993 |
DBLP DOI BibTeX RDF |
|
13 | Peter Bertels, Wim Heirman, Dirk Stroobandt |
Strategies for dynamic memory allocation in hybrid architectures. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
java, memory management, hardware acceleration |
13 | Bithika Khargharia, Salim Hariri, Wael Kdouh, Manal Houri, Hesham El-Rewini, Mazin S. Yousif |
Autonomic power and performance management of high-performance servers. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Lakshminarayanan Subramanian, Karthikeyan Mahesh |
Efficient End-Host Resource Management with Kernel Optimizations for Multimedia Applications. |
ECMAST |
1999 |
DBLP DOI BibTeX RDF |
|
13 | John R. Feehrer, Jon Sauer, Lars H. Ramfelt |
Design and Implementation of a Prototype Optical Deflection Network. |
SIGCOMM |
1994 |
DBLP DOI BibTeX RDF |
|
13 | Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage |
Clock Synchronization through Handshake Signalling. |
ASYNC |
2002 |
DBLP DOI BibTeX RDF |
GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures |
13 | Jason E. Fritts, Roger D. Chamberlain |
Breaking the Memory Bottleneck with an Optical Data Path. |
Annual Simulation Symposium |
2002 |
DBLP DOI BibTeX RDF |
bandwidth bottleneck, processor-memory gap, performance evaluation, media processing, optical bus |
13 | Peter J. Varman, I. V. Ramakrishnan |
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays. |
IEEE Trans. Computers |
1986 |
DBLP DOI BibTeX RDF |
extensible algorithms, processor-memory tradeoff, parallel processing, VLSI, matrix multiplication, Array Processors, linear array |
13 | Leonard Uhr |
Comparing Serial Computers, Arrays, and Networks Using Measures of "Active Resources". |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
Active resources, evaluating computer power, processor-memory ratio, image processing, parallel computers, SIMD, MIMD |
12 | K. Ganeshamoorthy, D. N. Ranasinghe |
On the Performance of Parallel Neural Network Implementations on Distributed Memory Architectures. |
CCGRID |
2008 |
DBLP DOI BibTeX RDF |
Parallel neural network, Hybrid partition, VSM, DM |
12 | Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram |
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee |
A low-cost memory remapping scheme for address bus protection. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
address bus leakage protection, secure processor |
12 | Karl Thaller, Andreas Steininger |
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. |
IEEE Trans. Reliab. |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li 0001 |
An evaluation of a compiler optimization for improving the performance of a coherence directory. |
International Conference on Supercomputing |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Sobhan Niknam, Yixian Shen, Anuj Pathania, Andy D. Pimentel |
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems. |
ISVLSI |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda |
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. |
ACM Trans. Archit. Code Optim. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda |
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
12 | Amirali Boroumand |
Practical Mechanisms for Reducing Processor-Memory Data Movement in Modern Workloads. |
|
2021 |
DOI RDF |
|
12 | Naveed Ul Mustafa |
Reducing processor-memory performance gap and improving network-on-chip throughput (İşlemci-bellek performans farkını azaltmak ve yonga-üstü-ağ verimini artırmak) |
|
2019 |
RDF |
|
12 | Sam Van den Steen, Lieven Eeckhout |
Modeling Superscalar Processor Memory-Level Parallelism. |
IEEE Comput. Archit. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Karthik Rao, William J. Song, Yorai Wardi, Sudhakar Yalamanchili |
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
12 | Keith D. Cooper, Xiaoran Xu |
Efficient Characterization of Hidden Processor Memory Hierarchies. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
12 | Baki Berkay Yilmaz, Alenka G. Zajic, Milos Prvulovic |
Modelling Jitter in Wireless Channel Created by Processor-Memory Activity. |
ICASSP |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Keith D. Cooper, Xiaoran Xu |
Efficient Characterization of Hidden Processor Memory Hierarchies. |
ICCS (3) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Aditya Agrawal, Josep Torrellas, Sachin Idgunji |
Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. |
MICRO |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan |
Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraints. |
ISQED |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Henry Wong, Vaughn Betz, Jonathan Rose |
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. |
ACM Trans. Reconfigurable Technol. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Hyuk-Je Kwon, Yongseok Choi |
Protocol for a Simplified Processor-Memory Interface Using High-Speed Serial Link. |
CloudComp |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Etienne Sicard, Alexandre Boyer, Priscila Fernandez-Lopez, An Zhou, Nicolas Marier, Frédéric Lafon |
EMC performance analysis of a processor/memory system using PCB and Package-On-Package. |
EMC Compo |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Steven G. Smith, David R. Jefferson, Peter D. Barnes Jr., Sergei Nikolaev |
Improving per processor memory use of ns-3 to enable large scale simulations. |
WNS3 |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Sobhan Niknam, Arghavan Asad, Mahmood Fathy, Amir-Mohammad Rahmani |
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. |
ReCoSoC |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Wooil Kim |
Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy |
|
2015 |
RDF |
|
12 | Alvaro Velasquez, Sumit Kumar Jha 0001 |
Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck. |
IDT |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski |
3D DRAM and PCMs in Processor Memory Hierarchy. |
ARCS |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Suhas M. Satheesh, Emre Salman |
Power Distribution in TSV-Based 3-D Processor-Memory Stacks. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
12 | Aamir Zia, Philip Jacob 0001, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald 0001 |
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. |
IEEE Trans. Very Large Scale Integr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
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