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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 242 occurrences of 204 keywords
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Results
Found 226 publication records. Showing 226 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
57 | Prabhat Mishra 0001, Mahesh Mamidipaka, Nikil D. Dutt |
Processor-memory coexploration using an architecture description language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(1), pp. 140-162, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Processor-memory codesign, memory exploration, design space exploration, architecture description language |
47 | Minsu Choi, Nohpill Park, Fabrizio Lombardi |
Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy |
44 | Prabhat Mishra 0001, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 70-75, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Xi Chen 0068, Robert P. Dick, Alok N. Choudhary |
Operating System Controlled Processor-Memory Bus Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1154-1159, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron |
Memory-miser: a performance-constrained runtime system for power-scalable clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 237-246, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
resource allocation, control, power management, memory |
35 | Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen |
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 15-25, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA |
35 | Ashley Saulsbury, Fong Pong, Andreas Nowatzyk |
Missing the Memory Wall: The Case for Processor/Memory Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 90-101, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
29 | Sajal K. Das 0001, Sanjoy K. Sen |
Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 281-285, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time |
27 | Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt |
A new approach to parallelising tracing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 8th International Symposium on Memory Management, ISMM 2009, Dublin, Ireland, June 19-20, 2009, pp. 10-19, 2009, ACM, 978-1-60558-347-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory-centric tracing algorithm, parallel |
27 | Trishul M. Chilimbi, Mark D. Hill, James R. Larus |
Making Pointer-Based Data Structures Cache Conscious. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 33(12), pp. 67-74, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl |
Processor/Memory Co-Exploration on Multiple Abstraction Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10966-10973, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Keun Soo Yim, Jang-Soo Lee, Jihong Kim 0001, Shin-Dug Kim, Kern Koh |
A Space-Efficient On-Chip Compressed Cache Organization for High Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Second InternationalSymposium, ISPA 2004, Hong Kong, China, December 13-15, 2004, Proceedings, pp. 952-964, 2004, Springer, 3-540-24128-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
processor-memory performance gap, on-chip compressed cache, fine-grained management, internal fragmentation problem, Parallel processing |
25 | Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee |
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 991-996, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
processor-memory, VLSI, performance modeling, three dimensional, 3D ICs, vertical integration, thermal analysis |
24 | Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou |
Cross-component energy management: Joint adaptation of processor and memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(3), pp. 14, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low-power design, memory, adaptive systems, processor, Energy management, performance guarantee, control algorithms |
24 | Nathan Fisher, James H. Anderson, Sanjoy K. Baruah |
Task Partitioning upon Memory-Constrained Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 416-421, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Memory-constrained systems, Utilization-based schedulability tests, Multiprocessor systems, Partitioned scheduling |
23 | Prasad Krishna Saravu |
Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 17th International Workshop on Microprocessor and SOC Test and Verification, MTV 2016, Austin, TX, USA, December 12-13, 2016, pp. 7-14, 2016, IEEE Computer Society, 978-1-4673-8924-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Shuo-Hsien Hsiao, C. Y. Roger Chen |
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(5), pp. 632-640, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
message size, circuit switched multistage interconnection networks, hold strategy, processor-memory communications, processor processing time, closed queuing network model, performance evaluation, performance evaluation, multiprocessor interconnection networks, queueing theory, multiprocessor systems, switching theory, memory access |
21 | Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang |
Chip Multithreaded Consistency Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(2), pp. 298-305, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Godson-2, computer architecture, multithreading, memory consistency model, event ordering |
21 | Hans M. Mulder |
Data Buffering: Run-Time Versus Compile-Time Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 144-151, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
20 | Taskin Koçak, Jacob Engel |
Performance evaluation of wormhole routed network processor-memory interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ali El-Haj-Mahmoud, Eric Rotenberg |
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 2-13, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, multithreading, worst-case execution time, memory latency, schedulability test |
20 | Per Stenström |
The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings, pp. 5, 2005, Springer, 3-540-30317-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Lory D. Molesky, Krithi Ramamritham |
Recovery Protocols for Shared Memory Database Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 1995 ACM SIGMOD International Conference on Management of Data, San Jose, California, USA, May 22-25, 1995., pp. 11-22, 1995, ACM Press, 978-0-89791-731-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Hans Eberle |
Analysis of processor-memory communication by the NS 32000 processor family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 22(5), pp. 367-377, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | I. K. Hetherington, P. Kusulas |
The 3B20D Processor & DMERT operating system: 3B20D Processor memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Bell Syst. Tech. J. ![In: Bell Syst. Tech. J. 62(1), pp. 207-220, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
19 | Shankar Mahadevan, Michael Storgaard, Jan Madsen, Kashif Virk |
ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 13th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2005), 27-29 September 2005, Atlanta, GA, USA, pp. 480-483, 2005, IEEE Computer Society, 0-7695-2458-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam |
Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 37, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Cociorva, Gerald Baumgartner, Chi-Chung Lam, P. Sadayappan, J. Ramanujam |
Memory-Constrained Communication Minimization for a Class of Array Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 1-15, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Karl-Erwin Großpietsch, Tanya A. Silayeva |
A Combined Safety/Security Approach for Co-Operative Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Low-Cost Software-Based Self-Testing of RISC Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10714-10719, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Rony Ghattas, Gregory S. Parsons, Alexander G. Dean |
Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2007, April 3-6, 2007, Bellevue, Washington, USA, pp. 168-182, 2007, IEEE Computer Society, 978-0-7695-2800-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | William Leinberger, George Karypis, Vipin Kumar 0001 |
Memory Management Techniques for Gang Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 252-261, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Bruce R. Childers, Tarun Nakra |
Reordering Memory Bus Transactions for Reduced Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, Vancouver, BC, Canada, June 18, 2000, Proceedings, pp. 146-161, 2000, Springer, 3-540-41781-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 16-18 April 2003, Cambridge, MA, USA, pp. 341-350, 2003, IEEE Computer Society, 0-7695-1938-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy |
16 | Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf |
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 80-89, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jaehyun Park 0006, Byeongho Kim, Sungmin Yun, Eojin Lee, Minsoo Rhu, Jung Ho Ahn |
TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021, pp. 268-281, 2021, ACM, 978-1-4503-8557-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, pp. 168-175, 2016, IEEE Computer Society, 978-1-4673-8776-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski |
Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 61(10), pp. 539-552, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Philip Jacob 0001, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald 0001, Kerry Bernstein |
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 97(1), pp. 108-122, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
25 Years ISCA: Retrospectives and Reprints ![In: 25 Years of the International Symposia on Computer Architecture (Selected Papers)., pp. 32-33, 1998, ACM, 1-58113-058-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Using Cache Memory to Reduce Processor-Memory Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
25 Years ISCA: Retrospectives and Reprints ![In: 25 Years of the International Symposia on Computer Architecture (Selected Papers)., pp. 255-262, 1998, ACM, 1-58113-058-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | James R. Goodman |
Using Cache Memory to Reduce Processor-Memory Traffic ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 124-131, 1983, ACM, 0-89791-101-6. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
16 | Li Chen, Sujit Dey |
Software-based self-testing methodology for processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 369-380, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Easwaran Raman, David I. August |
Recursive data structure profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 5-14, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RDS, dynamic shape graph, list linearization, memory profiling, shape profiling |
15 | Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen |
Enhanced Configurable Parallel Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 28-37, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Abhaya Asthana, Nandit Soparkar, H. V. Jagadish, Paul Krzyzanowski |
Logic-enhanced memory for high performance databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Electronic Systems, 1st International Conference, KES 1997, Adelaide, South Australia, 21-23 May, 1997, Proceedings, Part II, pp. 517-524, 1997, IEEE. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Daniel H. Linder, James C. Harden |
Access Graphs: A Model for Investigating Memory Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(1), pp. 39-52, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
access pipelining, synchronization, caches, computer architecture, computer architectures, synchronisation, shared memory systems, memory consistency, massively parallel systems |
15 | Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon |
Analytic Evaluation of Shared-Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(2), pp. 166-180, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
performance evaluation, heterogeneity, Analytical model, shared memory multiprocessor, mean value analysis |
15 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 605-609, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 299-304, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security |
15 | Pyrrhos Stathis, Dmitry Cheresiz, Stamatis Vassiliadis, Ben H. H. Juurlink |
Sparse Matrix Transpose Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Martti Forsell, Martti Penttonen, Ville Leppänen |
Efficient Two-Level Mesh based Simulation of PRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 29-35, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
time-processor optimal, simulation, interconnection network, mesh, PRAM, shared memory machine |
15 | Joseph P. Heid |
A hybrid computer interface for microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1977 National Computer Conference, June 13-16, 1977, Dallas, Texas, USA, pp. 207-215, 1977, AFIPS Press, 978-1-4503-7914-4. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
|
14 | Eduardo Braulio Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet |
A Code Compression Method to Cope with Security Hardware Overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 185-192, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Dennis Abts, Abdulla Bataineh, Steve Scott, Greg Faanes, Jim Schwarzmeier, Eric Lundberg, Tim Johnson, Mike Bye, Gerald Schwoerer |
The Cray BlackWidow: a highly scalable vector multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, SC 2007, November 10-16, 2007, Reno, Nevada, USA, pp. 17, 2007, ACM Press, 978-1-59593-764-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-radix, architecture, multiprocessor, shared memory, distributed shared memory, vector, fat-tree, MPP |
14 | Uzi Vishkin |
Two techniques for reconciling algorithm parallelism with memory constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2002, Winnipeg, Manitoba, Canada, August 11-13, 2002, pp. 95-98, 2002, ACM, 1-58113-529-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory systems constraints, parallel algorithms, prefetching |
14 | Krishna Kant 0001, Youjip Won |
Server Capacity Planning for Web Traffic Workload. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 11(5), pp. 731-747, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
caching/proxy server, band-width requirements, Web server, self-similarity, symmetric multiprocessors, traffic characterization |
14 | Neil C. Audsley, Konstantinos Bletsas |
Fixed Priority Timing Analysis of Real-Time Systems with Limited Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June - 2 July 1004, Catania, Italy, Proceedings, pp. 231-238, 2004, IEEE Computer Society, 0-7695-2176-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
Embedded hardware and software self-testing methodologies for processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 625-630, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Kris Venstermans, Lieven Eeckhout, Koen De Bosschere |
Java object header elimination for reduced memory consumption in 64-bit virtual machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(3), pp. 17, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
64-bit implementation, Java object model, implicit typing, typed virtual addressing, Virtual machine |
14 | Tushar Mohan, Bronis R. de Supinski, Sally A. McKee, Frank Mueller 0001, Andy Yoo, Martin Schulz 0001 |
Identifying and Exploiting Spatial Regularity in Data Memory References. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 15-21 November 2003, Phoenix, AZ, USA, CD-Rom, pp. 49, 2003, ACM, 1-58113-695-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis |
Algorithmic foundations for a parallel vector access memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2000, Bar Harbor, Maine, USA, July 9-13, 2000, pp. 156-165, 2000, ACM, 1-58113-185-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schlatter Ellis |
Power Aware Page Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000., pp. 105-116, 2000, ACM Press, 1-58113-317-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Arnold Neville Pears, Rhys S. Francis |
Barrier Semantics in Very Weak Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 728-731, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
13 | Peter Bertels, Wim Heirman, Dirk Stroobandt |
Strategies for dynamic memory allocation in hybrid architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 217-220, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
java, memory management, hardware acceleration |
13 | Bithika Khargharia, Salim Hariri, Wael Kdouh, Manal Houri, Hesham El-Rewini, Mazin S. Yousif |
Autonomic power and performance management of high-performance servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Lakshminarayanan Subramanian, Karthikeyan Mahesh |
Efficient End-Host Resource Management with Kernel Optimizations for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECMAST ![In: Multimedia Applications, Services and Techniques - ECMAST'99, 4th European Conference, Madrid, Spain, May 1999, Proceedings, pp. 46-57, 1999, Springer, 3-540-66082-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | John R. Feehrer, Jon Sauer, Lars H. Ramfelt |
Design and Implementation of a Prototype Optical Deflection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 1994 Conference on Communications Architectures, Protocols and Applications, London, UK, August 31 - September 2, 1994, pp. 191-200, 1994, ACM, 0-89791-682-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
13 | Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage |
Clock Synchronization through Handshake Signalling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 59-68, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures |
13 | Jason E. Fritts, Roger D. Chamberlain |
Breaking the Memory Bottleneck with an Optical Data Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 35th Annual Simulation Symposium (ANSS-35 2002), San Diego, California, USA, 14-18 April 2002, pp. 352-362, 2002, IEEE Computer Society, 0-7695-1552-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bandwidth bottleneck, processor-memory gap, performance evaluation, media processing, optical bus |
13 | Peter J. Varman, I. V. Ramakrishnan |
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(11), pp. 989-996, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
extensible algorithms, processor-memory tradeoff, parallel processing, VLSI, matrix multiplication, Array Processors, linear array |
13 | Leonard Uhr |
Comparing Serial Computers, Arrays, and Networks Using Measures of "Active Resources". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(10), pp. 1022-1025, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
Active resources, evaluating computer power, processor-memory ratio, image processing, parallel computers, SIMD, MIMD |
12 | K. Ganeshamoorthy, D. N. Ranasinghe |
On the Performance of Parallel Neural Network Implementations on Distributed Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 8th IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2008), 19-22 May 2008, Lyon, France, pp. 90-97, 2008, IEEE Computer Society, 978-0-7695-3156-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Parallel neural network, Hybrid partition, VSM, DM |
12 | Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram |
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1072-1077, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee |
A low-cost memory remapping scheme for address bus protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 74-83, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address bus leakage protection, secure processor |
12 | Karl Thaller, Andreas Steininger |
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 52(4), pp. 413-422, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li 0001 |
An evaluation of a compiler optimization for improving the performance of a coherence directory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 75-84, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
12 | Sobhan Niknam, Yixian Shen, Anuj Pathania, Andy D. Pimentel |
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023, Foz do Iguacu, Brazil, June 20-23, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2769-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda |
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 19(3), pp. 44:1-44:25, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda |
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2109.12405, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
12 | Amirali Boroumand |
Practical Mechanisms for Reducing Processor-Memory Data Movement in Modern Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
DOI RDF |
|
12 | Naveed Ul Mustafa |
Reducing processor-memory performance gap and improving network-on-chip throughput (İşlemci-bellek performans farkını azaltmak ve yonga-üstü-ağ verimini artırmak) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
12 | Sam Van den Steen, Lieven Eeckhout |
Modeling Superscalar Processor Memory-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 17(1), pp. 9-12, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Karthik Rao, William J. Song, Yorai Wardi, Sudhakar Yalamanchili |
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1808.09087, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
12 | Keith D. Cooper, Xiaoran Xu |
Efficient Characterization of Hidden Processor Memory Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1807.03104, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
12 | Baki Berkay Yilmaz, Alenka G. Zajic, Milos Prvulovic |
Modelling Jitter in Wireless Channel Created by Processor-Memory Activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2018 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2018, Calgary, AB, Canada, April 15-20, 2018, pp. 2037-2041, 2018, IEEE, 978-1-5386-4658-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Keith D. Cooper, Xiaoran Xu |
Efficient Characterization of Hidden Processor Memory Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (3) ![In: Computational Science - ICCS 2018 - 18th International Conference, Wuxi, China, June 11-13, 2018 Proceedings, Part III, pp. 335-349, 2018, Springer, 978-3-319-93712-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Aditya Agrawal, Josep Torrellas, Sachin Idgunji |
Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017, pp. 546-559, 2017, ACM, 978-1-4503-4952-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan |
Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017, pp. 360-366, 2017, IEEE, 978-1-5090-5404-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Henry Wong, Vaughn Betz, Jonathan Rose |
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 10(1), pp. 7:1-7:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Hyuk-Je Kwon, Yongseok Choi |
Protocol for a Simplified Processor-Memory Interface Using High-Speed Serial Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CloudComp ![In: Cloud Computing - 6th International Conference, CloudComp 2015, Daejeon, South Korea, October 28-29, 2015, Proceedings, pp. 301-310, 2015, Springer, 978-3-319-38903-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Etienne Sicard, Alexandre Boyer, Priscila Fernandez-Lopez, An Zhou, Nicolas Marier, Frédéric Lafon |
EMC performance analysis of a processor/memory system using PCB and Package-On-Package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMC Compo ![In: 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2015, Edinburgh, UK, November 10-13, 2015, pp. 238-243, 2015, IEEE, 978-1-4673-7897-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Steven G. Smith, David R. Jefferson, Peter D. Barnes Jr., Sergei Nikolaev |
Improving per processor memory use of ns-3 to enable large scale simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WNS3 ![In: Proceedings of the 2015 Workshop on ns-3, WNS3 '15, Barcelona, Spain, May 13-14, 2015, pp. 60-66, 2015, ACM, 978-1-4503-3375-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Sobhan Niknam, Arghavan Asad, Mahmood Fathy, Amir-Mohammad Rahmani |
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1, 2015, pp. 1-8, 2015, IEEE, 978-1-4673-7942-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Wooil Kim |
Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
12 | Alvaro Velasquez, Sumit Kumar Jha 0001 |
Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014, pp. 147-152, 2014, IEEE, 978-1-4799-8200-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski |
3D DRAM and PCMs in Processor Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2014 - 27th International Conference, Lübeck, Germany, February 25-28, 2014. Proceedings, pp. 183-195, 2014, Springer, 978-3-319-04890-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
12 | Suhas M. Satheesh, Emre Salman |
Power Distribution in TSV-Based 3-D Processor-Memory Stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 2(4), pp. 692-703, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
12 | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011, pp. 141-146, 2011, IEEE Computer Society, 978-0-7695-4348-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
12 | Aamir Zia, Philip Jacob 0001, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald 0001 |
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(6), pp. 967-977, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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