Search results for "r-nuca"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
193	Javier Lira, Carlos Molina, Antonio González 0001	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
174	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
168	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar	Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.	MICRO	2003	DBLP DOI BibTeX RDF
136	Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete	A NUCA Model for Embedded Systems Cache Design.	ESTIMedia	2005	DBLP DOI BibTeX RDF
118	Thomas Y. Yeh, Glenn Reinman	Fast and fair: data-stream quality of service.	CASES	2005	DBLP DOI BibTeX RDF	NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS
105	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
99	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
80	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
80	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
75	Javier Lira, Carlos Molina, Antonio González 0001	Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs.	Euro-Par	2009	DBLP DOI BibTeX RDF
75	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
75	Sayaka Akioka, Feihui Li, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin	Ring Prediction for Non-Uniform Cache Architectures.	PACT	2007	DBLP DOI BibTeX RDF
68	Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	NUCA, post office placement problem, CMP, data migration
61	Mahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son 0001	A novel migration-based NUCA design for chip multiprocessors.	SC	2008	DBLP DOI BibTeX RDF
56	Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin	Ring data location prediction scheme for Non-Uniform Cache Architectures.	ICCD	2008	DBLP DOI BibTeX RDF
51	Roberto Nuca, Erlend Storvik, Florin A. Radu, Matteo Icardi	Splitting Schemes for Coupled Differential Equations: Block Schur-Based Approaches and Partial Jacobi Approximation.	CoRR	2022	DBLP DOI BibTeX RDF
48	David Corbalán-Navarro, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González 0001	DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficient Graphics Rendering.	PDP	2022	DBLP DOI BibTeX RDF
48	Paul Caheny, Lluc Alvarez, Marc Casas, Miquel Moretó	TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models.	SC	2022	DBLP DOI BibTeX RDF
48	Jagadish Kotra, Mohammad Arjomand, Diana R. Guttman, Mahmut T. Kandemir, Chita R. Das	Re-NUCA: A Practical NUCA Architecture for ReRAM Based Last-Level Caches.	IPDPS	2016	DBLP DOI BibTeX RDF
48	Anuj Arora, Mayur Harne, Hameedah Sultan, Akriti Bagaria, Smruti R. Sarangi	FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches.	IEEE Trans. Parallel Distributed Syst.	2015	DBLP DOI BibTeX RDF
48	Hui Wang, Chunrong Lai, Yicong Huang 0004, Shih-Lien Lu, Rui Wang 0014, Zhongzhi Luan, Depei Qian	Remapping NUCA: Improving NUCA Cache's Power Efficiency.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
43	Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang	No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.	DAC	2009	DBLP DOI BibTeX RDF	level-1 non-uniform cache architecture, ring interconnection, single-cycle transactions, multi-core, NOC, SOC, arbitration, memory structure
43	Haakon Dybdahl, Per Stenström	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors.	HPCA	2007	DBLP DOI BibTeX RDF
37	Changkyu Kim, Doug Burger, Stephen W. Keckler	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.	ASPLOS	2002	DBLP DOI BibTeX RDF
25	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
25	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	Dynamic cache clustering for chip multiprocessors.	ICS	2009	DBLP DOI BibTeX RDF	non-uniform cache architecture (nuca), chip multiprocessor (cmp)
25	Lei Jin 0002, Hyunjin Lee, Sangyeun Cho	A flexible data to L2 cache mapping approach for future multicore processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	non-uniform cache architecture (NUCA), page allocation
24	Yixian Shen, Sobhan Niknam, Anuj Pathania, Andy D. Pimentel	Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations.	DATE	2023	DBLP DOI BibTeX RDF
24	Martin Rapp, Anuj Pathania, Tulika Mitra, Jörg Henkel	Neural Network-Based Performance Prediction for Task Migration on S-NUCA Many-Cores.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
24	Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang 0001, Jianlei Yang 0001, Zhaohao Wang, Dijun Liu, Weisheng Zhao	A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
24	Brian C. Schwedock, Nathan Beckmann	Jumanji: The Case for Dynamic NUCA in the Datacenter.	MICRO	2020	DBLP DOI BibTeX RDF
24	Martin Rapp, Anuj Pathania, Tulika Mitra, Jörg Henkel	Prediction-Based Task Migration on S-NUCA Many-Cores.	DATE	2019	DBLP DOI BibTeX RDF
24	Zicong Wang, Xiaowen Chen, Zhonghai Lu, Yang Guo 0003	Cache Access Fairness in 3D Mesh-Based NUCA.	IEEE Access	2018	DBLP DOI BibTeX RDF
24	Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete	Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.	Future Gener. Comput. Syst.	2018	DBLP DOI BibTeX RDF
24	Anuj Pathania, Jörg Henkel	Task scheduling for many-cores with S-NUCA caches.	DATE	2018	DBLP DOI BibTeX RDF
24	Eldhose Peter, Anuj Arora, Janibul Bashir, Akriti Bagaria, Smruti R. Sarangi	Optical Overlay NUCA: A High-Speed Substrate for Shared L2 Caches.	ACM J. Emerg. Technol. Comput. Syst.	2017	DBLP DOI BibTeX RDF
24	Zicong Wang, Xiaowen Chen, Chen Li 0015, Yang Guo 0003	Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.	NOCS	2017	DBLP DOI BibTeX RDF
24	Hela Belhadj Amor, Abbas Sheibanyrad, Frédéric Pétrot	A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support.	DSD	2017	DBLP DOI BibTeX RDF
24	Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang 0001, Youguang Zhang, Dijun Liu, Ying Wang 0001, Weisheng Zhao	Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.	ICCAD	2017	DBLP DOI BibTeX RDF
24	Janibul Bashir, Smruti R. Sarangi	NUPLet: A Photonic Based Multi-Chip NUCA Architecture.	ICCD	2017	DBLP DOI BibTeX RDF
24	Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung	Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
24	Jianhua Li, Xin An, Yiming Ouyang, Wei Wang	Thread Progress Aware Block Migration for Dynamic NUCA.	PDP	2016	DBLP DOI BibTeX RDF
24	Shounak Chakraborty 0001, Shirshendu Das, Hemangee K. Kapoor	Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs.	SAC	2016	DBLP DOI BibTeX RDF
24	Ying Wang 0001, Lei Zhang 0008, Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001	Data Remapping for Static NUCA in Degradable Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
24	Shirshendu Das, Hemangee K. Kapoor	Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs.	VLSID	2015	DBLP DOI BibTeX RDF
24	Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das	An efficient searching mechanism for dynamic NUCA in chip multiprocessors.	VDAT	2015	DBLP DOI BibTeX RDF
24	Pierfrancesco Foglia, Manuel Comparetti	A workload independent energy reduction strategy for D-NUCA caches.	J. Supercomput.	2014	DBLP DOI BibTeX RDF
24	Kuei-Chung Chang, Chen-Yu Chen, Chin-Sheng Yu, Ching-Wen Chen	Supporting faulty banks in NUCA by NoC assisted remapping mechanisms.	J. Supercomput.	2014	DBLP DOI BibTeX RDF
24	Farrukh Hijaz, Omer Khan	NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
24	Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera	Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
24	Pierfrancesco Foglia, Marco Solinas	Exploiting replication to improve performances of NUCA-based CMP systems.	ACM Trans. Embed. Comput. Syst.	2014	DBLP DOI BibTeX RDF
24	Eldhose Peter, Anuj Arora, Akriti Bagaria, Smruti R. Sarangi	Optical overlay NUCA: A high speed substrate for shared L2 caches.	HiPC	2014	DBLP DOI BibTeX RDF
24	Yiqiang Ding, Wei Zhang 0002	Bounding the Worst-Case Execution Time of Static NUCA Caches.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
24	Yiqiang Ding, Wei Zhang 0002	WCET analysis of static NUCA caches.	IPCCC	2014	DBLP DOI BibTeX RDF
24	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	Author retrospective for a NUCA substrate for flexible CMP cache sharing.	ICS 25th Anniversary	2014	DBLP DOI BibTeX RDF
24	Yuang Zhang, Li Li 0003, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao	Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.	ISCAS	2014	DBLP DOI BibTeX RDF
24	Javier Lira, Carlos Molina, Ryan N. Rakvic, Antonio González 0001	Replacement techniques for dynamic NUCA cache designs on CMPs.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
24	Abbas BanaiyanMofrad, Houam Homayoun, Vasileios Kontorinis, Dean M. Tullsen, Nikil D. Dutt	REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.	IGCC	2013	DBLP DOI BibTeX RDF
24	Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera	LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
24	Kuei-Chung Chang, Ing-Ming Liao, Chiu-Han Liao	Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanisms.	J. Supercomput.	2012	DBLP DOI BibTeX RDF
24	Javier Lira, Timothy M. Jones 0001, Carlos Molina, Antonio González 0001	The migration prefetcher: Anticipating data promotion in dynamic NUCA caches.	ACM Trans. Archit. Code Optim.	2012	DBLP DOI BibTeX RDF
24	Anwen Huang, Jun Gao, Wei Guo, Wenqiang Shi, Minxuan Zhang, Jiang Jiang	PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture.	NAS	2012	DBLP DOI BibTeX RDF
24	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman	BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs.	ISLPED	2012	DBLP DOI BibTeX RDF
24	Xiaomin Jia, Jiang Jiang, Yongwen Wang, Shubo Qi, Tianlei Zhao, Guitao Fu, Minxuan Zhang	BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs.	Comput. Informatics	2011	DBLP BibTeX RDF
24	Javier Lira, Timothy M. Jones 0001, Carlos Molina, Antonio González 0001	Beforehand Migration on D-NUCA Caches.	PACT	2011	DBLP DOI BibTeX RDF
24	Asim Khan, Kyungsu Kang, Chong-Min Kyung	Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Pierfrancesco Foglia, Francesco Panicucci, Marco Solinas, Julio Sahuquillo	Energy Behaviour of NUCA Caches in CMPs.	DSD	2011	DBLP DOI BibTeX RDF
24	Yuanrui Zhang, Wei Ding 0008, Mahmut T. Kandemir, Jun Liu 0008, Ohyoung Jang	A data layout optimization framework for NUCA-based multicores.	MICRO	2011	DBLP DOI BibTeX RDF
24	Javier Lira, Carlos Molina, David M. Brooks, Antonio González 0001	Implementing a hybrid SRAM / eDRAM NUCA architecture.	HiPC	2011	DBLP DOI BibTeX RDF
24	Javier Lira, Carlos Molina, Antonio González 0001	HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors.	IPDPS	2011	DBLP DOI BibTeX RDF
24	Jongpil Jung, Kyungsu Kang, Chong-Min Kyung	Design and management of 3D-stacked NUCA cache for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
24	Manuel Comparetti	Leakage reduction alternatives for deep sub-micron D-NUCA caches.		2011	RDF
24	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Way adaptable D-NUCA caches.	Int. J. High Perform. Syst. Archit.	2010	DBLP DOI BibTeX RDF
24	Jongpil Jung, Seonpil Kim, Chong-Min Kyung	Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
24	Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni	Re-NUCA: Boosting CMP Performance Through Block Replication.	DSD	2010	DBLP DOI BibTeX RDF
24	Javier Merino, Valentin Puente, José-Ángel Gregorio	ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture.	HPCA	2010	DBLP DOI BibTeX RDF
24	Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin	T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
24	Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete	Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.	SBAC-PAD	2010	DBLP DOI BibTeX RDF
24	Ying Wang 0001, Lei Zhang 0008, Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001	Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.	PRDC	2010	DBLP DOI BibTeX RDF
24	Enric Musoll	Load balancing packets on a tile-based massive multi-core processor with S-NUCA.	ANCS	2010	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Impact of on-chip network parameters on nuca cache performances.	IET Comput. Digit. Tech.	2009	DBLP DOI BibTeX RDF
24	Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai	Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors.	PACT	2009	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	A power-efficient migration mechanism for D-NUCA caches.	DATE	2009	DBLP DOI BibTeX RDF
24	Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals	Light NUCA: A proposal for bridging the inter-cache latency gap.	DATE	2009	DBLP DOI BibTeX RDF
24	Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas	An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.	DSD	2009	DBLP DOI BibTeX RDF
24	Alberto Ros 0001, Marcelo Cintra, Manuel E. Acacio, José M. García 0001	Distance-aware round-robin mapping for large NUCA caches.	HiPC	2009	DBLP DOI BibTeX RDF
24	Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas	Analysis of Performance Dependencies in NUCA-Based CMP Systems.	SBAC-PAD	2009	DBLP DOI BibTeX RDF
24	Javier Merino, Valentin Puente, Pablo Prieto, José-Ángel Gregorio	SP-NUCA: a cost effective dynamic non-uniform cache architecture.	SIGARCH Comput. Archit. News	2008	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström	Leveraging Data Promotion for Low Power D-NUCA Caches.	DSD	2008	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.	SBAC-PAD	2008	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström	Improving power efficiency of D-NUCA caches.	SIGARCH Comput. Archit. News	2007	DBLP DOI BibTeX RDF
24	Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Analysis of static and dynamic energy consumption in NUCA caches: initial results.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
19	Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter	Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.	HPCA	2009	DBLP DOI BibTeX RDF
19	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF
19	Song Hao, Zhihui Du, David A. Bader, Man Wang	A Prediction Based CMP Cache Migration Policy.	HPCC	2008	DBLP DOI BibTeX RDF
19	Lei Jin 0002, Sangyeun Cho	Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches.	ICPP	2008	DBLP DOI BibTeX RDF
19	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu 0001, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
19	Bradford M. Beckmann, David A. Wood 0001	Managing Wire Delay in Large Chip-Multiprocessor Caches.	MICRO	2004	DBLP DOI BibTeX RDF
19	Changkyu Kim, Doug Burger, Stephen W. Keckler	Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.	IEEE Micro	2003	DBLP DOI BibTeX RDF
19	Doug Burger	Architectural versus physical solutions for on-chip communication challenges.	CODES+ISSS	2003	DBLP DOI BibTeX RDF