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article(15949) book(72) data(11) incollection(258) inproceedings(27856) phdthesis(975) proceedings(157)
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CoRR(4238) ICASSP(818) INTERSPEECH(809) CODES+ISSS(775) ALIFE(711) DAC(700) IEEE Trans. Comput. Aided Des....(668) CASES(604) LOPSTR(567) SSW(528) ICCAD(473) DATE(457) ICMC(455) CDC(419) SMACD(397) ACC(343) More (+10 of total 4355)
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Found 45278 publication records. Showing 45278 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
66Mark Genoe, Paul Vanoostende, Geert van Wauwe On the use of VHDL-based behavioral synthesis for telecom ASIC design. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
54Greg Stitt, Frank Vahid Binary synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Binary synthesis, synthesis from software binaries, FPGA, hardware/software codesign, hardware/software partitioning, configurable logic, warp processors
51Sylvain Lefebvre 0001, Hugues Hoppe Appearance-space texture synthesis. Search on Bibsonomy ACM Trans. Graph. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF RTT synthesis, anisometric synthesis, exemplar-based synthesis, feature-based synthesis, dimensionality reduction, surface textures
51John Williams, Mark J. Clement Distributed Polyphonic Music Synthesis. Search on Bibsonomy HPDC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF polyphonic music synthesis, music synthesis, distributed music synthesis, Csound music synthesis package, multiple servers, networks, music, communication protocols, distributed multimedia
48Jan Madsen, Bjarne Hald An approach to interface synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF channel optimization, client-side interface description, client/server module synthesis, communication events formalization, existing module reuse, multiple client/server environment, one-sided interface description, server interface description, software reusability, application program interfaces, client-server systems, subroutines, interface synthesis, point-to-point communication
48Ilya Issenin, Nikil D. Dutt Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF customized memory hierarchy, hierarchical TDMA buses, data reuse, multiprocessor system-on-chip, communication synthesis
47Jian Liu, Jicheng Fu, Yansheng Zhang, Farokh B. Bastani, I-Ling Yen, Ann T. Tai, Savio N. Chau Deductive Glue Code Synthesis for Embedded Software Systems Based on Code Patterns. Search on Bibsonomy ISORC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Automated code synthesis, Deductive code synthesis, Real-time system, Code patterns
45Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling
45Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
44Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
44Chih-Tung Chen, Kayhan Küçükçakar High-level scheduling model and control synthesis for a broad range of design applications. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
44H. Fatih Ugurdag, Thomas E. Fuhrman Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
44Ti-Yen Yen, Wayne H. Wolf Communication synthesis for distributed embedded systems. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF analysis algorithm, real-time systems, embedded systems, CAD, distributed processing, distributed embedded systems, interprocess communication, delay bounds, system buses, communication links, co-synthesis, synthesis algorithm, hardware-software co-synthesis
42Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya Synthesis of system-level communication by an allocation-based approach. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF allocation-based approach, high level primitives, interconnected processes, protocol selection, system-level communication synthesis, protocols, high level synthesis, systems analysis, cost function, interface synthesis, communication control
42Eike Grimpe, Frank Oppenheimer Extending the SystemC synthesis subset by object-oriented features. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF C/C++ based design, object-orientation, high-level synthesis, SystemC, system level design, hardware description language, hardware synthesis
41Ali Dasdan Efficient algorithms for debugging timing constraint violations. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
41Miodrag Potkonjak, Wayne H. Wolf Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
40Mihhail Matskin, Enn Tyugu Strategies of Structural Synthesis of Programs. Search on Bibsonomy ASE The full citation details ... 1997 DBLP  DOI  BibTeX  RDF structural program synthesis strategies, deductive program synthesis method, compositional programming, decidable logical calculus, PSPACE complexity, independent subtasks, iteration synthesis, regular data structures, heuristics, programming environments, structured programming, proof search, search efficiency
40Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja Incorporating testability considerations in high-level synthesis. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
40Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken Manufacturability and Testability Oriented Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
40Bharat P. Dave, Niraj K. Jha COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF scheduling, distributed systems, embedded systems, hierarchy, allocation, system synthesis, hardware-software co-synthesis
40Saurabh Srivastava 0001, Sumit Gulwani, Jeffrey S. Foster From program verification to program synthesis. Search on Bibsonomy POPL The full citation details ... 2010 DBLP  DOI  BibTeX  RDF proof-theoretic program synthesis, verification
40J. C. Hwang, C. W. Huang, C. T. Cheng The Development of Load Characteristics Information Network System to Improve the Estimated Efficiency of Load Synthesis in Taipower. Search on Bibsonomy ICICIC (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF load survey, load synthesis, network database, customer management
40Vijay Raghunathan, Srivaths Ravi 0001, Ganesh Lakshminarayana High-Level Synthesis with Variable-Latency Components. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
40Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
39James D. Edge, Adrian Hilton 0001, Philip J. B. Jackson Model-based synthesis of visual speech movements from 3D video. Search on Bibsonomy SIGGRAPH Posters The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Raul Camposano Behavior-Preserving Transformations for High-Level Synthesis. Search on Bibsonomy Hardware Specification, Verification and Synthesis The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
38Hirozumi Yamaguchi, Khaled El-Fakih, Gregor von Bochmann, Teruo Higashino Protocol synthesis and re-synthesis with optimal allocation of resources based on extended Petri nets. Search on Bibsonomy Distributed Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Protocol re-synthesis, Distributed system, Petri net, Service specification, Protocol specification, Protocol synthesis
37Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer Minimum-power retiming for dual-supply CMOS circuits. Search on Bibsonomy Timing Issues in the Specification and Synthesis of Digital Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF dual-supply, retiming theory, low-power, synthesis, low-power design
37Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
37Hideyuki Mizuno, Satoshi Takahashi Unit selection using k-nearest neighbor search for concatenative speech synthesis. Search on Bibsonomy IUCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF concatenative speech synthesis, synthesis unit selection, nearest neighbor search, text to speech
37Sylvain Lefebvre 0001, Hugues Hoppe Parallel controllable texture synthesis. Search on Bibsonomy ACM Trans. Graph. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Gaussian stack, coordinate jitter, data amplification, neighborhood matching, runtime content synthesis, synthesis magnification
37Byoungro So, Pedro C. Diniz, Mary W. Hall Using estimates from behavioral synthesis tools in compiler-directed design space exploration. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
37Bharat P. Dave, Niraj K. Jha CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF aperiodic task graphs, scheduling, distributed systems, embedded systems, allocation, system synthesis, hardware-software co-synthesis
37S. C. Chan, Andrew K. C. Wong Synthesis and Recognition of Sequences. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF sequences synthesis, sequences recognition, hierarchical sequence synthesis procedure, taxonomic hierarchy, unsupervised classification procedure, pattern recognition, probability, alignment, supervised classification, alphabet
36Viktor Kuncak, Mikaël Mayer, Ruzica Piskac, Philippe Suter Complete functional synthesis. Search on Bibsonomy PLDI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bapa, synthesis procedure, decision procedure, presburger arithmetic
36Jason Cong, Kirill Minkovich Optimality Study of Logic Synthesis for LUT-Based FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Bernd Finkbeiner, Sven Schewe Semi-automatic Distributed Synthesis. Search on Bibsonomy ATVA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Reinaldo A. Bergamaschi Bridging the domains of high-level and logic synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid On the efficiency of formal synthesis-experimental results. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
36Alex Orailoglu Microarchitectural synthesis for rapid BIST testing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
35Miodrag Potkonjak, Anantha P. Chandrakasan Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. Search on Bibsonomy ICIP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
35Herman Schmit, Donald E. Thomas Array mapping in behavioral synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF array grouping, array mapping, memory components, memory design space, schedule length, scheduling, data structures, memory architecture, hardware description languages, binding, behavioral synthesis, access times, design representation, hardware synthesis, synthesis tool
35Frank Vahid Procedure exlining: a transformation for improved system and behavioral synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
35P. A. Subrahmanyam What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components. Search on Bibsonomy Hardware Specification, Verification and Synthesis The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
35Mukund Sivaraman, Shail Aditya Cycle-time aware architecture synthesis of custom hardware accelerators. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF embedded hardware architecture synthesis, operator chaining, target clock period, timing during scheduling, high-level synthesis, timing analysis, delay analysis, clock frequency
33Alex Orailoglu Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
33Ahmad Abualsamid, Raed Alqadi, Parameswaran Ramanathan Distributed synthesis of real-time computer systems. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF engineering workstations, distributed synthesis, design library, processor estimation, application constraints, suitable architecture identification, application task scheduling, runtime speedup, scheduling, real-time systems, computational complexity, parallelization, CAD, distributed processing, high level synthesis, high-level synthesis, software libraries, workstation network, real-time computer systems, resource estimation, component library
33Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer Arithmetic built-in self test for high-level synthesis. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
33Steven D. Johnson Manipulating Logical Organization with System Factorizations. Search on Bibsonomy Hardware Specification, Verification and Synthesis The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
33Sumit Gulwani Dimensions in program synthesis. Search on Bibsonomy PPDP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF deductive synthesis, inductive synthesis, sat solving, smt solving, machine learning, genetic programming, programming by demonstration, belief propagation, programming by examples, probabilistic inference
33Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk High-Quality Circuit Synthesis for Modern Technologies. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
33Ganesh Ramanarayanan, Kavita Bala Constrained Texture Synthesis via Energy Minimization. Search on Bibsonomy IEEE Trans. Vis. Comput. Graph. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF detail synthesis, image analogies, Texture synthesis, super-resolution
33Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF high-level synthesis, memory synthesis
33Minjie Zhang, Chengqi Zhang Potential Cases, Methodologies, and Strategies of Synthesis of Solutions in Distributed Expert Systems. Search on Bibsonomy IEEE Trans. Knowl. Data Eng. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Distributed expert systems, synthesis of solutions, synthesis strategies, inductive methods, methodologies, analysis methods
33Oleg Golubitsky, Sean M. Falconer, Dmitri Maslov Synthesis of the optimal 4-bit reversible circuits. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF quantum computing, logic synthesis, reversible circuits
33Li-Yi Wei, Jianwei Han, Kun Zhou 0001, Hujun Bao, Baining Guo, Heung-Yeung Shum Inverse texture synthesis. Search on Bibsonomy ACM Trans. Graph. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF GPU techniques, texture mapping, texture synthesis
33Rastislav Bodík Software synthesis with sketching. Search on Bibsonomy PEPM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF synthesis
33Jason Cong, Kirill Minkovich Optimality study of logic synthesis for LUT-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
33Chuanliang Xia Analysis of Properties of Petri Synthesis Net. Search on Bibsonomy TAMC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF liveness and boundedness, Petri nets, synthesis, analysis
33Steve Zelinka, Michael Garland Jump map-based interactive texture synthesis. Search on Bibsonomy ACM Trans. Graph. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Interactive texture synthesis, jump maps, texturing surfaces
33U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF delay/cost table, hierarchical control data-flow graph, time-constrained synthesis, pipelining, reconfigurable computing, mixed integer linear programming, list scheduling
32Krishnendu Chatterjee, Thomas A. Henzinger Assume-Guarantee Synthesis. Search on Bibsonomy TACAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Orna Kupferman, Nir Piterman, Moshe Y. Vardi Safraless Compositional Synthesis. Search on Bibsonomy CAV The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Keoncheol Shin, Taewhan Kim Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Yuan Yun, Liping Wang 0001, Liwen Guan Dimensional synthesis of a 3-DOF parallel manipulator. Search on Bibsonomy SMC (6) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Áprád Furka Combinatorial synthesis on macroscopic solid support units. Search on Bibsonomy RECOMB The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya Architectural Simulation in the Context of Behavioral Synthesis. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Anand Raghunathan, Niraj K. Jha SCALP: an iterative-improvement-based low-power data path synthesis system. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
31Steffen Peter, Tony Givargis Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Wei Hu 0008, Armaiti Ardeshiricham, Lingjuan Wu, Ryan Kastner Integrating Information Flow Tracking into High-Level Synthesis Design Flow. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Sheikh Ariful Islam, Srinivas Katkoori Behavioral Synthesis of Key-Obfuscated RTL IP. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Anirban Sengupta, Mahendra Rathor Hardware (IP) Watermarking During Behavioral Synthesis. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen High-Level Synthesis for Minimizing Power Side-Channel Information Leakage. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Christian Pilato, Donatella Sciuto, Francesco Regazzoni 0001, Siddharth Garg, Ramesh Karri Protecting Hardware IP Cores During High-Level Synthesis. Search on Bibsonomy Behavioral Synthesis for Hardware Security The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Ernst-Rüdiger Olderog, Bernhard Steffen, Wang Yi 0001 Model Checking, Synthesis, and Learning. Search on Bibsonomy Model Checking, Synthesis, and Learning The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
31André Inácio Reis, Jody M. A. Matos Physical Awareness Starting at Technology-Independent Logic Synthesis. Search on Bibsonomy Advanced Logic Synthesis The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
31Leon Stok EDA3.0: Implications to Logic Synthesis. Search on Bibsonomy Advanced Logic Synthesis The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
31Bijoy Antony Jose, Sandeep K. Shukla MRICDF: A Polychronous Model for Embedded Software Synthesis. Search on Bibsonomy Synthesis of Embedded Software The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Sven Schewe Software Synthesis is Hard - and Simple. Search on Bibsonomy Software Synthesis The full citation details ... 2009 DBLP  BibTeX  RDF
31Rastislav Bodík, Orna Kupferman, Douglas R. Smith, Eran Yahav 09501 Abstracts Collection - Software Synthesis. Search on Bibsonomy Software Synthesis The full citation details ... 2009 DBLP  BibTeX  RDF
31Luc De Raedt, Thomas G. Dietterich, Lise Getoor, Kristian Kersting, Stephen H. Muggleton 07161 Abstracts Collection -- Probabilistic, Logical and Relational Learning - A Further Synthesis. Search on Bibsonomy Probabilistic, Logical and Relational Learning - A Further Synthesis The full citation details ... 2007 DBLP  BibTeX  RDF
31Henry A. Kautz, Wolfgang Thomas, Moshe Y. Vardi 05241 Abstracts Collection - Synthesis and Planning. Search on Bibsonomy Synthesis and Planning The full citation details ... 2005 DBLP  BibTeX  RDF
31Henry A. Kautz, Wolfgang Thomas, Moshe Y. Vardi 05241 Executive Summary - Synthesis and Planning. Search on Bibsonomy Synthesis and Planning The full citation details ... 2005 DBLP  BibTeX  RDF
31E. T. Kapuya, M. D. Edwards Microarchitecture/Microcode Synthesis from VHDL. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer Data Part Optimizations in the CALLAS Synthesis Environment. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven Module Generation in an Architectural Synthesis Environment. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31James Pardey The Synthesis of a Parallel Controller from a Petri Net Model. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Inhag Park, Kevin O'Brien, Ahmed Amine Jerraya AMICAL: Architectural Synthesis based on VHDL. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Andreas Münzner BADGE - A synthesis tool for customized arithmetic building blocks. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier Specification and Synthesis of Communicating Finite State Machines. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff RTL Controller Synthesis. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Laurent Gerbaux, Régis Leveugle, Gabriele Saucier Synthesis of large controllers using ROM or PLA generators. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Peter Marwedel Implementations of IF-statements in the TODOS microarchitecture synthesis system. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson 0001 Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier ASYL: A Control Driven RTL Synthesis System using Library Blocks. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Pierre Abouzeid, Régis Leveugle, Gabriele Saucier Logic Synthesis for Automatic Layout. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Farhad Mavaddat Data-Path Synthesis as Grammar Inference. Search on Bibsonomy Synthesis for Control Dominated Circuits The full citation details ... 1992 DBLP  BibTeX  RDF
31Geoffrey M. Brown, Miriam Leeser From Programs to Transistors: Verifying Hardware Synthesis Tools. Search on Bibsonomy Hardware Specification, Verification and Synthesis The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
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