Search results for "reduced-area"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
32	K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.	Parallel reduced area multipliers.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
23	Hussein M. Alnuweiri	A New Class of Optimal Bounded-Degree VLSI Sorting Networks.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	VLSI sorting networks, optimal VLSI sorters, rotate-sort, enumeration-sort, reduced-area, K-shuffle layouts, VLSI, optimisation, logic design, sorting, time complexity, bounded-degree
21	Savvas Koudounas, Julius Georgiou	A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Ahmad A. Hiasat	High-Speed and Reduced-Area Modular Adder Structures for RNS.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder
16	Timothy Sherwood, Brad Calder	Patchable instruction ROM architecture.	CASES	2001	DBLP DOI BibTeX RDF
14	Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic	Application specific forwarding network and instruction encoding for multi-pipe ASIPs.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-pipe ASIP, VLIW, forwarding, instruction encoding
14	Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel	Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME.	SBCCI	2023	DBLP DOI BibTeX RDF
14	Mohsen A. M. El-Bendary, M. Ayman	Efficient Multiple 4-Bit ALU Designs for Fast Computation and Reduced Area.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
14	Abhishek Bhat, Nagendra Krishnapura	A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
14	Xiaowei Deng, Yunchen Qiu, David Toops, George Jamison	A Trim Bit One Time Programmable EPROM with Aggressively Reduced Area, Enhanced Functionality, and Extra Features.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Muhammad Mazher Iqbal, Husain Parvez, Fasahat Hussain, Muhammad Rashid	An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
14	R. Saravana Ram, M. Lordwin Cecil Prabhaker, K. Suresh, Kamalraj Subramaniam, M. Venkatesan	Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
14	Karim Ali 0004, Fei Li 0015, Sunny Y. H. Lua, Chun-Huat Heng	Energy Efficient Reduced Area Overhead Spin-Orbit Torque Non-Volatile SRAMs.	IECON	2020	DBLP DOI BibTeX RDF
14	Tongxin Yang, Toshinori Sato, Tomoaki Ukezono	An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area.	ISVLSI	2019	DBLP DOI BibTeX RDF
14	Arindam Banerjee 0003, Debesh Kumar Das	A New Squarer design with reduced area and delay.	IET Comput. Digit. Tech.	2016	DBLP DOI BibTeX RDF
14	Arindam Banerjee 0003, Debesh Kumar Das	Squarer design with reduced area and delay.	VDAT	2015	DBLP DOI BibTeX RDF
14	Hirotaka Kawashima, Naofumi Takagi	Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers.	IPSJ Trans. Syst. LSI Des. Methodol.	2011	DBLP DOI BibTeX RDF
14	Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov	Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.	HLDVT	2011	DBLP DOI BibTeX RDF
14	Padma Devi, Gurinder Pal Singh, Balwinder Singh	Low Power Optimized Array Multiplier with Reduced Area.	HPAGC	2011	DBLP DOI BibTeX RDF
14	Amir Sabbagh Molahosseini, M. Kuchaki Rafsanjani, S. H. Ghafouri, M. Hashemipour	A Reduced-Area Reverse Converter for the Moduli Set {2n, 2n-1, 22n-1-1}.	Int. J. Adv. Comp. Techn.	2010	DBLP BibTeX RDF
14	Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan	A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.	ISQED	2010	DBLP DOI BibTeX RDF
14	Tuhin Subhra Chakraborty, Saswat Chakrabarti	A reduced area 1 GSPS FFT design using MRMDF architecture for UWB communication.	APCCAS	2008	DBLP DOI BibTeX RDF
14	H. Souffi-Kebbati, Jean-Philippe Blonde, Francis Braun	A new semi-flat architecture for high speed and reduced area CORDIC chip.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
14	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format	CoRR	2006	DBLP BibTeX RDF
14	Biplab K. Sikdar, Samir Roy, Debesh K. Das	A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, reachability, degree-of-freedom
14	Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe	Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	DDFS, NCO, direct digital frequency synthesizer, numerically controlled oscillator, phase accumulator, low power
14	Youngjoon Kim, Lee-Sup Kim	A low power carry select adder with reduced area.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
14	Trudi-Heleen Joubert, Evert Seevinck, Monuko du Plessis	A CMOS reduced-area SRAM cell.	ISCAS	2000	DBLP DOI BibTeX RDF
14	Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund	A reduced-area low-power low-voltage single-ended differential pair.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
14	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
14	Nur A. Touba, Edward J. McCluskey	Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection.	ICCAD	1994	DBLP DOI BibTeX RDF
14	K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.	Reduced area multipliers.	ASAP	1993	DBLP DOI BibTeX RDF
14	Christos A. Papachristou, Anil L. Pandya	A design scheme for PLA-based control tables with reduced area and time-delay cost.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
14	Akhilesh Tyagi	A reduced area scheme for carry-select adders.	ICCD	1990	DBLP DOI BibTeX RDF
11	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
10	Marco Ottavi, Vamsi Vankamamidi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano	Design of a QCA Memory with Parallel Read/Serial Write.	ISVLSI	2005	DBLP DOI BibTeX RDF
9	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
9	Amir Zjajo, Mingxin Song	A low-power digitally-programmable variable gain amplifier in 65 nm CMOS.	ISLPED	2010	DBLP DOI BibTeX RDF	dicrete-time amplifier, variable gain amplifier, waveform generator
9	Sudhakar Maddi, M. B. Srinivas	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.	SBCCI	2007	DBLP DOI BibTeX RDF	sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
9	Peter R. Wilson, Reuben Wilcock	Behavioural modeling and simulation of a switched-current phase locked loop.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
9	B. Suresh, Biswadeep Chaterjee, R. Harinath	Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability
8	George Economakos, Kostas Anagnostopoulos	Bit level architectural exploration technique for the design of low power multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Rakesh Kumar 0002, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
8	Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel	Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
7	Elias Teodoro Silva Jr., Marco A. Wehrmeister, Flávio Rech Wagner, Carlos Eduardo Pereira	An approach to improve predictability in communication services in distributed real-time embedded systems.	JTRES	2007	DBLP DOI BibTeX RDF	real-time systems, energy efficiency, embedded applications, networked embedded systems
7	David Marche, Yves Gagnon, Yvon Savaria	. A new switch compensation technique for inverted R-2R ladder DACs.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
6	Pushpa Kumar, Kang Zhang 0001	Visualization of clustered directed acyclic graphs with node interleaving.	SAC	2009	DBLP DOI BibTeX RDF	node interleaving, overlapping nodes, visualization, graph drawing, directed acyclic graphs
6	Khan A. Wahid, Seok-Bum Ko, Daniel Teng	Efficient hardware implementation of an image compressor for wireless capsule endoscopy applications.	IJCNN	2008	DBLP DOI BibTeX RDF
6	Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron	Applications of Small-Scale Reconfigurability to Graphics Processors.	ARC	2006	DBLP DOI BibTeX RDF
6	José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera	High-Speed Function Approximation Using a Minimax Quadratic Interpolator.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Table-based methods, minimax polynomial approximation, single-precision computations, computer arithmetic, square root, reciprocal, elementary functions
6	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
6	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw	A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.	CASES	2005	DBLP DOI BibTeX RDF	sensor network, energy efficiency, microprocessor, memory organization
6	Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003	Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform.	Soft Comput.	2004	DBLP DOI BibTeX RDF	Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware
6	Jorge R. Fernandes, Manuel Medeiros Silva	A very low-power CMOS parallel A/D converter for embedded applications.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
6	Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne	Metric Definition for Circuit Speed Optimization.	PATMOS	2003	DBLP DOI BibTeX RDF
6	G. Harling	A DRAM Compiler for Fully Optimized Memory Instances.	MTDT	2001	DBLP DOI BibTeX RDF
6	Christopher T. Weaver, Rajeev Krishna, Lisa Wu 0001, Todd M. Austin	Application specific architectures: a recipe for fast, flexible and power efficient designs.	CASES	2001	DBLP DOI BibTeX RDF
6	Ben I. Hounsell, Tughrul Arslan	Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform .	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
6	Gauthier Lafruit, Francky Catthoor, Jan Cornelis 0001, Hugo De Man	An efficient VLSI architecture for 2-D wavelet image coding with novel image scan.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
6	P. C. Shah, Hosaker N. Mahabala	A New Compaction Scheme Based on Compression Ridges.	DAC	1987	DBLP DOI BibTeX RDF
4	Cláudio Sapateiro, Nelson Baloian, Pedro Antunes 0001, Gustavo Zurita	Developing collaborative peer-to-peer applications on mobile devices.	CSCWD	2009	DBLP DOI BibTeX RDF
4	Tomás Lang, Alberto Nannarelli	Division Unit for Binary Integer Decimals.	ASAP	2009	DBLP DOI BibTeX RDF
4	Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki	Transistor-level based defect tolerance for reliable nanoelectronics.	AICCSA	2008	DBLP DOI BibTeX RDF
4	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.	NOCS	2007	DBLP DOI BibTeX RDF
4	Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro	On the design of very small transconductance OTAs with reduced input offset.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, CMOS, analog design
4	Sebastián López, Félix Tobajas, A. Villar, V. de Armas, José Francisco López, Roberto Sarmiento	Low cost efficient architecture for H.264 motion estimation.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
4	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod	Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	digital signal processing (DSP) systems, electromagnetic interference (EMI), speech recognition system (SRS), on-line testing, noise immunity
4	A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky	A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.	IOLTS	2004	DBLP DOI BibTeX RDF
4	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri	An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.	DFT	2004	DBLP DOI BibTeX RDF
4	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for In-Field SOC Test.	DFT	2004	DBLP DOI BibTeX RDF
4	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	speech-recognition systems (SRS), digital signal processing (DSP), on-line testing, performance degradation, noise immunity, area overhead, recovery blocks
4	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum	Briefing a New Approach to Improve the EMI Immunity of DSP Systems.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Digital Signal Processing (DSP) Systems, Electromagnetic Interference (EMI), On-Line Testing, Noise Immunity
4	Eric Keller, Gordon J. Brebner, Philip James-Roxby	Software Decelerators.	FPL	2003	DBLP DOI BibTeX RDF
4	Massimo Conti, Paolo Crippa, Francesco Fedecostunte, Simone Orcioni, F. Ricciardi, Claudio Turchetti, Loris Vendrame	A modular test structure for CMOS mismatch characterization.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
4	Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	High Speed Ring Generators and Compactors of Test Data.	VTS	2003	DBLP DOI BibTeX RDF
4	Ahmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi	A Low Power High Performance Distributed DCT Architecture.	ISVLSI	2002	DBLP DOI BibTeX RDF	Distributed Arithmetic (DA), Multiply and Accumulate unit (MAC), multiplier-free solution, power/area efficient VLSI design, discrete cosine transform (DCT)
4	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity
4	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
4	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
4	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), analog and mixed-signal testing, ADC test
4	Ismet Bayraktaroglu, Alex Orailoglu	Accumulation-based concurrent fault detection for linear digital state variable systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	concurrent fault detection, linear digital state variable systems, algorithmic fault detection scheme, accumulation-based approach, fault diagnosis, logic testing, error detection, error detection, linear systems, digital filters, digital signal processing chips, digital systems, area overhead
4	Mohammad A. Naal, Emmanuel Simeu	High-Level Synthesis Methodology for On-Line Testability Optimization.	IOLTW	2000	DBLP DOI BibTeX RDF	On-line testability, Function factorization, idle-time operation, High-level synthesis
4	Elisenda Roca, Servando Espejo-Meana, Rafael Domínguez-Castro, Gustavo Liñán, Ángel Rodríguez-Vázquez	A Programmable Imager for Very High Speed Cellular Signal Processing.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
4	Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham	Design For Testability Method for CML Digital Circuits.	DATE	1999	DBLP DOI BibTeX RDF
4	Charu C. Aggarwal, Joel L. Wolf, Philip S. Yu, Marina A. Epelman	The S-Tree: An Efficient Index for Multidimensional Objects.	SSD	1997	DBLP DOI BibTeX RDF
4	Tudor Jebelean	Design of a systolic coprocessor for rational addition.	ASAP	1995	DBLP DOI BibTeX RDF	systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD
4	Subhrajit Bhattacharya, Franc Brglez, Sujit Dey	Transformations and resynthesis for testability of RT-level control-data path specifications.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF