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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 104 occurrences of 89 keywords
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Results
Found 88 publication records. Showing 88 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Akhilesh Tyagi |
A Reduced-Area Scheme for Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1163-1170, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders |
32 | K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. |
Parallel reduced area multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 9(3), pp. 181-191, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Hussein M. Alnuweiri |
A New Class of Optimal Bounded-Degree VLSI Sorting Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(6), pp. 746-752, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
VLSI sorting networks, optimal VLSI sorters, rotate-sort, enumeration-sort, reduced-area, K-shuffle layouts, VLSI, optimisation, logic design, sorting, time complexity, bounded-degree |
21 | Savvas Koudounas, Julius Georgiou |
A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3832-3835, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Ahmad A. Hiasat |
High-Speed and Reduced-Area Modular Adder Structures for RNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(1), pp. 84-89, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder |
16 | Timothy Sherwood, Brad Calder |
Patchable instruction ROM architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 24-33, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 241-246, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
14 | Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel |
Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1834-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Mohsen A. M. El-Bendary, M. Ayman |
Efficient Multiple 4-Bit ALU Designs for Fast Computation and Reduced Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(8), pp. 4671-4691, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Abhishek Bhat, Nagendra Krishnapura |
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(1), pp. 160-171, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Xiaowei Deng, Yunchen Qiu, David Toops, George Jamison |
A Trim Bit One Time Programmable EPROM with Aggressively Reduced Area, Enhanced Functionality, and Extra Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 1467-1471, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Muhammad Mazher Iqbal, Husain Parvez, Fasahat Hussain, Muhammad Rashid |
An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(4), pp. 2150065:1-2150065:24, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | R. Saravana Ram, M. Lordwin Cecil Prabhaker, K. Suresh, Kamalraj Subramaniam, M. Venkatesan |
Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 76, pp. 103088, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Karim Ali 0004, Fei Li 0015, Sunny Y. H. Lua, Chun-Huat Heng |
Energy Efficient Reduced Area Overhead Spin-Orbit Torque Non-Volatile SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: The 46th Annual Conference of the IEEE Industrial Electronics Society, IECON 2020, Singapore, October 18-21, 2020, pp. 2275-2280, 2020, IEEE, 978-1-7281-5414-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Tongxin Yang, Toshinori Sato, Tomoaki Ukezono |
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pp. 385-390, 2019, IEEE, 978-1-7281-3391-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Arindam Banerjee 0003, Debesh Kumar Das |
A New Squarer design with reduced area and delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 10(5), pp. 205-214, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Arindam Banerjee 0003, Debesh Kumar Das |
Squarer design with reduced area and delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Hirotaka Kawashima, Naofumi Takagi |
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 4, pp. 131-139, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov |
Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011, pp. 92-97, 2011, IEEE Computer Society, 978-1-4577-1744-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Padma Devi, Gurinder Pal Singh, Balwinder Singh |
Low Power Optimized Array Multiplier with Reduced Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPAGC ![In: High Performance Architecture and Grid Computing - International Conference, HPAGC 2011, Chandigarh, India, July 19-20, 2011. Proceedings, pp. 224-232, 2011, Springer, 978-3-642-22576-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Amir Sabbagh Molahosseini, M. Kuchaki Rafsanjani, S. H. Ghafouri, M. Hashemipour |
A Reduced-Area Reverse Converter for the Moduli Set {2n, 2n-1, 22n-1-1}. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Adv. Comp. Techn. ![In: Int. J. Adv. Comp. Techn. 2(5), pp. 61-65, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
14 | Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan |
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 131-138, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Tuhin Subhra Chakraborty, Saswat Chakrabarti |
A reduced area 1 GSPS FFT design using MRMDF architecture for UWB communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1128-1131, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | H. Souffi-Kebbati, Jean-Philippe Blonde, Francis Braun |
A new semi-flat architecture for high speed and reduced area CORDIC chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 37(2), pp. 181-187, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas |
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/cs/0609036, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
14 | Biplab K. Sikdar, Samir Roy, Debesh K. Das |
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 83-93, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
emitability, FSM state encoding, reachability, degree-of-freedom |
14 | Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe |
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 249-252, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DDFS, NCO, direct digital frequency synthesizer, numerically controlled oscillator, phase accumulator, low power |
14 | Youngjoon Kim, Lee-Sup Kim |
A low power carry select adder with reduced area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 218-221, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Trudi-Heleen Joubert, Evert Seevinck, Monuko du Plessis |
A CMOS reduced-area SRAM cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 335-338, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund |
A reduced-area low-power low-voltage single-ended differential pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(2), pp. 254-257, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Subhrajit Bhattacharya, Sujit Dey |
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 74-80, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology |
14 | Nur A. Touba, Edward J. McCluskey |
Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 651-654, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
14 | K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. |
Reduced area multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 478-489, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
14 | Christos A. Papachristou, Anil L. Pandya |
A design scheme for PLA-based control tables with reduced area and time-delay cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5), pp. 453-472, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Akhilesh Tyagi |
A reduced area scheme for carry-select adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990, pp. 255-258, 1990, IEEE Computer Society, 0-8186-2079-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | Betul Buyukkurt, Zhi Guo, Walid A. Najjar |
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 401-412, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Marco Ottavi, Vamsi Vankamamidi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano |
Design of a QCA Memory with Parallel Read/Serial Write. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 292-294, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 62-67, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
9 | Amir Zjajo, Mingxin Song |
A low-power digitally-programmable variable gain amplifier in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 105-110, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dicrete-time amplifier, variable gain amplifier, waveform generator |
9 | Sudhakar Maddi, M. B. Srinivas |
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 147-152, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures |
9 | Peter R. Wilson, Reuben Wilcock |
Behavioural modeling and simulation of a switched-current phase locked loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5174-5177, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | B. Suresh, Biswadeep Chaterjee, R. Harinath |
Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 512-517, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability |
8 | George Economakos, Kostas Anagnostopoulos |
Bit level architectural exploration technique for the design of low power multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Rakesh Kumar 0002, Norman P. Jouppi, Dean M. Tullsen |
Conjoined-Core Chip Multiprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 195-206, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel |
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 31-36, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Elias Teodoro Silva Jr., Marco A. Wehrmeister, Flávio Rech Wagner, Carlos Eduardo Pereira |
An approach to improve predictability in communication services in distributed real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, JTRES 2007, Institute of Computer Engineering, Vienna University of Technology, 26-28 September 2007, Vienna, Austria, pp. 121-126, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
real-time systems, energy efficiency, embedded applications, networked embedded systems |
7 | David Marche, Yves Gagnon, Yvon Savaria |
. A new switch compensation technique for inverted R-2R ladder DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 196-199, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
6 | Pushpa Kumar, Kang Zhang 0001 |
Visualization of clustered directed acyclic graphs with node interleaving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), Honolulu, Hawaii, USA, March 9-12, 2009, pp. 1800-1805, 2009, ACM, 978-1-60558-166-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
node interleaving, overlapping nodes, visualization, graph drawing, directed acyclic graphs |
6 | Khan A. Wahid, Seok-Bum Ko, Daniel Teng |
Efficient hardware implementation of an image compressor for wireless capsule endoscopy applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 2761-2765, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
6 | Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron |
Applications of Small-Scale Reconfigurability to Graphics Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 99-108, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
6 | José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera |
High-Speed Function Approximation Using a Minimax Quadratic Interpolator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 304-318, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Table-based methods, minimax polynomial approximation, single-precision computations, computer arithmetic, square root, reciprocal, elementary functions |
6 | Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel |
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 76-81, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
6 | Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw |
A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 249-256, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sensor network, energy efficiency, microprocessor, memory organization |
6 | Ben I. Hounsell, Tughrul Arslan, Robert Thomson 0003 |
Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 8(5), pp. 307-317, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Robust hardware, Finite impulse response filters, Genetic algorithms, Fault tolerant, Programmable logic arrays, PLAs, FIR filters, Evolvable hardware |
6 | Jorge R. Fernandes, Manuel Medeiros Silva |
A very low-power CMOS parallel A/D converter for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 1056-1059, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
6 | Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne |
Metric Definition for Circuit Speed Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 451-460, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
6 | G. Harling |
A DRAM Compiler for Fully Optimized Memory Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 3-8, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Christopher T. Weaver, Rajeev Krishna, Lisa Wu 0001, Todd M. Austin |
Application specific architectures: a recipe for fast, flexible and power efficient designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 181-185, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Ben I. Hounsell, Tughrul Arslan |
Evolutionary Design And Adaptation Of Digital Filters Within An Embedded Fault Tolerant Hardware Platform . ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 12-14 July 2001, Long Beach, CA, USA, pp. 127-135, 2001, IEEE Computer Society, 0-7695-1180-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Gauthier Lafruit, Francky Catthoor, Jan Cornelis 0001, Hugo De Man |
An efficient VLSI architecture for 2-D wavelet image coding with novel image scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(1), pp. 56-68, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
6 | P. C. Shah, Hosaker N. Mahabala |
A New Compaction Scheme Based on Compression Ridges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 645-648, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
4 | Cláudio Sapateiro, Nelson Baloian, Pedro Antunes 0001, Gustavo Zurita |
Developing collaborative peer-to-peer applications on mobile devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 13th International Conference on Computers Supported Cooperative Work in Design, CSCWD 2009, April 22-24, 2009, Santiago, Chile, pp. 396-401, 2009, IEEE, 978-1-4244-3534-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
4 | Tomás Lang, Alberto Nannarelli |
Division Unit for Binary Integer Decimals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 1-7, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
4 | Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki |
Transistor-level based defect tolerance for reliable nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 6th ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2008, Doha, Qatar, March 31 - April 4, 2008, pp. 53-60, 2008, IEEE Computer Society, 978-1-4244-1967-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
4 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 173-182, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
4 | Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro |
On the design of very small transconductance OTAs with reduced input offset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 15-20, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low-power, CMOS, analog design |
4 | Sebastián López, Félix Tobajas, A. Villar, V. de Armas, José Francisco López, Roberto Sarmiento |
Low cost efficient architecture for H.264 motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 412-415, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
4 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod |
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 397-411, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
digital signal processing (DSP) systems, electromagnetic interference (EMI), speech recognition system (SRS), on-line testing, noise immunity |
4 | A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky |
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 52-57, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri |
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 130-138, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an I-IP for In-Field SOC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 404-412, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr. |
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(1), pp. 61-72, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
speech-recognition systems (SRS), digital signal processing (DSP), on-line testing, performance degradation, noise immunity, area overhead, recovery blocks |
4 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum |
Briefing a New Approach to Improve the EMI Immunity of DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 468-473, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Digital Signal Processing (DSP) Systems, Electromagnetic Interference (EMI), On-Line Testing, Noise Immunity |
4 | Eric Keller, Gordon J. Brebner, Philip James-Roxby |
Software Decelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 385-395, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
4 | Massimo Conti, Paolo Crippa, Francesco Fedecostunte, Simone Orcioni, F. Ricciardi, Claudio Turchetti, Loris Vendrame |
A modular test structure for CMOS mismatch characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 569-572, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
4 | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
High Speed Ring Generators and Compactors of Test Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 57-62, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
4 | Ahmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi |
A Low Power High Performance Distributed DCT Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 26-34, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Distributed Arithmetic (DA), Multiply and Accumulate unit (MAC), multiplier-free solution, power/area efficient VLSI design, discrete cosine transform (DCT) |
4 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr. |
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 224-229, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity |
4 | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López |
Low depth carry lookahead addition using charge recycling threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 469-472, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
4 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr. |
A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 187, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
4 | Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell |
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 255-266, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Built-In Self-Test (BIST), analog and mixed-signal testing, ADC test |
4 | Ismet Bayraktaroglu, Alex Orailoglu |
Accumulation-based concurrent fault detection for linear digital state variable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 484-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
concurrent fault detection, linear digital state variable systems, algorithmic fault detection scheme, accumulation-based approach, fault diagnosis, logic testing, error detection, error detection, linear systems, digital filters, digital signal processing chips, digital systems, area overhead |
4 | Mohammad A. Naal, Emmanuel Simeu |
High-Level Synthesis Methodology for On-Line Testability Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 201-206, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
On-line testability, Function factorization, idle-time operation, High-level synthesis |
4 | Elisenda Roca, Servando Espejo-Meana, Rafael Domínguez-Castro, Gustavo Liñán, Ángel Rodríguez-Vázquez |
A Programmable Imager for Very High Speed Cellular Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 23(2-3), pp. 305-318, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
4 | Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham |
Design For Testability Method for CML Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 360-367, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
4 | Charu C. Aggarwal, Joel L. Wolf, Philip S. Yu, Marina A. Epelman |
The S-Tree: An Efficient Index for Multidimensional Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: Advances in Spatial Databases, 5th International Symposium, SSD'97, Berlin, Germany, July 15-18, 1997, Proceedings, pp. 350-373, 1997, Springer, 3-540-63238-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
4 | Tudor Jebelean |
Design of a systolic coprocessor for rational addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 282-289, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD |
4 | Subhrajit Bhattacharya, Franc Brglez, Sujit Dey |
Transformations and resynthesis for testability of RT-level control-data path specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(3), pp. 304-318, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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