Search results for "repeater"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
205	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	Practical repeater insertion for low power: what repeater library do we need?	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
202	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	Practical repeater insertion for low power: what repeater library do we need?	DAC	2004	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion
139	Yuantao Peng, Xun Liu	An Efficient Low-Power Repeater-Insertion Scheme.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
102	Charbel J. Akl, Magdy A. Bayoumi	Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
102	Srividya Srinivasaraghavan, Wayne P. Burleson	Interconnect Effort - A Unification of Repeater Insertion and Logical Effort.	ISVLSI	2003	DBLP DOI BibTeX RDF
96	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Fast buffering for optimizing worst slack and resource consumption in repeater trees.	ISPD	2009	DBLP DOI BibTeX RDF	interconnect buffering, repeater tree, physical design, repeater insertion, timing closure
87	Charbel J. Akl, Magdy A. Bayoumi	Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	high-speed signaling, repeater, wires
87	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
87	Hui-shin Chae, Kye-san Lee, Jae Sang Cha	An Adaptive Repeater System for OFDM with Frequency Hopping Control to Reduce the Interference.	KES (1)	2005	DBLP DOI BibTeX RDF	Repeater System, ISI (Inter Symbol Interference), Frequency Hopping Controller
87	Yuantao Peng, Xun Liu	A sensitivity analysis of low-power repeater insertion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, sensitivity, repeater insertion
87	Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar	Net weighting to reduce repeater counts during placement.	DAC	2005	DBLP DOI BibTeX RDF	interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting
78	Nikolai Ryzhenko, Oleg Venger	A practical repeater insertion flow.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, buffer insertion, fanout optimization, topology generation
78	Jakub Borkowski, Jarno Niemelä, Tero Isotalo, Panu Lähdekorpi, Jukka Lempiäinen	Utilization of an Indoor DAS for Repeater Deployment in WCDMA.	VTC Spring	2006	DBLP DOI BibTeX RDF
78	Srinivasa R. Sridhara, Naresh R. Shanbhag	A low-power bus design using joint repeater insertion and coding.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, coding, crosstalk, repeaters
78	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Repeater insertion in tree structured inductive interconnect.	ICCAD	1999	DBLP DOI BibTeX RDF
75	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Efficient generation of short and fast repeater tree topologies.	ISPD	2006	DBLP DOI BibTeX RDF	inverter tree, repeater tree, buffering, tree topology, rectilinear Steiner tree
75	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors	Accounting for the skin effect during repeater insertion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	buffer design, optimization, delay, power, repeater insertion, skin effect
75	Yuantao Peng, Xun Liu	Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method.	DAC	2005	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion
75	Yuantao Peng, Xun Liu	Power macromodeling of global interconnects considering practical repeater insertion.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, interconnect, macromodeling, repeater insertion
75	Dinesh Pamunuwa, Hannu Tenhunen	On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects.	ISQED	2002	DBLP DOI BibTeX RDF	Cross-talk, Delay minimisation, Static timing, Repeater insertion, Deep sub-micron
72	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.	SLIP	2006	DBLP DOI BibTeX RDF	delay-balanced, minimal-power, interconnects, repeaters
66	Yuantao Peng, Xun Liu	RITC: Repeater Insertion with Timing Target Compensation.	ISVLSI	2005	DBLP DOI BibTeX RDF
66	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power.	DATE	2005	DBLP DOI BibTeX RDF
66	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
66	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
66	Probir Sarkar, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centricfloorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
66	Yehea I. Ismail, Eby G. Friedman	Repeater insertion in RLC lines for minimum propagation delay.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
63	Longfei Shi, XueSong Wang 0003, Shunping Xiao	Polarization discrimination between repeater false-target and radar target.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	repeater false-target, discrimination, polarization
63	XueSong Wang, JianCheng Liu, Wenming Zhang, QiXiang Fu, Zhong Liu, XiaoXia Xie	Mathematic principles of interrupted-sampling repeater jamming (ISRJ).	Sci. China Ser. F Inf. Sci.	2007	DBLP DOI BibTeX RDF	interrupted-sampling, repeater jamming, ambiguity function, pulse compression, linear frequency modulated signal
63	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
63	Ja Chun Ku, Yehea I. Ismail	Thermal-aware methodology for repeater insertion in low-power VLSI circuits.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
63	W. T. Cheung, N. Wong	Power optimization in a repeater-inserted interconnect via geometric programming.	ISLPED	2006	DBLP DOI BibTeX RDF	optimization, interconnect, power, repeater, geometric programming
60	Mart L. Molle, Boaz Yeger	Reducing the Effects of Large Propagation Delays on High Speed IEEE 802.3 CSMA/CD Networks using Collision Truncation.	LCN	1997	DBLP DOI BibTeX RDF
54	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
54	Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai	Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
54	Naohiko Uramoto, Hiroshi Maruyama	InfoBus Repeater: A Secure and Distributed Publish/Subscribe Middleware.	ICPP Workshops	1999	DBLP DOI BibTeX RDF
54	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
51	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
48	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters in bidirectional buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
45	Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose	Thermal-aware task scheduling at the system software level.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
45	Pathma Rathinavelu, Gottfried Schapeler, Andreas Weber 0003	UMTS Coverage and Capacity Enhancement Using Repeaters and Remote RF Heads.	AINA (2)	2006	DBLP DOI BibTeX RDF	UMTS network, coverage and capacity enhancement, remote RF head, repeater
45	Prashant Saxena, Bill Halpin	Modeling repeaters explicitly within analytical placement.	DAC	2004	DBLP DOI BibTeX RDF	interconnect, placement, scaling, buffering, repeater insertion, force-directed placement, analytical placement
45	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
45	P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
42	Yisheng Xue	Amplify-and-forward repeater enhanced random access in single-cell wireless communications.	PIMRC	2008	DBLP DOI BibTeX RDF
42	Himanshu Kaul, Jae-sun Seo, Mark A. Anders 0001, Dennis Sylvester, Ram Krishnamurthy 0001	A robust alternate repeater technique for high performance busses in the multi-core era.	ISCAS	2008	DBLP DOI BibTeX RDF
42	Ja Chun Ku, Yehea I. Ismail	Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
42	Krishnamoorthy Natarajan, S. J. Nagalakshmi	Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach.	CCECE	2006	DBLP DOI BibTeX RDF
42	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick	Repeater scaling and its impact on CAD.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
42	Weiping Liao, Lei He 0001	Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.	ICCAD	2003	DBLP DOI BibTeX RDF
42	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
42	P. Kaewplung, P. Thipchatchawanwong	Performance improvement of 40 Gbit/s optical soliton transmission system by employing all-optically regenerative repeater using nonlinear optical loop mirror.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
42	Dinesh Pamunuwa, Hannu Tenhunen	Repeater Insertion To Minimise Delay In Coupled Interconnects.	VLSI Design	2001	DBLP DOI BibTeX RDF
42	Yehea I. Ismail, Eby G. Friedman	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
42	I-Min Liu, Adnan Aziz, D. F. Wong 0001	Meeting Delay Constraints in DSM by Minimal Repeater Insertion.	DATE	2000	DBLP DOI BibTeX RDF
42	Julian Culetu, Chaim Amir, John MacDonald	A Practical Repeater Insertion Method in High Speed VLSI Circuits.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
39	Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
36	Miao Qingyu, Afif Osseiran	Performance Comparison Between DF relay and RF Repeaters in the Cellular System.	VTC Spring	2008	DBLP DOI BibTeX RDF
36	Paramvir Bahl, Ranveer Chandra, Patrick P. C. Lee, Vishal Misra, Jitendra Padhye, Dan Rubenstein, Yan Yu	Opportunistic use of client repeaters to improve performance of WLANs.	CoNEXT	2008	DBLP DOI BibTeX RDF
36	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
36	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
36	Charbel J. Akl, Magdy A. Bayoumi	Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
36	Jinwook Jang, Sheng Xu, Wayne P. Burleson	Jitter in Deep Sub-Micron Interconnect.	ISVLSI	2005	DBLP DOI BibTeX RDF
36	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif	Power-aware global signaling strategies.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
36	Chong Hyun Lee, Jae Sang Cha	Interference Cancellation Algorithm Development and Implementation for Digital Television.	ICCSA (2)	2005	DBLP DOI BibTeX RDF
33	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
33	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
30	Rodney Van Meter, Thaddeus D. Ladd, W. J. Munro, Kae Nemoto	System design for a long-line quantum repeater.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	purification, quantum networking, quantum repeaters, resource scheduling, quantum information
30	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
30	Sung Ik Park, Heung Mook Kim, So Ra Park, Yong-Tae Lee, Jong Soo Lim	A Novel On-Channel Repeater for Terrestrial-Digital Multimedia Broadcasting System of Korea.	VTC Spring	2008	DBLP DOI BibTeX RDF
30	Hongwu Yang, Weitong Guo, Qingqing Liang	A Speaking Rate Adjustable Digital Speech Repeater for Listening Comprehension in Second-Language Learning.	CSSE (5)	2008	DBLP DOI BibTeX RDF
30	Atul Maheshwari, Wayne P. Burleson	Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
30	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
30	Vineet Wason, Kaustav Banerjee	A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer-interconnect system, statistical delay and power models, sensitivity analysis, parameter variations, statistical optimization
30	Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
30	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
30	Vinita V. Deodhar, Jeffrey A. Davis	Voltage scaling and repeater insertion for high-throughput low-power interconnects.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Atul Maheshwari, Wayne P. Burleson	Repeater and current-sensing hybrid circuits for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	interconnect circuits, delay, power, area
30	Yu Cao 0001, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
30	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
30	Hannu Tenhunen, Dinesh Pamunuwa	On dynamic delay and repeater insertion.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
30	Yu Cao 0001, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.	ISQED	2001	DBLP DOI BibTeX RDF
30	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.	ISLPED	2000	DBLP DOI BibTeX RDF
30	John Lillis, Chung-Kuan Cheng	Timing optimization for multisource nets: characterization andoptimal repeater insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	John Lillis, Chung-Kuan Cheng	Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.	DAC	1997	DBLP DOI BibTeX RDF
24	Paramvir Bahl, Ranveer Chandra, Patrick P. C. Lee, Vishal Misra, Jitendra Padhye, Dan Rubenstein, Yan Yu	Opportunistic use of client repeaters to improve performance of WLANs.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	rate anomaly, wireless, IEEE 802.11
24	David S. Kung 0001, Ruchir Puri	CAD challenges for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
24	Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester	Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
24	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.	DATE	2007	DBLP DOI BibTeX RDF
24	Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant	INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations.	CASES	2007	DBLP DOI BibTeX RDF	interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors
24	Kyungmi Park, Chung Gu Kang 0001, Daeyoung Chang, Seungho Song, Jongguk Ahn, Jongtae Ihm	Relay-enhanced Cellular Performance of OFDMA-TDD System for Mobile Wireless Broadband Services.	ICCCN	2007	DBLP DOI BibTeX RDF
24	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Andrew B. Kahng, Sherief Reda, Puneet Sharma	On-Line Adjustable Buffering for Runtime Power Reduction.	ISQED	2007	DBLP DOI BibTeX RDF
24	Jae-sun Seo, Prashant Singh, Dennis Sylvester, David T. Blaauw	Self-Time Regenerators for High-Speed and Low-Power Interconnect.	ISQED	2007	DBLP DOI BibTeX RDF
24	Prashant Saxena	On controlling perturbation due to repeaters during quadratic placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Lutz H.-J. Lampe, Robert Schober, Simon Yiu	Distributed space-time coding for multihop transmission in power line communication networks.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
24	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	An energy-efficient temporal encoding circuit technique for on-chip high performance buses.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	on-chip buses, energy-efficient, encoding, repeaters
24	Abinash Roy, Masud H. Chowdhury	Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.	APCCAS	2006	DBLP DOI BibTeX RDF