Search results for "signal-path"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
46	Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral signal path, incremental modeling, small-signal, sequential design space pruning, minimax optimization
39	Di Long, Xianlong Hong, Sheqin Dong	Signal-path driven partition and placement for analog circuit.	ASP-DAC	2006	DBLP DOI BibTeX RDF	analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition
20	Janusz Rzeszut, Bozena Kaminska, Yvon Savaria	A new method for testing mixed analog and digital circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits
18	Bengi Karacali, Mark J. Karol	Network-wide inference of end-to-end path intersections.	NOMS	2008	DBLP DOI BibTeX RDF
16	Manabu Mikami, Teruya Fujii	A Downlink Transmission Method for OFDM Cellular Systems with Inter-Cell Interference Cancellation Using Simplified MLD based on MMSE QRD-M Algorithm.	VTC Spring	2008	DBLP DOI BibTeX RDF
14	Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
14	Kong-Aik Lee, Woon-Seng Gan	On Delayless Architecture for the Normalized Subband Adaptive Filter.	ICME	2007	DBLP DOI BibTeX RDF
14	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Low Cost On-Line Testing of RF Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
12	Predrag Spasojevic	Generalized Decorrelators for Fading Channels.	ITCC	2001	DBLP DOI BibTeX RDF
11	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Low Cost On-Line Testing Strategy for RF Circuits.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	on-line analog testing, DSP-based testing, analog test
11	Mohammad A. Al-Shyoukh, A. Teutsch	A pipelined dual-channel switched capacitor programmable gain amplifier.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Piotr Krauze	Identification of Control-Related Signal Path for Semi-Active Vehicle Suspension with Magnetorheological Dampers.	Sensors	2023	DBLP DOI BibTeX RDF
10	Debatrayee Roychowdhury, Soroush Moallemi, Sule Ozev, Jennifer Kitchen	Self-Interference Signal Path Characterization in Full-Duplex Transceivers Using Built-in Self-Test.	RWS	2020	DBLP DOI BibTeX RDF
10	Kentaro Yamamoto, Ken Sasaki, Dairoku Muramatsu, Fukuro Koshiji	Numerical Simulation of Electric Field Distribution and Signal Path of a Commonly Used Schematic Diagram of Human Body Communication.	GCCE	2019	DBLP DOI BibTeX RDF
10	Yu-Lin Chu, Hsi-Yu Kuo, Sheng-Fu Hsu, Yung-Sheng Tsai, Ming-Yi Wang, Chuan-Li Chang, Bill Kiang, Kenneth Wu	A new mechanism of signal path charging damage across separated power domain deep N-Well interface.	IRPS	2018	DBLP DOI BibTeX RDF
10	Zyad Nossire, Julius P. Dichter, Navarun Gupta, Rami AlKawamleh	New Mathematical Model for Wireless Signal Path Loss inside Buildings.	ISPAN-FCST-ISCC	2017	DBLP DOI BibTeX RDF
10	Yunyun Ma, Jinbo Wang, Yuelong Qu, Tao Zhang	Testing Requirement Analysis Method Based on Signal Path for High Reliability Software.	DSA	2017	DBLP DOI BibTeX RDF
10	Leszek J. Opalski, Katarzyna Opalska	Bandwidth broadening of the photodetector signal path.	MIXDES	2016	DBLP DOI BibTeX RDF
10	Kenichi Ito, Yu Hotta	Signal Path Loss Simulation of Human Arm for Galvanic Coupling Intra-Body Communication Using Circuit and Finite Element Method Models.	ISADS	2015	DBLP DOI BibTeX RDF
10	Till Moritz Essinger, Rüdiger Hoffmann	Feedback suppression in a mechanically coupled, short signal path sensor-actuator system for use as a hearing implant.	TSP	2015	DBLP DOI BibTeX RDF
10	Jesús Llor, Manuel P. Malumbres	Statistical Modeling of Large-Scale Signal Path Loss in Underwater Acoustic Networks.	Sensors	2013	DBLP DOI BibTeX RDF
10	Jacques Christophe Rudell, Pankaj Goyal, Christopher D. Hull, Shmuel Ravid, Adil Kidwai	A 1.1V 5-to-6GHz reduced-component direct-conversion transmit signal path in 45nm CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
10	Piotr Laskowski, Arkadiusz Glowacki, Christian Boit	Detectability of dynamic photon emission in static Si CCD for signal path determination in integrated circuits.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
10	Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, Philip John Crawley, James T. Kao, Zhiwei Dong, Madhu Chennam, Tim Nutt, David S. Trager, Mitchell Reid	A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
10	Rod Burt, Joy Zhang	A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
10	Yu Wang 0002, Huazhong Yang, Hui Wang 0004	Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
10	Rod Burt, Joy Zhang	A Micropower Chopper-Stabilized Operational Amplifier using a SC Notch Filter with Synchronous Integration inside the ContinuousTime Signal Path.	ISSCC	2006	DBLP DOI BibTeX RDF
10	Hua Tang, Ying Wei 0002, Alex Doboli	MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption.	DATE	2005	DBLP DOI BibTeX RDF
10	Longji Wang, Victor E. DeBrunner, Linda DeBrunner	Sub-band adaptive filter structure without signal path delay for active control.	ICASSP	2002	DBLP DOI BibTeX RDF
10	Michael Catalano, Richard K. Feldman, Roberto Krutiansky, Richard Swan	Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test System.	ITC	1983	DBLP BibTeX RDF
9	Ming Liu 0022, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003	Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices.	NanoNet	2009	DBLP DOI BibTeX RDF	carbon nanorelay, nanoelectromechanical switch, CMOS-nano hybrid, FPGA, carbon nanotube
9	Liang Zhao, Won Namgoong	A novel phase-noise compensation scheme for communication receivers.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
9	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	An improved RF loopback for test time reduction.	DATE	2006	DBLP DOI BibTeX RDF
9	Mikko Loikkanen, Juha Kostamovaara	PSRR improvement technique for amplifiers with Miller capacitor.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Andreas Westfeld, Gritta Wolf	Steganography in a Video Conferencing System.	Information Hiding	1998	DBLP DOI BibTeX RDF
9	Guoliang Xing, Rui Tan 0001, Benyuan Liu, Jianping Wang 0001, Xiaohua Jia, Chih-Wei Yi	Data fusion improves the coverage of wireless sensor networks.	MobiCom	2009	DBLP DOI BibTeX RDF	performance limits, wireless sensor network, coverage, data fusion, target detection
9	Ana Rusu, Mohammed Ismail 0001, Hannu Tenhunen	A Modified Cascaded Sigma-Delta Modulator with Improved Linearity.	ISVLSI	2005	DBLP DOI BibTeX RDF
9	Jen-Lin Fan, Jieh-Tsorng Wu	A robust background calibration technique for switched-capacitor pipelined ADCs.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
9	Marcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin	Testing RF Signal Paths Using Spectral Analysis and Subsampling.	SBCCI	2003	DBLP DOI BibTeX RDF
9	Magnus Wiklund, Stefan Nilsson, Christian Bjork, Sven Mattisson	A 2GHz image-reject receiver in a low IF architecture fabricated in a 0.1µm CMOS technology.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
9	Masashi Shimanouchi	New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.	ITC	2002	DBLP DOI BibTeX RDF
9	Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu	Test Synthesis for Mixed-Signal SOC Paths.	DATE	2000	DBLP DOI BibTeX RDF
9	Vojin G. Oklobdzija, David Villeger	Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
7	Shouwen Lai, Yuanchen Ma, Hui Deng	HO-RSVP: a protocol providing QoS support for seamless handover between wireless networks.	Q2SWinet	2006	DBLP DOI BibTeX RDF	HO-RSVP, mobile IPv4, QoS, handover, RSVP
7	Miguel Eduardo Litvin, Samiha Mourad	Self-reset logic for fast arithmetic applications.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
7	Miguel A. Martins, Jorge R. Fernandes, Manuel Medeiros Silva	Multi-band combined LNA and mixer.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Reducing Test Time Using an Enhanced RF Loopback.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Loopback test, RF test
7	Ramón González Carvajal, Juan Antonio Gómez Galán, Antonio Jesús Torralba Silgado, Clara Isabel Luján-Martínez, Jaime Ramírez-Angulo, Antonio J. López-Martín	A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor.	ISCAS	2007	DBLP DOI BibTeX RDF
7	Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger	A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
7	Yoshinori Ichikawa, Toshihiro Furukawa	A new approach for non-uniform subband adaptive filtering.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
7	Degang Chen 0001, Zhongjun Yu, Randall L. Geiger	An adaptive, truly background calibration method for high speed pipeline ADC design.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
7	Ramesh Harjani, Jackson Harvey, Robert Sainati	Analog/RF Physical Layer Issues For UWB Systems.	VLSI Design	2004	DBLP DOI BibTeX RDF
7	Anthony Chan Carusone, David A. Johns	A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
5	Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi	Performance assessment of analog circuits with carbon nanotube FET (CNFET).	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	analog, circuits
5	Yongfeng Feng, H. Alan Mantooth	Algorithms for Automatic Model Topology Formulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
5	N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung	Measuring and modeling FPGA clock variability.	FPGA	2008	DBLP DOI BibTeX RDF	within-die variability, modeling, FPGA, process variation, clock skew
5	Qiang Li, Yue-Ping Zhang	Waveform Distortion and Performance of Impulse Radio with Realistic Antennas in Deterministic Multipath Channels.	VTC Spring	2008	DBLP DOI BibTeX RDF
5	Sam Vakil, Ben Liang 0001	Effect of Joint Cooperation and Multi-Hopping on the Capacity of Wireless Networks.	SECON	2008	DBLP DOI BibTeX RDF
5	Mingjie Lin, Jianying Luo, Yaling Ma	A low-power monolithically stacked 3D-TCAM.	ISCAS	2008	DBLP DOI BibTeX RDF
5	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.	DELTA	2008	DBLP DOI BibTeX RDF	high-level decision diagrams, fault tolerance, fault simulation
5	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
5	Chung-Yu Wu, Chien-Ta Huang	A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
5	Chao Yang 0030, Andrew J. Mason	Zero-IF VGA with novel offset cancellation.	ISCAS	2006	DBLP DOI BibTeX RDF
5	Chang-Ching Wu, A. Yen, Jen-Chung Chang	A 0.13µm CMOS T/R switch design for ultrawideband wireless applications.	ISCAS	2006	DBLP DOI BibTeX RDF
5	Jia Di, Dilip P. Vasudevan	Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.	DELTA	2006	DBLP DOI BibTeX RDF
5	Franz Schlögl, Horst Dietrich, Horst Zimmermann	Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS.	APCCAS	2006	DBLP DOI BibTeX RDF
5	Robert G. Lorenz, Stephen P. Boyd	Robust minimum variance beamforming.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
5	Eric Lebel, Ali Assi 0001, Mohamad Sawan	Field programmable Gm-C array for wide frequency range bandpass filter applications.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
5	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
5	Hassan El Makssoud, David Guiraud, Philippe Poignet	Mathematical Muscle Model for Functional Electrical Stimulation Control Strategies.	ICRA	2004	DBLP DOI BibTeX RDF
5	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
5	Adão Antônio de Souza Jr., Luigi Carro	Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities.	DFT	2004	DBLP DOI BibTeX RDF
5	J. Shorb, Xiaoyong Li 0001, David J. Allstot	A resonant pad for ESD protected narrowband CMOS RF applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
5	Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald 0001	A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	BC, BCII, FPGA, dynamic routing, CML
5	D. J. Kinniment, Oleh V. Maevsky, Gordon Russell 0002, Alexandre Yakovlev, Alexandre V. Bystrov	On-Chip Structures for Timing Measurements and Test.	ASYNC	2002	DBLP DOI BibTeX RDF
5	Bradley A. Minch	Inverting the bipolar differential pair for low-voltage applications.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
5	Tim Hendtlass, Gerard Murray	The Macronet Element: A Substitute for the Conventional Neuron.	IEA/AIE	2002	DBLP DOI BibTeX RDF
5	Erik Bruun	On dynamic range limitations of CMOS current conveyors.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
5	Mourad N. El-Gamal, Gordon W. Roberts	A 1.2 V NPN-only log-domain integrator.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
5	Raimund Ubar, Marina Brik	Multi-Level Test Generation and Fault Diagnosis for Finite State Machines.	EDCC	1996	DBLP DOI BibTeX RDF