Search results for "single-rail"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
98	Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel	A single-rail re-implementation of a DCC error detector using a generic standard-cell library.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits
74	Ad M. G. Peeters, Kees van Berkel 0001	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
61	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Design and Analysis of Dual-Rail Circuits for Security Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security
61	Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Improving the Security of Dual-Rail Circuits.	CHES	2004	DBLP DOI BibTeX RDF
54	Frank Grassert, Dirk Timmermann	Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	redundant numbers, self-timed logic, single-rail logic, low power, dynamic logic
53	Radu Negulescu, Ad M. G. Peeters	Verification of Speed-Dependences in Single-Rail Handshake Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF	single-rail, isochronic forks, verification, timing, asynchronous circuits, progress, speed-independent circuits, process spaces, handshake circuits
51	David W. Lloyd, Jim D. Garside	A Practical Comparison of Asynchronous Design Styles.	ASYNC	2001	DBLP DOI BibTeX RDF
50	Abhinav Vishnu, Gopalakrishnan Santhanaraman, Wei Huang 0003, Hyun-Wook Jin, Dhabaleswar K. Panda 0001	Supporting MPI-2 One Sided Communication on Multi-rail InfiniBand Clusters: Design Challenges and Performance Benefits.	HiPC	2005	DBLP DOI BibTeX RDF
48	Eric Menendez, Ken Mai	A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.	HOST	2008	DBLP DOI BibTeX RDF
43	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
43	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
42	Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang	A new robust handshake for asymmetric asynchronous micro-pipelines.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
42	Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu	A Robust Handshake for Asynchronous System.	IWSOC	2003	DBLP DOI BibTeX RDF
32	Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya	A zero-time-overhead asynchronous four-phase controller.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng	A semi-custom memory design for an asynchronous 8051 microcontroller.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Paavan Mistry, Raymond S. K. Kwan	Generation and Optimization of Train Timetables Using Coevolution.	GECCO	2003	DBLP DOI BibTeX RDF
30	Jae-Hee Won, Kiyoung Choi	Low power self-timed Radix-2 division (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	RSD, radix-2 division, low power, self-timed
30	Mark E. Dean, David L. Dill, Mark Horowitz	Self-timed logic using Current-Sensing Completion Detection (CSCD).	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
28	Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu	A dual-rail/single-rail hybrid system using null convention logic circuits.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
28	Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.	ISCAS	2012	DBLP DOI BibTeX RDF
28	Gensoh Matsubara, Nobuhiro Ide	A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.	ASYNC	1997	DBLP DOI BibTeX RDF	floating point, division, square root, self-timed
21	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
21	Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.	FPL	2006	DBLP DOI BibTeX RDF
21	Geun Rae Cho, Tom Chen 0001	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.	VLSI Design	2003	DBLP DOI BibTeX RDF
21	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
21	Luis A. Plana, Steven M. Nowick	Architectural optimization for low-power nonpipelined asynchronous systems.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
21	Hyunseok Jeong, Seunglee Bae, Seongjeon Choi	Quantum teleportation between a single-rail single-photon qubit and a coherent-state qubit using hybrid entanglement under decoherence effects.	Quantum Inf. Process.	2016	DBLP DOI BibTeX RDF
16	Yanjiang Liu, Tongzhou Qu, Zibin Dai	A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks.	ACM Trans. Design Autom. Electr. Syst.	2022	DBLP DOI BibTeX RDF
16	Adnan Ghafoor, Muhammad Waqar Mughal, Arbab A. Khan	An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner	A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
16	Maryem Benyoussef, Claude Thibeault, Yvon Savaria	A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits.	ISCAS	2019	DBLP DOI BibTeX RDF
16	Wenyi Tang, Song Jia, Yuan Wang 0001	A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
16	Lukás Nagy, Viera Stopjaková, Juraj Brenkus	Current Sensing Completion Detection in Single-Rail Asynchronous Systems.	Comput. Informatics	2014	DBLP BibTeX RDF
16	Ruiping Cao, Jianping Hu	Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits.	J. Electr. Comput. Eng.	2014	DBLP DOI BibTeX RDF
16	Amir Moradi 0001, Thomas Eisenbarth 0001, Axel Poschmann, Christof Paar	Power Analysis of Single-Rail Storage Elements as Used in MDPL.	ICISC	2009	DBLP DOI BibTeX RDF
16	Weiwen Zhu, Zeljko Zilic, Radu Negulescu	A single-rail handshake CDMA correlator.	ICECS	2002	DBLP DOI BibTeX RDF
16	Eckhard Grass, Richard C. S. Morling, Izzet Kale	Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing.	ASYNC	1996	DBLP DOI BibTeX RDF
16	Hung Chi Lai, Saburo Muroga	Design of MOS networks in single-rail input logic for incompletely specified functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
12	Abdelhalim Alsharqawi, Abdel Ejnioui	Clockless Pipelining for Coarse Grain Datapaths.	VLSI Design	2006	DBLP DOI BibTeX RDF
11	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	Dual-threshold pass-transistor logic design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual threshold, pass transistor, low power, leakage
11	Maurizio Tranchero, Leonardo Maria Reyneri	Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools.	DSD	2008	DBLP DOI BibTeX RDF
11	Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang	A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	semi-dynamic, sparse-tree, parallel prefix adder
11	Abhinav Vishnu, Brad Benton, Dhabaleswar K. Panda 0001	High Performance MPI on IBM 12x InfiniBand Architecture.	IPDPS	2007	DBLP DOI BibTeX RDF
11	Atabak Mahram, Mehrdad Najibi, Hossein Pedram	An asynchronous fpga logic cell implementation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	PCHB, a synchronous design, logic cell, FPGA
11	Petros Oikonomakos, Simon W. Moore	An Asynchronous PLA with Improved Security Characteristics.	DSD	2006	DBLP DOI BibTeX RDF
11	Feng Shi 0010, Yiorgos Makris	Testing delay faults in asynchronous handshake circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	test generation, asynchronous circuits, delay faults, handshake circuits
11	Wai-Chi Fang, Jaw-Chyng L. Lue	VLSI Bio-Inspired Microsystem for Robust Microarrray Image Analysis and Recognition.	IIH-MSP	2006	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
11	Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel	An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Bhushan A. Shinkre, James E. Stine	A pipelined clock-delayed domino carry-lookahead adder.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
11	Scott C. Smith	Speedup of Self-Timed Digital Systems Using Early Completion.	ISVLSI	2002	DBLP DOI BibTeX RDF	asynchronous, NCL, NULL Convention Logic, delay-insensitive
11	Ad M. G. Peeters, Kees van Berkel 0001	Synchronous Handshake Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
11	Byung G. Jo, Jin Y. Kang, Myung Hoon Sunwoo	A low power and area efficient FIR filter chip for PRML read channels.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
11	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
11	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF