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Found 312 publication records. Showing 312 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
143 | Jian Wang, Guang R. Gao |
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 1-17, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism |
122 | Monica S. Lam |
Software pipelining: an effective scheduling technique for VLIW machines (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 244-256, 1988, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
101 | Reese B. Jones, Vicki H. Allan |
Software pipelining: a comparison and improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 46-56, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
recognition of parallelism, software pipelining, operation scheduling |
95 | João M. P. Cardoso |
Dynamic loop pipelining in data-driven architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 106-115, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compilation, reconfigurable computing, software pipelining, dataflow, data-driven architectures |
88 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Time Optimal Software Pipelining of Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(5), pp. 339-391, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compiler optimization, instruction-level parallelism, software pipelining, VLIW |
78 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-dimension software pipelining for multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 7, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Software pipelining, loop transformation, modulo scheduling |
76 | Mark G. Stoodley, Corinna G. Lee |
Software Pipelining Loops with Conditional Branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 262-273, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
73 | Won So, Alexander G. Dean |
Complementing software pipelining with software thread integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 137-146, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration |
69 | Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao |
Minimizing communication in rate-optimal software pipelining for stream programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 210-217, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dfbrook, multi-core, software pipelining, cell processor, stream programs |
67 | Dragan Milicev, Zoran Jovanovic |
A Formal Model of Software Pipelining Loops with Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 554-558, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software pipelining loops, PSP model, parallel programming, finite state machine, formal model, software pipelining, parallelizing loops, conditional branches |
63 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 138-144, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
62 | Monica Lam 0001 |
Software Pipelining: An Effective Scheduling Technique for VLIW Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'88 Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, June 22-24, 1988, pp. 318-328, 1988, ACM, 0-89791-269-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
62 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Optimal software pipelining of loops with control flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 117-128, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, software pipelining, VLIW |
61 | Miodrag Potkonjak, Jan M. Rabaey |
Optimizing throughput and resource utilization using pipelining: Transformation based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(2), pp. 117-130, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
61 | Noureddine Chabini, Wayne H. Wolf |
An approach for integrating basic retiming and software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2004, September 27-29, 2004, Pisa, Italy, Fourth ACM International Conference On Embedded Software, Proceedings, pp. 287-296, 2004, ACM, 1-58113-860-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size |
61 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 613-620, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Scheduling, Software pipelining, Retiming, DSP processors |
60 | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 338-344, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation |
60 | Alexander Aiken, Alexandru Nicolau, Steven Novack |
Resource-Constrained Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(12), pp. 1248-1270, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Software pipelining, instruction scheduling, program optimization, global scheduling, fine-grain parallelism |
60 | Jian Wang 0046, Andreas Krall, M. Anton Ertl, Christine Eisenbeis |
Software pipelining with register allocation and spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 95-99, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling |
59 | Mohammed Fellahi, Albert Cohen 0001 |
Software Pipelining in Nested Loops with Prolog-Epilog Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 80-94, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
56 | Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor |
A comparative evaluation of software techniques to hide memory latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 229-241, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches |
54 | Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao |
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 175-188, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Haibo Lin, Wenlong Li, Zhizhong Tang |
Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Programming Technologies, 5th International Workshop, APPT 2003, Xiamen, China, September 17-19, 2003, Proceedings, pp. 109-113, 2003, Springer, 3-540-20054-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
53 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 182-199, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
53 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 67-72, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors |
53 | Pierre-Yves Calland, Alain Darte, Yves Robert |
Circuit Retiming Applied to Decomposed Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(1), pp. 24-35, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling |
52 | Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001 |
Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part I, pp. 820-826, 2005, Springer, 3-540-28894-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano |
Software De-Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 15-16 September 2004, Chicago, IL, USA, pp. 7-16, 2004, IEEE Computer Society, 0-7695-2144-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Hui Liu 0006, Zili Shao, Meng Wang 0005, Junzhao Du, Chun Jason Xue, Zhiping Jia |
Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 249-262, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming |
51 | Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson |
Latency-tolerant software pipelining in a production compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 104-113, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic |
51 | Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo |
Control Mechanism for Software Pipelining on Nested Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 345-350, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ILSP, software pipelining, VLIW, dataflow, nested loop |
49 | Reese B. Jones, Vicki H. Allan |
Software Pipelining: An Evaluation of Enhanced Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991, pp. 82-92, 1991, ACM/IEEE, 0-89791-460-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
software pipelining, instruction scheduling, loop optimization, fine-grain parallelism |
49 | Kalyan Muthukumar, Gautam Doshi |
Software Pipelining of Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 165-181, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson |
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung |
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1268-1280, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
46 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-Dimension Software Pipelining for Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 163-174, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard |
SCAN: A Heuristic for Near-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 289-298, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong |
Towards efficient fine-grain software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 369-379, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
45 | Daniel Kästner, Markus Pister 0002 |
Generic Software Pipelining at the Assembly Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29 - October 1, 2005, pp. 50-61, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
PROPAN, software pipelining, modulo scheduling, postpass optimization |
45 | Peter Pfahler, Georg Piepenbrock |
A Comparison of Modulo Scheduling Techniques for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 18-32, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors |
45 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multi-dimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 154-167, 2005, ACM, 1-59593-056-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
44 | Chihong Zhang, Zhizhong Tang |
An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 378-382, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
44 | Vincent Van Dongen, Guang R. Gao, Qi Ning |
A Polynomial Time Method for Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 613-624, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
44 | Bogong Su, Jian Wang 0046, Zhizhong Tang, Wei Zhao, Yimin Wu |
A software pipelining based VLIW architecture and optimizing compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 17-27, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
44 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Timing Optimization of Nested Loops Considering Code Size for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 475-482, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Sid Ahmed Ali Touati |
On the Periodic Register Need in Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1493-1504, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining |
44 | G. X. Tyson, M. Smelyanskyi, Edward S. Davidson |
Evaluating the Use of Register Queues in Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 769-783, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW |
43 | Jean-Baptiste Tristan, Xavier Leroy |
A simple, verified validator for software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010, pp. 83-92, 2010, ACM, 978-1-60558-479-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
software pipelining, translation validation, verified compilers, symbolic evaluation |
43 | Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August |
Performance scalability of decoupled software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(2), pp. 8:1-8:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Decoupled software pipelining, performance analysis |
43 | Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria |
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 187-204, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multiphase, sequential circuit, software pipelining, clock, Retiming |
43 | François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer |
Optimal design of synchronous circuits using software pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 516-532, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
software pipelining, retiming, Resynthesis |
43 | Soo-Mook Moon, Kemal Ebcioglu |
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(6), pp. 853-898, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar |
43 | Bogong Su, Stanley Habib, Wei Zhao, Jian Wang 0046, Youfeng Wu |
A study of pointer aliasing for software pipelining using run-time disambiguation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 112-117, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
compensation code, pointer aliasing, rerollability, run-time disambiguation, software pipelining |
43 | B. Ramakrishna Rau |
Iterative modulo scheduling: an algorithm for software pipelining loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 63-74, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
software pipelining, instruction scheduling, modulo scheduling, loop scheduling |
42 | Gang-Ryung Uh |
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 133-150, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | SangMin Shim, Soo-Mook Moon |
Split-Path Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 447-462, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling |
41 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 977-994, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing |
41 | Ramaswamy Govindarajan, Guang R. Gao, Palash Desai |
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(3), pp. 207-229, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs |
39 | Yoshiyuki Yamashita, Masato Tsuru |
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 420-435, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | John C. Ruttenberg, Guang R. Gao, Woody Lichtenstein, Artour Stoutchinin |
Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), Philadephia, Pennsylvania, USA, May 21-24, 1996, pp. 1-11, 1996, ACM, 0-89791-795-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1014-1029, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
37 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1395-1415, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Cagdas Akturan, Margarida F. Jacome |
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 34-40, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Qi Ning, Guang R. Gao |
A Novel Framework of Register Allocation for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Charleston, South Carolina, USA, January 1993, pp. 29-42, 1993, ACM Press, 0-89791-560-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee |
A software pipelining algorithm in high-level synthesis for FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 297-302, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August |
Parallel-stage decoupled software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 114-123, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism |
36 | Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu |
Exploiting Software Pipelining for Network-on-Chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 295-302, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Alban Douillet, Hongbo Rong, Guang R. Gao |
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 311-322, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Ke Zhou 0001, Zhongying Niu |
Decease I/O Mean Response Time Using Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 332-337, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Raya Leviathan, Amir Pnueli |
Validating software pipelining optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 280-287, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, verification, compilers, pipeline processors, translation validation |
36 | Josep Llosa, Mateo Valero, Eduard Ayguadé |
Heuristics for Register-Constrained Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 250-261, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
36 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 640-651, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong |
An Efficient Scheme for Fine-Grain Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 90 - VAPP IV, Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, September 10-13, 1990, Proceedings, pp. 709-720, 1990, Springer, 3-540-53065-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
35 | Hugo Venturini, Frédéric Riss, Jean-Claude Fernandez, Miguel Santana |
Non-transparent debugging for software-pipelined loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 23-32, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-transparent debugging, compiler, software-pipelining, debugger |
34 | Bogong Su, Shiyuan Ding, Jian Wang 0046, Jinshi Xia |
GURPR - a method for global software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 88-96, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
34 | Chen Ding, Steve Carr 0001, Philip H. Sweany |
Modulo Scheduling with Cache Reuse Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1079-1083, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Glenn Altemose, Cindy Norris |
Register pressure responsive software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), March 11-14, 2001, Las Vegas, NV, USA, pp. 626-631, 2001, ACM, 1-58113-287-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
34 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(11), pp. 1133-1149, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling |
34 | Pierre-Yves Calland, Alain Darte, Yves Robert |
A New Guaranteed Heuristic for the Software Pipelining Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996, pp. 261-269, 1996, ACM, 0-89791-803-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit retiming, guaranteed heuristic, software pipelining, list scheduling, cyclic scheduling |
34 | Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001 |
Post-pass periodic register allocation to minimise loop unrolling degree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 141-150, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded code optimisation, periodic register allocation, software pipelining, loop unrolling |
34 | Christopher Zimmer 0001, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley |
Facilitating compiler optimizations through the dynamic mapping of alternate register structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 165-169, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register queues, compiler optimizations, software pipelining |
34 | Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha |
Code size reduction technique and implementation for software-pipelined DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(4), pp. 590-613, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, software pipelining, Retiming, DSP processors |
34 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
MIRS: Modulo Scheduling with Integrated Register Spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1-3, 2001. Revised Papers, pp. 239-253, 2001, Springer, 3-540-04029-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code |
34 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Improved spill code generation for software pipelined loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Vancouver, Britith Columbia, Canada, June 18-21, 2000, pp. 134-144, 2000, ACM, 1-58113-199-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, spill code |
33 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 153-162, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
29 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 237-247, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Yoshiyuki Yamashita, Masato Tsuru |
Software Pipelining for Packet Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Third International Conference, HPCC 2007, Houston, USA, September 26-28, 2007, Proceedings, pp. 446-459, 2007, Springer, 978-3-540-75443-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Lin Qiao, Weitong Huang, Zhizhong Tang |
A Dynamic Data Dependence Analysis Approach for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 221-228, 2005, Springer, 3-540-29810-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Steve Carr 0001, Chen Ding, Philip H. Sweany |
Improving Software Pipelining with Unroll-and-Jam. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 29th Annual Hawaii International Conference on System Sciences (HICSS-29), January 3-6, 1996, Maui, Hawaii, USA, pp. 183-192, 1996, IEEE Computer Society, 0-8186-7324-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao |
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), La Jolla, California, USA, June 18-21, 1995, pp. 139-150, 1995, ACM, 0-89791-697-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Minimizing register requirements under resource-constrained rate-optimal software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 85-94, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
28 | Kemal Ebcioglu |
A compilation technique for software pipelining of loops with conditional jumps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 69-79, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
28 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(4), pp. 23:1-23:68, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register allocation, Software pipelining |
28 | F. Jesús Sánchez, Antonio González 0001 |
Cache Sensitive Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 338-348, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
VLIW machines, Software pipelining, software prefetching, locality analysis |
27 | Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zhang 0005, Tzu-Han Hung, David I. August |
Decoupled software pipelining creates parallelization opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 121-130, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DSWP, enabling transformation, parallelization, multicore, speculation |
27 | Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba |
Clustered Decoupled Software Pipelining on Commodity CMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 681-688, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August |
Speculative Decoupled Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 49-59, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August |
Automatic Thread Extraction with Decoupled Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 105-118, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yanjun Zhang, Hu He 0001, Yihe Sun |
A new register file access architecture for software pipelining in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 627-630, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August |
Decoupled Software Pipelining with the Synchronization Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 177-188, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
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