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Searching for phrase test-per-clock (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1995-2002 (18) 2003-2009 (16) 2010-2017 (6)
Publication types (Num. hits)
article(17) inproceedings(23)
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The graphs summarize 65 occurrences of 43 keywords

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Found 40 publication records. Showing 40 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
100Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
73Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel A Gated Clock Scheme for Low Power Testing of Logic Cores. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test-per-scan, test-per-clock, low power design, low power test
71Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding
66Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Test-per-Clock Schemes, Reseeding Techniques, Built-In Self-Test, Linear Feedback Shift Registers, Test Pattern Generation
53Shivakumar Swaminathan, Krishnendu Chakrabarty On Using Twisted-Ring Counters for Test Set Embedding in BIST. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
49Ondrej Novák, Jiri Nosek Test-per-Clock Testing of the Circuits with Scan. Search on Bibsonomy IOLTW The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST. Search on Bibsonomy IDT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
45Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch An adjacency-based test pattern generator for low power BIST design. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
43Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan Multimode scan: Test per clock BIST for IP cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF SoC, BIST, scan, digital testing
35Chien-In Henry Chen, Kiran George Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Search on Bibsonomy Asian Test Symposium The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
31Malav Shah Efficient scan-based BIST scheme for low power testing of VLSI chips. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
31Danial J. Neebel, Charles R. Kime Cellular Automata for Weighted Random Pattern Generation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multiple weight sets, hybrid cellular automata, weighted cellular automata, test-per-clock pattern generation, Built-in self-test, cellular automata, weighted random patterns
30Bin Zhou, Yizheng Ye, Yongsheng Wang Simultaneous reduction in test data volume and test time for TRC-reseeding. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF encoded vector, twisted-ring counter, built-in self test
30Chien-In Henry Chen, Kiran George Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Ioannis Voyiatzis Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns. Search on Bibsonomy ETS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
30Shaochong Lei, Zhen Wang, Zeye Liu 0002, Feng Liang A low cost test pattern generator for test-per-clock BIST scheme. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
27Abhijit Jas, Kartik Mohanram, Nur A. Touba An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
25Zhiyuan He 0002, Gert Jervan, Zebo Peng, Petru Eles Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici Power profile manipulation: a new approach for reducing test application time under power constraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Ondrej Novák, Zdenek Plíva Logic testing with test-per-clock pattern loading and improved diagnostic abilities. Search on Bibsonomy DDECS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
25Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick An Accumulator - Based Test-Per-Clock Scheme. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka Test-per-Clock Detection, Localization and Identification of Interconnect Faults. Search on Bibsonomy ETS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Malav Shah, Dipankar Nagchoudhuri BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Albrecht P. Stroele, Hans-Joachim Wunderlich Hardware-optimal test register insertion. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos Reseeding-Based Test Set Embedding with Reduced Test Sequences. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
22Ondrej Novák, Jiri Nosek Test Pattern Decompression Using a Scan Chain. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF hardware test pattern generators, BIST, test pattern generation, scan design
20Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas A new built-in TPG method for circuits with random patternresistant faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
19Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
19Debaditya Mukherjee, Melvin A. Breuer An IEEE 1149.1 Compliant Test Control Architecture. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
19Albrecht P. Stroele, Hans-Joachim Wunderlich Test register insertion with minimum hardware cost. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test register insertion, BILBO, CBILBO, Built-in self-test
18Jacob Savir Distributed BIST Architecture to Combat Delay Faults. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF BIST, LFSR, delay test, MISR, LSSD, SRL
17Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou Deterministic BIST for RNS Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
15Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu An Improved Soft-Error Rate Measurement Technique. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
14Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka Effective BIST for crosstalk faults in interconnects. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
14Petr Fiser Pseudo-Random Pattern Generator Design for Column-Matching BIST. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
12Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu Accelerating Soft Error Rate Testing Through Pattern Selection. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error
12Nur A. Touba Circular BIST with state skipping. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
12Egor S. Sogomonyan, Adit D. Singh, Michael Gössel A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF design-for-testability, BIST, scan design
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