Search results for "testbench"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Martin Zambaldi, Wolfgang Ecker	Re-use-centric architecture for a fully accelerated testbench environment.	DAC	2003	DBLP DOI BibTeX RDF	hardware testbench, acceleration, functional verification
111	Kelly D. Larson	Translation of an existing VMM-based SystemVerilog testbench to OVM.	DAC	2008	DBLP DOI BibTeX RDF	OVM, VMM, testbenches, SystemVerilog
111	Young-Il Kim, Chong-Min Kyung	Automatic translation of behavioral testbench for fully accelerated simulation.	ICCAD	2004	DBLP DOI BibTeX RDF
105	Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi	Property-Specific Testbench Generation for Guided Simulation.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	guided simulation, intelligent testbench generation, witness graph, property-specific testbench, approximate model checking, symbolic model checking, iterative refinement
72	Görschwin Fey, Rolf Drechsler	Improving simulation-based verification by means of formal methods.	ASP-DAC	2004	DBLP DOI BibTeX RDF
53	Ioannis Mavroidis, Ioannis Papaefstathiou	Efficient testbench code synthesis for a hardware emulator system.	DATE	2007	DBLP DOI BibTeX RDF
53	Aman Kokrady, Theo J. Powell, S. Ramakrishnan	Reducing Design Verification Cycle Time through Testbench Redundancy.	VLSI Design	2006	DBLP DOI BibTeX RDF
50	Stanislaw Deniziak, Krzysztof Sapiecha	High Level Testbench Generation for VHDL Models.	ECBS	1999	DBLP DOI BibTeX RDF	simulation, VHDL, testbench
43	Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung	Communication-efficient hardware acceleration for fast functional simulation.	DAC	2004	DBLP DOI BibTeX RDF	functional verification, communication overhead, simulation acceleration
43	Matthias Bauer 0003, Wolfgang Ecker, Renate Henftling, Andreas Zinn	A Method for Accelerating Test Environments.	EUROMICRO	1999	DBLP DOI BibTeX RDF
41	Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard	Maintaining consistency between systemC and RTL system designs.	DAC	2006	DBLP DOI BibTeX RDF	SPIRIT, transactor, verification, systemC, RTL, TLM, testbench, VIP
38	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
38	Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang	Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	verification strategy, optimization, functional verification, coverage analysis, hierarchical verification
38	Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park	Instruction Based Testbench Architecture, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
38	Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta	An automatic testbench generation tool for a SystemC functional verification methodology.	SBCCI	2004	DBLP DOI BibTeX RDF	Brazilip, SCV, VeriSC, tool, SystemC
38	Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Wolfgang Ecker, Martin Zambaldi	Platform-Based Testbench Generation.	DATE	2003	DBLP DOI BibTeX RDF
29	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	A PD-based methodology to enhance efficiency in testbenches with random stimulation.	SBCCI	2009	DBLP DOI BibTeX RDF	parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis
29	Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang	RT-level vector selection for realistic peak power simulation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	peak power estimation, vector selection, power modeling
29	Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil	TLM: Crossing Over From Buzz To Adoption.	DAC	2007	DBLP DOI BibTeX RDF
29	Alexander Krupp, Wolfgang Müller 0003	Classification trees for random tests and functional coverage.	DATE	2006	DBLP DOI BibTeX RDF
29	Sanggyu Park, Soo-Ik Chae	A C/C++-Based Functional Verification Framework Using the SystemC Verification Library.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
29	Sylvain Huet, Emmanuel Casseau, Olivier Pasquier	Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
29	Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Program Generation: A Case Study.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
29	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
29	Christian Stangier, Ulrich Holtmann	Applying Formal Verification with Protocol Compiler.	DSD	2001	DBLP DOI BibTeX RDF
26	Brian Bailey	Was it worth the wait? Yes!	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	verification, formal verification, design reuse, testbench, SystemVerilog
26	Indradeep Ghosh, Srivaths Ravi 0001	On automatic generation of RTL validation test benches using circuit testing techniques.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage
26	Kanna Shimizu, David L. Dill	Deriving a simulation input generator and a coverage metric from a formal specification.	DAC	2002	DBLP DOI BibTeX RDF	BDD minimization, input generation, coverage, testbench
24	Nikolas J. Wilhelm, Constantin von Deimling, Sami Haddadin, Claudio Glowalla, Rainer Burgkart	Validation of a Robotic Testbench for Evaluating Biomechanical Effects of Implant Rotation in Total Knee Arthroplasty on a Cadaveric Specimen.	Sensors	2023	DBLP DOI BibTeX RDF
24	Mohammad Ismael, Ayman Hroub, Abdellatif Abu-Issa	AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification.	ICM	2023	DBLP DOI BibTeX RDF
24	Hasan Tariq, Mohammed Alsageer, Tamer Khattab, Farid Touati	Autonomous SkyCube Testbench using UAV-Assisted Ka-Band OFDM Transceiver.	IWCMC	2023	DBLP DOI BibTeX RDF
24	Rikard Gannedahl, Javad Bagheri Asli, Henrik Sjöland, Atila Alvandpour	A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity.	NEWCAS	2023	DBLP DOI BibTeX RDF
24	Antonio González-Morgado, Guillermo Heredia, Aníbal Ollero	An Open-Source, Low-Cost UAV Testbench for Educational Purposes.	ROBOT (2)	2023	DBLP DOI BibTeX RDF
24	Luke R. Upton, Guénolé Lallement, Michael D. Scott 0002, Joyce Taylor, Robert M. Radway, Dennis Rich, Mark Nelson, Subhasish Mitra, Boris Murmann	Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices.	ISQED	2023	DBLP DOI BibTeX RDF
24	Abhishek Sanjeev Chandgaonkar, Vaishali Ingale, Vinay Patil, Vanita Agarwal	Development Of SV UVM Testbench For Verification Of AMBA AXI3 IP Used For Memory Access Application.	ICCCNT	2023	DBLP DOI BibTeX RDF
24	Shreyash Naresh Chauhan, Ganesh K. Andurkar	Development of UVM Testbench for I3C protocol.	ICCCNT	2023	DBLP DOI BibTeX RDF
24	Ruolin Wang, Yuejiao Xu, Jie Peng, Jianmin Ji	A²CoST: An ASP-based Avoidable Collision Scenario Testbench for Autonomous Vehicles.	KR	2023	DBLP DOI BibTeX RDF
24	John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis	A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi.	IDAACS	2023	DBLP DOI BibTeX RDF
24	Valentin Baier, Michael Schardt, Maximilian Fink, Martin Jakobi, Alexander W. Koch	MEMS-Scanner Testbench for High Field of View LiDAR Applications.	Sensors	2022	DBLP DOI BibTeX RDF
24	Haopeng Chen, Steffen Müller 0002	Analysis of Real-Time LiDAR Sensor Simulation for Testing Automated Driving Functions on a Vehicle-in-the-Loop Testbench.	IV	2022	DBLP DOI BibTeX RDF
24	Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang 0001, Xuan Zeng 0001, Dian Zhou	A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.	ASP-DAC	2022	DBLP DOI BibTeX RDF
24	Alessio Paolo Buccino, Gaute T. Einevoll	MEArec: A Fast and Customizable Testbench Simulator for Ground-truth Extracellular Spiking Activity.	Neuroinformatics	2021	DBLP DOI BibTeX RDF
24	Jorge Jiménez, Antoni Grau, Cristobal Padilla	Integration of a Testbench for the Optical and Thermal Characterization of Near-Infrared Detectors Used in Ground and Space-Based Astronomy.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
24	Harsh Bhargav, Vineesh V. S., Binod Kumar 0001, Virendra Singh	Enhancing Testbench Quality via Genetic Algorithm.	MWSCAS	2021	DBLP DOI BibTeX RDF
24	Aditya Kulkarni, Ayush Singh, Sachin Arun Waje, Sunil Shrirangrao Kashide, Seonil Brian Choi	TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs.	SoCC	2021	DBLP DOI BibTeX RDF
24	Selim Solmaz, Franz R. Holzinger	A Novel Testbench for Development, Calibration and Functional Testing of ADAS/AD Functions.	ICCVE	2019	DBLP DOI BibTeX RDF
24	Youngnam Han	5G K-Simulator and TestBench Demonstration Proposal.	CCNC	2019	DBLP DOI BibTeX RDF
24	Vineeth B, B. Bala Tripura Sundari	UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol.	ICACCI	2018	DBLP DOI BibTeX RDF
24	Jigar Savla	Getting Started on Co-Emulation: Transition your Design and Testbench to an Emulator.	MTV	2018	DBLP DOI BibTeX RDF
24	Slimane Boutobza, Sorin Popa, Andrea Costa	An Automatic Testbench Generator for Test Patterns Validation.	EWDTS	2018	DBLP DOI BibTeX RDF
24	Muhammad Hassan 0002, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler	Testbench qualification for SystemC-AMS timed data flow models.	DATE	2018	DBLP DOI BibTeX RDF
24	Khaled Salah 0001, Hassan Mostafa	Constructing Effective UVM Testbench for DRAM Memory Controllers.	NGCAS	2018	DBLP DOI BibTeX RDF
24	Nicole Fern, Kwang-Ting Cheng	Mining mutation testing simulation traces for security and testbench debugging.	ICCAD	2017	DBLP DOI BibTeX RDF
24	Neeraj Bokde, Kishore Kulat	R package imputeTestbench as a Testbench to compare missing value imputation methods.	CoRR	2016	DBLP BibTeX RDF
24	Ahmed El-Naggar, Essraa Massoud, Ahmed Medhat, Hala Ibrahim, Bassma Al-Abassy, Sameh El-Ashry, Mostafa Khamis, Ahmed Shalaby 0001	A narrative of UVM testbench environment for interconnection routers: A practical approach.	IDT	2016	DBLP DOI BibTeX RDF
24	Ralph Weissnegger, Markus Pistauer, Christian Kreiner, Markus Schuß, Kay Römer, Christian Steger	Automatic Testbench Generation for Simulation-based Verification of Safety-critical Systems in UML.	PECCS	2016	DBLP DOI BibTeX RDF
24	Kai Huang 0002, Peng Zhu, Rongjie Yan, Xiaolang Yan	Functional Testbench Qualification by Mutation Analysis.	VLSI Design	2015	DBLP DOI BibTeX RDF
24	Eman El Mandouh, Amr G. Wassal	Guiding intelligent testbench automation using data mining and formal methods.	IDT	2015	DBLP DOI BibTeX RDF
24	Mohamed Abdelsalam, Ashraf Salem	SoC verification platforms using HW emulation and co-modeling Testbench technologies.	IDT	2015	DBLP DOI BibTeX RDF
24	Graziella Scandurra, Gianluca Cannatà, Gino Giusi, Carmine Ciofi	A simple and effective testbench for quartz tuning fork characterization and sensing applications.	I2MTC	2015	DBLP DOI BibTeX RDF
24	Dong Gwan Lee, Kil Seok Cho, Jin Hwa Shin	A simple prediction method of ballistic missile trajectory to designate search direction and its verification using a testbench.	ASCC	2015	DBLP DOI BibTeX RDF
24	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli	Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
24	Somnath Banerjee 0003, Tushar Gupta	Optimized Simulation Acceleration with Partial Testbench Evaluation.	MTV	2014	DBLP DOI BibTeX RDF
24	Lucas Cicero, Camel Tanougast, Harry Ramenah, Loïc Siéler, F. Lecerf	A Li-Ion cell testbench for fast characterization and modeling.	CoDIT	2014	DBLP DOI BibTeX RDF
24	Mehdi Dehbashi, André Sülflow, Görschwin Fey	Automated design debugging in a testbench-based verification environment.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
24	Geng Zhong, Jian Zhou, Bei Xia	Parameter and UVM, making a layered testbench powerful.	ASICON	2013	DBLP DOI BibTeX RDF
24	Matteo Morelli, Federico Moro, Tizar Rizano, Daniele Fontanelli, Luigi Palopoli 0002, Marco Di Natale	A robotic vehicle testbench for the application of MBD-MDE development technologies.	ETFA	2013	DBLP DOI BibTeX RDF
24	Saif Uddin, Johnny Öberg	Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach.	NORCHIP	2012	DBLP DOI BibTeX RDF
24	Giuseppe Di Guglielmo, Graziano Pravadelli	A testbench specification language for SystemC verification.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
24	Zhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon	Practical and efficient SOC verification flow by reusing IP testcase and testbench.	ISOCC	2012	DBLP DOI BibTeX RDF
24	Namdo Kim, Young-Nam Yun, Young-Rae Cho, Jay B. Kim, Byeong Min	How to automate millions lines of top-level UVM testbench and handle huge register classes.	ISOCC	2012	DBLP DOI BibTeX RDF
24	Takushi Hashida, Yuuki Araga, Makoto Nagata	A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
24	Chin-Lung Chuang, Chien-Nan Jimmy Liu	Hybrid Testbench Acceleration for Reducing Communication Overhead.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF
24	James O. Owuor, Josiah L. Munda, Adisa A. Jimoh	The ieee 34 node radial test feeder as a simulation testbench for Distributed Generation.	AFRICON	2011	DBLP DOI BibTeX RDF
24	Mehdi Dehbashi, André Sülflow, Görschwin Fey	Automated Design Debugging in a Testbench-Based Verification Environment.	DSD	2011	DBLP DOI BibTeX RDF
24	Mario Westmeier, Benjamin Herwig, Josef Börcsök	Enhancing a simulation environment for computer architecture to a SystemC based testbench tool for design verification.	ICAT	2011	DBLP DOI BibTeX RDF
24	Peter Lisherness, Kwang-Ting (Tim) Cheng	Coverage discounting: A generalized approach for testbench qualification.	HLDVT	2011	DBLP DOI BibTeX RDF
24	Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Ping Li 0024	A new event driven testbench synthesis engine for FPGA emulation.	ASICON	2011	DBLP DOI BibTeX RDF
24	Takushi Hashida, Yuuki Araga, Makoto Nagata	A diagnosis testbench of analog IP cores against on-chip environmental disturbances.	VTS	2011	DBLP DOI BibTeX RDF
24	Mile K. Stojcev	Navabi Zainalabedin, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, & Verification (second ed.), McGraw Hill, New York (2006) ISBN 0-07-144564-1 Hardcover, pp 384, plus XVI.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
24	Joseph W. Lyles Jr.	Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor.	MTV	2008	DBLP DOI BibTeX RDF
24	Kana Murale, Scot Hildebrandt, Per Bojsen, Alfonso Urzua	AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator.	MTV	2008	DBLP DOI BibTeX RDF
24	Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg	Panel: Software practices for verification/testbench management.	HLDVT	2008	DBLP DOI BibTeX RDF
24	Iakovos Mavroidis, Ioannis Papaefstathiou	Accelerating hardware simulation: Testbench code emulation.	FPT	2008	DBLP DOI BibTeX RDF
24	Michel Pignol, Thierry Parrain, Vincent Claverie, Christian Boléat, Guy Estaves	Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448.	IOLTS	2008	DBLP DOI BibTeX RDF
24	Martin Zambaldi	Concepts for the development of a generic multi-level testbench covering different areas of application.		2008	RDF
24	Martin Horn, Josef Zehetner	A Brake-Testbench for Research and Education.	CCA	2007	DBLP DOI BibTeX RDF
24	Stephan Kubisch, Harald Widiger, Ronald Hecht, Dirk Timmermann, Martin Siemroth	Architektur einer flexiblen, wiederverwendbaren Testbench zur Verifikation paketverarbeitender Hardware in SystemC.	MBMV	2007	DBLP BibTeX RDF
24	Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler	Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques.	FDL	2007	DBLP BibTeX RDF
24	Staffan Berg	Algorithmic Test Generation - a New Approach to testbench Creation.	FDL	2007	DBLP BibTeX RDF
24	Takahito Nakajima, Shigeru Namiki, Shuhei Kinoshita, Naohiko Shimizu	A Portable Co-Verification System Which Generates Testbench Automatically.	FPT	2007	DBLP DOI BibTeX RDF
24	Dierk Engelhardt, Tilo Linz	TestBench meets TestFrame: State of the Art Testdesign.	Softwaretechnik-Trends	2006	DBLP BibTeX RDF
24	Anton Schlatter	TestFrame meets TestBench: State of the Art Testautomatisierung.	Softwaretechnik-Trends	2006	DBLP BibTeX RDF
24	Jungbo Son, Hae-Wook Choi, Sin-Chong Park	Accelerating Verification with Reusable Testbench.	IEICE Trans. Inf. Syst.	2006	DBLP DOI BibTeX RDF
24	Ho-Seok Choi, Hae-Wook Choi, Sin-Chong Park	Instruction Based Synthesizable Testbench Architecture.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
24	Janusz Sosnowski, Piotr Gawkowski, Przemyslaw Zygulski, Andrzej Tymoczko	Enhancing Fault Injection Testbench.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
24	Anshul Singh, Scott C. Smith	Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation.	CDES	2005	DBLP BibTeX RDF
24	Young-Il Kim, Chong-Min Kyung	TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
24	David Hunter	Some lessons learned on constructing an automated testbench for evolvable hardware experiments.	IEEE Congress on Evolutionary Computation	2004	DBLP DOI BibTeX RDF
24	Cordula Hansen, Wolfgang Rosenstiel	High Level Testbench Transformation for Pipelined Components.	MBMV	2002	DBLP BibTeX RDF