Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Martin Zambaldi, Wolfgang Ecker |
Re-use-centric architecture for a fully accelerated testbench environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 372-375, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hardware testbench, acceleration, functional verification |
111 | Kelly D. Larson |
Translation of an existing VMM-based SystemVerilog testbench to OVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 237, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
OVM, VMM, testbenches, SystemVerilog |
111 | Young-Il Kim, Chong-Min Kyung |
Automatic translation of behavioral testbench for fully accelerated simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 218-221, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
105 | Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi |
Property-Specific Testbench Generation for Guided Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 524-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
guided simulation, intelligent testbench generation, witness graph, property-specific testbench, approximate model checking, symbolic model checking, iterative refinement |
72 | Görschwin Fey, Rolf Drechsler |
Improving simulation-based verification by means of formal methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 640-643, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Ioannis Mavroidis, Ioannis Papaefstathiou |
Efficient testbench code synthesis for a hardware emulator system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 888-893, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Aman Kokrady, Theo J. Powell, S. Ramakrishnan |
Reducing Design Verification Cycle Time through Testbench Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 243-248, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Stanislaw Deniziak, Krzysztof Sapiecha |
High Level Testbench Generation for VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 6th Symposium on Engineering of Computer-Based Systems (ECBS '99), 7-12 March 1999, Nashville, TN, USA. IEEE Computer Society, 1999, pp. 146-151, 1999, IEEE Computer Society, 0-7695-0028-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
simulation, VHDL, testbench |
43 | Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung |
Communication-efficient hardware acceleration for fast functional simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 293-298, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
functional verification, communication overhead, simulation acceleration |
43 | Matthias Bauer 0003, Wolfgang Ecker, Renate Henftling, Andreas Zinn |
A Method for Accelerating Test Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1477-1480, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard |
Maintaining consistency between systemC and RTL system designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 85-89, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SPIRIT, transactor, verification, systemC, RTL, TLM, testbench, VIP |
38 | Mark H. Nodine |
Automatic Testbench Generation for Rearchitected Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 128-136, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang |
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 327-332, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification strategy, optimization, functional verification, coverage analysis, hierarchical verification |
38 | Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park |
Instruction Based Testbench Architecture, invited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 329-333, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta |
An automatic testbench generation tool for a SystemC functional verification methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 66-70, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Brazilip, SCV, VeriSC, tool, SystemC |
38 | Renate Henftling, Andreas Zinn, Matthias Bauer 0003, Wolfgang Ecker, Martin Zambaldi |
Platform-Based Testbench Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11038-11045, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang |
A PD-based methodology to enhance efficiency in testbenches with random stimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis |
29 | Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang |
RT-level vector selection for realistic peak power simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 576-581, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
peak power estimation, vector selection, power modeling |
29 | Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil |
TLM: Crossing Over From Buzz To Adoption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 444-445, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Alexander Krupp, Wolfgang Müller 0003 |
Classification trees for random tests and functional coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1031-1032, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Sanggyu Park, Soo-Ik Chae |
A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 237-239, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Sylvain Huet, Emmanuel Casseau, Olivier Pasquier |
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 240-243, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero |
Automatic Test Program Generation: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(2), pp. 102-109, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Mark Litterick, Joachim Geishauser |
Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 64-78, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Christian Stangier, Ulrich Holtmann |
Applying Formal Verification with Protocol Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 165-169, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Brian Bailey |
Was it worth the wait? Yes! ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(2), pp. 160-161, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
verification, formal verification, design reuse, testbench, SystemVerilog |
26 | Indradeep Ghosh, Srivaths Ravi 0001 |
On automatic generation of RTL validation test benches using circuit testing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 289-294, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage |
26 | Kanna Shimizu, David L. Dill |
Deriving a simulation input generator and a coverage metric from a formal specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 801-806, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
BDD minimization, input generation, coverage, testbench |
24 | Nikolas J. Wilhelm, Constantin von Deimling, Sami Haddadin, Claudio Glowalla, Rainer Burgkart |
Validation of a Robotic Testbench for Evaluating Biomechanical Effects of Implant Rotation in Total Knee Arthroplasty on a Cadaveric Specimen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(17), pp. 7459, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Ismael, Ayman Hroub, Abdellatif Abu-Issa |
AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2023, Abu Dhabi, United Arab Emirates, December 17-20, 2023, pp. 162-167, 2023, IEEE, 979-8-3503-8082-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Hasan Tariq, Mohammed Alsageer, Tamer Khattab, Farid Touati |
Autonomous SkyCube Testbench using UAV-Assisted Ka-Band OFDM Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: International Wireless Communications and Mobile Computing, IWCMC 2023, Marrakesh, Morocco, June 19-23, 2023, pp. 780-785, 2023, IEEE, 979-8-3503-3339-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Rikard Gannedahl, Javad Bagheri Asli, Henrik Sjöland, Atila Alvandpour |
A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Antonio González-Morgado, Guillermo Heredia, Aníbal Ollero |
An Open-Source, Low-Cost UAV Testbench for Educational Purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ROBOT (2) ![In: Robot 2023: Sixth Iberian Robotics Conference - Advances in Robotics, Volume 2, Coimbra, Portugal, 22-24 November 2023., pp. 539-550, 2023, Springer, 978-3-031-59166-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Luke R. Upton, Guénolé Lallement, Michael D. Scott 0002, Joyce Taylor, Robert M. Radway, Dennis Rich, Mark Nelson, Subhasish Mitra, Boris Murmann |
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3475-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Abhishek Sanjeev Chandgaonkar, Vaishali Ingale, Vinay Patil, Vanita Agarwal |
Development Of SV UVM Testbench For Verification Of AMBA AXI3 IP Used For Memory Access Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Shreyash Naresh Chauhan, Ganesh K. Andurkar |
Development of UVM Testbench for I3C protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ruolin Wang, Yuejiao Xu, Jie Peng, Jianmin Ji |
A²CoST: An ASP-based Avoidable Collision Scenario Testbench for Autonomous Vehicles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KR ![In: Proceedings of the 20th International Conference on Principles of Knowledge Representation and Reasoning, KR 2023, Rhodes, Greece, September 2-8, 2023., pp. 690-699, 2023, 978-1-956792-02-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis |
A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDAACS ![In: 12th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS 2023, Dortmund, Germany, September 7-9, 2023, pp. 674-679, 2023, IEEE, 979-8-3503-5805-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Valentin Baier, Michael Schardt, Maximilian Fink, Martin Jakobi, Alexander W. Koch |
MEMS-Scanner Testbench for High Field of View LiDAR Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(1), pp. 39, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Haopeng Chen, Steffen Müller 0002 |
Analysis of Real-Time LiDAR Sensor Simulation for Testing Automated Driving Functions on a Vehicle-in-the-Loop Testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IV ![In: 2022 IEEE Intelligent Vehicles Symposium, IV 2022, Aachen, Germany, June 4-9, 2022, pp. 1605-1614, 2022, IEEE, 978-1-6654-8821-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang 0001, Xuan Zeng 0001, Dian Zhou |
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 86-91, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Alessio Paolo Buccino, Gaute T. Einevoll |
MEArec: A Fast and Customizable Testbench Simulator for Ground-truth Extracellular Spiking Activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neuroinformatics ![In: Neuroinformatics 19(1), pp. 185-204, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Jorge Jiménez, Antoni Grau, Cristobal Padilla |
Integration of a Testbench for the Optical and Thermal Characterization of Near-Infrared Detectors Used in Ground and Space-Based Astronomy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 70, pp. 1-7, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Harsh Bhargav, Vineesh V. S., Binod Kumar 0001, Virendra Singh |
Enhancing Testbench Quality via Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021, pp. 652-656, 2021, IEEE, 978-1-6654-2461-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Aditya Kulkarni, Ayush Singh, Sachin Arun Waje, Sunil Shrirangrao Kashide, Seonil Brian Choi |
TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021, pp. 106-111, 2021, IEEE, 978-1-6654-2931-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Selim Solmaz, Franz R. Holzinger |
A Novel Testbench for Development, Calibration and Functional Testing of ADAS/AD Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCVE ![In: 2019 IEEE International Conference on Connected Vehicles and Expo, ICCVE 2019, Graz, Austria, November 4-8, 2019, pp. 1-8, 2019, IEEE, 978-1-7281-0142-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Youngnam Han |
5G K-Simulator and TestBench Demonstration Proposal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCNC ![In: 16th IEEE Annual Consumer Communications & Networking Conference, CCNC 2019, Las Vegas, NV, USA, January 11-14, 2019, pp. 1-2, 2019, IEEE, 978-1-5386-5553-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Vineeth B, B. Bala Tripura Sundari |
UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2018 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2018, Bangalore, India, September 19-22, 2018, pp. 307-310, 2018, IEEE, 978-1-5386-5314-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Jigar Savla |
Getting Started on Co-Emulation: Transition your Design and Testbench to an Emulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 19th International Workshop on Microprocessor and SOC Test and Verification, MTV 2018, Austin, TX, USA, December 9-10, 2018, pp. 46-51, 2018, IEEE, 978-1-5386-9250-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Slimane Boutobza, Sorin Popa, Andrea Costa |
An Automatic Testbench Generator for Test Patterns Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2018 IEEE East-West Design & Test Symposium, EWDTS 2018, Kazan, Russia, September 14-17, 2018, pp. 1-11, 2018, IEEE, 978-1-5386-5710-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Hassan 0002, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler |
Testbench qualification for SystemC-AMS timed data flow models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 857-860, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Khaled Salah 0001, Hassan Mostafa |
Constructing Effective UVM Testbench for DRAM Memory Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NGCAS ![In: 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018, pp. 178-181, 2018, IEEE, 978-1-5386-7681-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Nicole Fern, Kwang-Ting Cheng |
Mining mutation testing simulation traces for security and testbench debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 714-721, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Neeraj Bokde, Kishore Kulat |
R package imputeTestbench as a Testbench to compare missing value imputation methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1608.00476, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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24 | Ahmed El-Naggar, Essraa Massoud, Ahmed Medhat, Hala Ibrahim, Bassma Al-Abassy, Sameh El-Ashry, Mostafa Khamis, Ahmed Shalaby 0001 |
A narrative of UVM testbench environment for interconnection routers: A practical approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 11th International Design & Test Symposium, IDT 2016, Hammamet, Tunisia, December 18-20, 2016, pp. 98-103, 2016, IEEE, 978-1-5090-4900-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Ralph Weissnegger, Markus Pistauer, Christian Kreiner, Markus Schuß, Kay Römer, Christian Steger |
Automatic Testbench Generation for Simulation-based Verification of Safety-critical Systems in UML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PECCS ![In: Proceedings of the 6th International Joint Conference on Pervasive and Embedded Computing and Communication Systems (PECCS 2016), Lisbon, Portugal, July 25-27, 2016., pp. 70-75, 2016, SciTePress, 978-989-758-195-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Kai Huang 0002, Peng Zhu, Rongjie Yan, Xiaolang Yan |
Functional Testbench Qualification by Mutation Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2015, pp. 256474:1-256474:9, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Eman El Mandouh, Amr G. Wassal |
Guiding intelligent testbench automation using data mining and formal methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015, pp. 60-65, 2015, IEEE, 978-1-4673-9994-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Mohamed Abdelsalam, Ashraf Salem |
SoC verification platforms using HW emulation and co-modeling Testbench technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015, pp. 14-19, 2015, IEEE, 978-1-4673-9994-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Graziella Scandurra, Gianluca Cannatà, Gino Giusi, Carmine Ciofi |
A simple and effective testbench for quartz tuning fork characterization and sensing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
I2MTC ![In: 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, Pisa, Italy, May 11-14, 2015, pp. 1871-1876, 2015, IEEE, 978-1-4799-6114-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Dong Gwan Lee, Kil Seok Cho, Jin Hwa Shin |
A simple prediction method of ballistic missile trajectory to designate search direction and its verification using a testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASCC ![In: 10th Asian Control Conference, ASCC 2015, Kota Kinabalu, Malaysia, May 31 - June 3, 2015, pp. 1-7, 2015, IEEE, 978-1-4799-7862-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli |
Testbench Qualification of SystemC TLM Protocols through Mutation Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 63(5), pp. 1248-1261, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Somnath Banerjee 0003, Tushar Gupta |
Optimized Simulation Acceleration with Partial Testbench Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014, pp. 22-27, 2014, IEEE Computer Society, 978-1-4673-6858-2. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Lucas Cicero, Camel Tanougast, Harry Ramenah, Loïc Siéler, F. Lecerf |
A Li-Ion cell testbench for fast characterization and modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoDIT ![In: International Conference on Control, Decision and Information Technologies, CoDIT 2014, Metz, France, November 3-5, 2014, pp. 562-565, 2014, IEEE, 978-1-4799-6773-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Mehdi Dehbashi, André Sülflow, Görschwin Fey |
Automated design debugging in a testbench-based verification environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(2), pp. 206-217, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Geng Zhong, Jian Zhou, Bei Xia |
Parameter and UVM, making a layered testbench powerful. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-6415-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Matteo Morelli, Federico Moro, Tizar Rizano, Daniele Fontanelli, Luigi Palopoli 0002, Marco Di Natale |
A robotic vehicle testbench for the application of MBD-MDE development technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETFA ![In: Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, ETFA 2013, Cagliari, Italy, September 10-13, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0864-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Saif Uddin, Johnny Öberg |
Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, pp. 1-5, 2012, IEEE, 978-1-4673-2221-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Giuseppe Di Guglielmo, Graziano Pravadelli |
A testbench specification language for SystemC verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012, pp. 333-342, 2012, ACM, 978-1-4503-1426-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Zhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon |
Practical and efficient SOC verification flow by reusing IP testcase and testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 175-178, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Namdo Kim, Young-Nam Yun, Young-Rae Cho, Jay B. Kim, Byeong Min |
How to automate millions lines of top-level UVM testbench and handle huge register classes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 405-407, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Takushi Hashida, Yuuki Araga, Makoto Nagata |
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(6), pp. 1016-1023, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Chin-Lung Chuang, Chien-Nan Jimmy Liu |
Hybrid Testbench Acceleration for Reducing Communication Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 28(2), pp. 40-51, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | James O. Owuor, Josiah L. Munda, Adisa A. Jimoh |
The ieee 34 node radial test feeder as a simulation testbench for Distributed Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFRICON ![In: AFRICON 2011, Victoria Falls, Livingstone, Zambia, September 13-15, 2011, pp. 1-6, 2011, IEEE, 978-1-61284-992-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Mehdi Dehbashi, André Sülflow, Görschwin Fey |
Automated Design Debugging in a Testbench-Based Verification Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 479-486, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Mario Westmeier, Benjamin Herwig, Josef Börcsök |
Enhancing a simulation environment for computer architecture to a SystemC based testbench tool for design verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAT ![In: XXIII International Symposium on Information, Communication and Automation Technologies, ICAT 2011, Sarajevo, Bosnia and Herzegovina, October 27-29, 2011, pp. 1-6, 2011, IEEE, 978-1-4577-0744-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Peter Lisherness, Kwang-Ting (Tim) Cheng |
Coverage discounting: A generalized approach for testbench qualification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011, pp. 49-56, 2011, IEEE Computer Society, 978-1-4577-1744-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Ping Li 0024 |
A new event driven testbench synthesis engine for FPGA emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 373-376, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Takushi Hashida, Yuuki Araga, Makoto Nagata |
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 70-75, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Mile K. Stojcev |
Navabi Zainalabedin, Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, & Verification (second ed.), McGraw Hill, New York (2006) ISBN 0-07-144564-1 Hardcover, pp 384, plus XVI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 48(1), pp. 167-168, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Joseph W. Lyles Jr. |
Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008, pp. 3-6, 2008, IEEE Computer Society, 978-0-7695-3581-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Kana Murale, Scot Hildebrandt, Per Bojsen, Alfonso Urzua |
AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008, pp. 81-87, 2008, IEEE Computer Society, 978-0-7695-3581-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg |
Panel: Software practices for verification/testbench management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: IEEE International High Level Design Validation and Test Workshop, HLDVT 2008, Incline Village, NV, USA, November 19-21, 2008, pp. 35-37, 2008, IEEE Computer Society, 978-1-4244-2922-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Iakovos Mavroidis, Ioannis Papaefstathiou |
Accelerating hardware simulation: Testbench code emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008, pp. 129-136, 2008, IEEE, 978-1-4244-2796-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Michel Pignol, Thierry Parrain, Vincent Claverie, Christian Boléat, Guy Estaves |
Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 182-184, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Martin Zambaldi |
Concepts for the development of a generic multi-level testbench covering different areas of application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
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24 | Martin Horn, Josef Zehetner |
A Brake-Testbench for Research and Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCA ![In: Proceedings of the IEEE International Conference on Control Applications, CCA 2007, Singapore, October 1-3, 2007, pp. 444-448, 2007, IEEE, 978-1-4244-0442-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Stephan Kubisch, Harald Widiger, Ronald Hecht, Dirk Timmermann, Martin Siemroth |
Architektur einer flexiblen, wiederverwendbaren Testbench zur Verifikation paketverarbeitender Hardware in SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007, pp. 9-18, 2007, Shaker, 978-3-8322-5956-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
24 | Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, pp. 146-151, 2007, ECSI. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
24 | Staffan Berg |
Algorithmic Test Generation - a New Approach to testbench Creation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, pp. 152-158, 2007, ECSI. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
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24 | Takahito Nakajima, Shigeru Namiki, Shuhei Kinoshita, Naohiko Shimizu |
A Portable Co-Verification System Which Generates Testbench Automatically. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007, pp. 345-348, 2007, IEEE, 1-4244-1472-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Dierk Engelhardt, Tilo Linz |
TestBench meets TestFrame: State of the Art Testdesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softwaretechnik-Trends ![In: Softwaretechnik-Trends 26(2), 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
24 | Anton Schlatter |
TestFrame meets TestBench: State of the Art Testautomatisierung. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softwaretechnik-Trends ![In: Softwaretechnik-Trends 26(2), 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
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24 | Jungbo Son, Hae-Wook Choi, Sin-Chong Park |
Accelerating Verification with Reusable Testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 89-D(2), pp. 853-856, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Ho-Seok Choi, Hae-Wook Choi, Sin-Chong Park |
Instruction Based Synthesizable Testbench Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(5), pp. 653-657, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Janusz Sosnowski, Piotr Gawkowski, Przemyslaw Zygulski, Andrzej Tymoczko |
Enhancing Fault Injection Testbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DepCoS-RELCOMEX ![In: 2006 International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX 2006), 24-28 May 2006, Szklarska Poreba, Poland, pp. 76-83, 2006, IEEE Computer Society, 0-7695-2565-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Anshul Singh, Scott C. Smith |
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 115-121, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
24 | Young-Il Kim, Chong-Min Kyung |
TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(6), pp. 484-493, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | David Hunter |
Some lessons learned on constructing an automated testbench for evolvable hardware experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2004, 19-23 June 2004, Portland, OR, USA, pp. 1808-1812, 2004, IEEE, 0-7803-8515-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Cordula Hansen, Wolfgang Rosenstiel |
High Level Testbench Transformation for Pipelined Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Tübingen, Germany, February 25-27, 2002, pp. 124-133, 2002, Shaker. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|