Search results for "x-by-wire"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
95	Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	SPFD-based wire removal in standard-cell and network-of-PLA circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
89	Chung-Ping Chen, D. F. Wong 0001	Optimal Wire-Sizing Function with Fringing Capacitance Consideration.	DAC	1997	DBLP DOI BibTeX RDF
86	Hongbo Zhang 0001, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng	Wire shaping is practical.	ISPD	2009	DBLP DOI BibTeX RDF	manufacturing for design, wire tapering, interconnect, opc, power minimization
77	Jason Cong, David Zhigang Pan	Wire width planning for interconnect performance optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
77	Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay	Interconnect synthesis without wire tapering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
77	Chris C. N. Chu, Martin D. F. Wong	A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
77	Zhong-Zhen Wu, Shih-Chieh Chang	Multiple wire reconnections based on implication flow graph.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
74	Chris C. N. Chu, D. F. Wong 0001	A new approach to simultaneous buffer insertion and wire sizing.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
73	Paul M. Antoszczyszyn, John M. Hannah, Peter M. Grant	A Comparison of Detailed Automatic Wire-Frame Fitting Methods.	ICIP (1)	1997	DBLP DOI BibTeX RDF	detailed automatic wire-frame fitting methods, semantic wire-frame fitting methods, extremely low bit-rate model-based moving image communication systems, lips, nose, transmitted scene, facial code-book, Candide wire-frame model, videophone scene, head-and-shoulders, MIT facial data-base, reconstruction, eyes, facial features, videotelephony
68	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
68	Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska	Wire length prediction in constraint driven placement.	SLIP	2003	DBLP DOI BibTeX RDF	wire length prediction, clustering
65	Theo van Walsum, Shirley A. M. Baert, Wiro J. Niessen	Guide wire reconstruction and visualization in 3DRA using monoplane fluoroscopic imaging.	IEEE Trans. Medical Imaging	2005	DBLP DOI BibTeX RDF
65	Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.	ICCD	2000	DBLP DOI BibTeX RDF
65	Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001	Optimal non-uniform wire-sizing under the Elmore delay model.	ICCAD	1996	DBLP DOI BibTeX RDF	Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation
65	S. Sakurai, Takafumi Aoki, Tatsuo Higuchi 0001	Wire-Free Computing Circuits Using Optical Wave-Casting.	ISMVL	1995	DBLP DOI BibTeX RDF	wire-free computing circuits, optical wave-casting, interconnection problems, information carriers, wire-free logic circuits, fully parallel visual processing system, parallel processing, parallel processing, multiprocessor interconnection networks, logic circuits
65	Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal	Computing area and wire length efficient routes for channels.	VLSI Design	1995	DBLP DOI BibTeX RDF	area efficient routes, wire length efficient routes, total wire length reduction, multilayer routing solutions, computational complexity, VLSI, NP-hard, polynomial time algorithms, network routing, circuit layout CAD, minimisation, VLSI layout, integrated circuit layout, channel routing
62	Ki-Jin Kim, Kwang-Ho Ahn, T. H. Lim	Low Phase Noise Bond Wire VCO for DVB-H.	DELTA	2008	DBLP DOI BibTeX RDF	bond wire, low phase noise, DVB-H
62	Narender Hanchate, Nagarajan Ranganathan	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
60	Dongsheng Wang 0012, Ping Zhang 0001, Chung-Kuan Cheng, Arunabha Sen	A Performance-Driven I/O Pin Routing Algorithm.	ASP-DAC	1999	DBLP DOI BibTeX RDF
59	Wen-Ting Wu, Jyh-Cheng Chen, Kai-Hsiu Chen, Kuo-Pao Fan	Design and implementation of WIRE Diameter.	ITRE	2005	DBLP DOI BibTeX RDF
59	Chris C. N. Chu, D. F. Wong 0001	Greedy wire-sizing is linear time.	ISPD	1998	DBLP DOI BibTeX RDF
58	Toshiyuki Hama, Hiroaki Etoh	Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
56	Tan Yan, Hiroshi Murata	Fast wire length estimation by net bundling for block placement.	ICCAD	2006	DBLP DOI BibTeX RDF	net bundling, wire length estimation, lookup table
55	Ronald I. Greenberg	The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	fat pyramid, universal parallel computation, wire delay, processor size, unit wire delay, routing networks, simulation, parallel computation, parallel architectures, multiprocessor interconnection networks, universality, fat-tree, wire length
53	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
53	Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang	Width and Timing-Constrained Wire Sizing for Critical Area Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
53	Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska	Individual wire-length prediction with application to timing-driven placement.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
53	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Is wire tapering worthwhile?	ICCAD	1999	DBLP DOI BibTeX RDF
53	Chris C. N. Chu, D. F. Wong 0001	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
51	Zhuo Li 0001, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
51	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
51	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry.	SLIP	2005	DBLP DOI BibTeX RDF	wire-length distribution model, routing, interconnect, rent
51	Hye Won Pyun	3D Game Engine for Real-Time Facial Animation.	Australian Conference on Artificial Intelligence	2005	DBLP DOI BibTeX RDF	multiple face models, wire deformation, local deformation, Real-time facial animation
50	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
50	Dirk Stroobandt	Multi-terminal nets do change conventional wire length distribution models.	SLIP	2001	DBLP DOI BibTeX RDF	multi-terminal nets, wire length estimation, Rent's rule
50	Youxin Gao, D. F. Wong 0001	Optimal shape function for a bi-directional wire under Elmore delay model.	ICCAD	1997	DBLP DOI BibTeX RDF	Bi-directional wire, Optimal shape, Elmore Delay
50	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
48	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano	Three-Dimensional Layout of On-Chip Tree-Based Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
48	Brock J. LaMeres, Sunil P. Khatri	Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.	ICCD	2005	DBLP DOI BibTeX RDF
48	Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail	Physical limitations on the bit-rate of on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	damping factor, delay, interconnects, bit-rate
47	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
47	Yingbin Liang, Gerhard Kramer, H. Vincent Poor, Shlomo Shamai	Recent results on compound wire-tap channels.	PIMRC	2008	DBLP DOI BibTeX RDF
47	Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi	Wire Sizing for Non-Tree Topology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
47	Michael Armbruster, Erik Zimmer, Matthias Lehmann, Reinhard Reichel, E. Sieglin, Gernot Spiegelberg, Armin Sulzmann	Affordable X-By-Wire technology based on an innovative, scalable E/E platform-concept.	VTC Spring	2006	DBLP DOI BibTeX RDF
47	Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee	Timing-constrained yield-driven wire sizing for critical area minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
47	T. N. Vijaykumar, Zeshan Chishti	Wire Delay is Not a Problem for SMT (In the Near Future).	ISCA	2004	DBLP DOI BibTeX RDF
47	Shirley A. M. Baert, Wiro J. Niessen	2D Guide Wire Tracking during Endovascular Interventions.	MICCAI (2)	2002	DBLP DOI BibTeX RDF
47	Shih-Chieh Chang, Zhong-Zhen Wu	Theorems and extensions of single wire replacement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
47	Sotiris Malassiotis, Michael G. Strintzis	Optimal biorthogonal wavelet decomposition of wire-frame meshes using box splines, and its application to the hierarchical coding of 3-D surfaces.	IEEE Trans. Image Process.	1999	DBLP DOI BibTeX RDF
47	Susanne Braun, Marcus Trapp, Claudia Nass, Matthias Gerbershagen, Stefan Schweitzer, Rodrigo Falcão, Matthias Naab, Markus Schweitzer, Torsten Kreutzer, Nikolaus Wire	Insights collaboration space: a team collaboration app for the design of data-driven services.	MoDELS (Companion)	2020	DBLP DOI BibTeX RDF
47	Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung 0001, Monica Lam 0001, Margie Levine, Brian Moore 0004, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb	Supporting Systolic and Memory Communciation in iWarp.	ISCA	1990	DBLP DOI BibTeX RDF
45	Hae Won Byun	Multimedia Authoring Tool for Real-Time Facial Animation.	MCAM	2007	DBLP DOI BibTeX RDF	multiple face models, wire deformation, local deformation, real-time facial animation
45	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani	How does partitioning matter for 3D floorplanning?	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	partitioning, floorplanning, 3D IC, wire length
44	Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang	Redundant via insertion with wire bending.	ISPD	2009	DBLP DOI BibTeX RDF	redundant via, wire bending, integer linear program
44	Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu	Adaptable wire-length distribution with tunable occupation probability.	SLIP	2007	DBLP DOI BibTeX RDF	wire-length distribution, rent's rule
44	Peng Liu 0024, Dingsheng Liu, Fang Huang 0001	MTF Measurement Based on Interactive Live-Wire Edge Extraction.	International Conference on Computational Science (2)	2007	DBLP DOI BibTeX RDF	MTF measurement, interactive Live-wire edge extraction, sharp edge
44	Dong Gun Kam, Joungho Kim, Jiheon Yu, Ho Choi, Kicheol Bae, Choonheung Lee	Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	wire bonded plastic ball grid array, WB-PBGA, 40 Gb/s Serial Link, chip-to-chip serial link, SiP, System-in-Package
44	Qinghua Liu, Malgorzata Marek-Sadowska	Wire length prediction-based technology mapping and fanout optimization.	ISPD	2005	DBLP DOI BibTeX RDF	prediction, congestion, wire length
44	Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel	A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool.	SLIP	2005	DBLP DOI BibTeX RDF	3-D FPGA, wire resource prediction
44	Brian Stephen Smith, Sung Kyu Lim	QCA channel routing with wire crossing minimization.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	QCA channel routing, weighted minimum feedback edge set, wire crossing minimization
44	Vidyasagar Nookala, Sachin S. Sapatnekar	A method for correcting the functionality of a wire-pipelined circuit.	DAC	2004	DBLP DOI BibTeX RDF	synchronous design, wire pipelining
44	Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie	Stochastic wire length sampling for cycle time estimation.	SLIP	2002	DBLP DOI BibTeX RDF	cycle time estimates, wire sampling, performance modeling, physical design
44	Chris C. N. Chu, D. F. Wong 0001	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
42	Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin	Datapath and control for quantum wires.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Architecture, Control, Layout
42	Stephen E. Krufka, Phillip Christie	Terminal optimization analysis for functional block re-use.	SLIP	2002	DBLP DOI BibTeX RDF	optimization, SoC, interconnect, Rent's rule
41	Markus Krug 0004, Anton V. Schedl	New demands for invehicle networks.	EUROMICRO	1997	DBLP DOI BibTeX RDF	in-vehicle communication networks, brake-by-wire system, steer-by-wire system, fault-tolerant communication systems, safety-critical applications, automotive electronics
41	Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono	Robust PD Control Using Adaptive Compensation for Completely Restrained Parallel-Wire Driven Robots: Translational Systems Using the Minimum Number of Wires Under Zero-Gravity Condition.	IEEE Trans. Robotics	2007	DBLP DOI BibTeX RDF
41	Min Ni, Seda Ogrenci Memik	Self-heating-aware optimal wire sizing under Elmore delay model.	DATE	2007	DBLP DOI BibTeX RDF
41	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	TROY: Track Router with Yield-driven Wire Planning.	DAC	2007	DBLP DOI BibTeX RDF
41	Qinghua Liu, Malgorzata Marek-Sadowska	Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri	Wire density driven global routing for CMP variation and timing.	ICCAD	2006	DBLP DOI BibTeX RDF	performance, VLSI, manufacturability, global routing
41	S. P. Shang, Xiaodong Hu 0001, Tong Jing	Average lengths of wire routing under M-architecture and X-architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
41	Shirley A. M. Baert, Graeme P. Penney, Theo van Walsum, Wiro J. Niessen	Precalibration Versus 2D-3D Registration for 3D Guide Wire Display in Endovascular Interventions.	MICCAI (2)	2004	DBLP DOI BibTeX RDF
41	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	An analysis of the wire-load model uncertainty problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
41	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
41	Song-Ra Pan, Yao-Wen Chang	Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.	ICCD	2000	DBLP DOI BibTeX RDF
41	Youxin Gao, D. F. Wong 0001	Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF
41	John P. Fishburn	Shaping a VLSI wire to minimize Elmore delay.	ED&TC	1997	DBLP DOI BibTeX RDF
41	Charles J. Alpert, Anirudh Devgan	Wire Segmenting for Improved Buffer Insertion.	DAC	1997	DBLP DOI BibTeX RDF
41	Penny J. Davies, Dugald B. Duncan	Time-marching numerical schemes for the electric field integral equation on a straight thin wire.	Adv. Comput. Math.	1994	DBLP DOI BibTeX RDF	AMS(MOS) subject classification 65M10, 65M25, 78A45, 65R20
39	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	Congestion-driven codesign of power and signal networks.	DAC	2002	DBLP DOI BibTeX RDF	signal routing, wire congestion, codesign, power grid noise
39	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
38	Fanzhi Kong, Yizhong Wang	Study on the Fast Matching Location Algorithm Based on Feature Points for Wire Bonding.	ISIP	2008	DBLP DOI BibTeX RDF	wire bonding, feature points matching, SIFT, PRS
38	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
38	Takahiro Endo, Yuki Kawachi, Haruhisa Kawasaki, Tetsuya Mouri	FPGA-Based Control for the Wire-Saving of Five-Fingered Haptic Interface.	EuroHaptics	2008	DBLP DOI BibTeX RDF	wire-saving control system, FPGA, Haptic interface
38	Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli	Early wire characterization for predictable network-on-chip global interconnects.	SLIP	2007	DBLP DOI BibTeX RDF	early wire characterization, design methodology, NoCs, global interconnects
38	Naim Bajçinca, Rui Cortesão, Markus Hauschild	Robust Control for Steer-by-Wire Vehicles.	Auton. Robots	2005	DBLP DOI BibTeX RDF	steer-by-wire, inverse disturbance observer, active observer, robust control, force control, model-matching, robustness analysis
38	Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu	Wire Length Distribution Model Considering Core Utilization for System on Chip.	ISVLSI	2005	DBLP DOI BibTeX RDF	Wire Length Distribution, core utilization, layout-area allocation, SoC
38	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
38	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
38	Hua Xiang 0001, I-Min Liu, Martin D. F. Wong	Wire Planning with Bounded Over-the-Block Wires.	ISQED	2005	DBLP DOI BibTeX RDF	over-the-block, wire planning, routing
38	Qinghua Liu, Malgorzata Marek-Sadowska	Pre-layout wire length and congestion estimation.	DAC	2004	DBLP DOI BibTeX RDF	prediction, congestion, wire length
38	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
38	Greg Eisenhauer, Fabián E. Bustamante, Karsten Schwan	Native Data Representation: An Efficient Wire Format for High-Performance Distributed Computing.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	wire format, communication, distributed computing, High-performance
36	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	Track Routing and Optimization for Yield.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
36	Tao Luo 0002, David Z. Pan	DPlace2.0: A stable and efficient analytical placement based on diffusion.	ASP-DAC	2008	DBLP DOI BibTeX RDF
36	Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.	ISQED	2007	DBLP DOI BibTeX RDF
36	Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu	On handling the fixed-outline constraints of floorplanning using less flexibility first principles.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Ron Ho	High-performance ULSI: the real limiter to interconnect scaling.	SLIP	2005	DBLP DOI BibTeX RDF	VLSI, wireless, 3D, scaling, proximity, repeaters, wires
36	Matthew Moe, Herman Schmit	Floorplanning of pipelined array modules using sequence pairs.	ISPD	2003	DBLP DOI BibTeX RDF	pipelined array, floorplan, sequence pair