| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Tomás Benes, Matej Bartík, Pavel Kubalík |
High Throughput and Low Latency LZ4 Compressor on FPGA.  |
ReConFig  |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Regina Marcela Ivo, Daniel M. Muñoz |
RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew E. Wilson, Michael J. Wirthlin |
Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abubakr Abdulgadir, William Diehl, Jens-Peter Kaps |
An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tolga Yalçin, Elif Bilge Kavun |
Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Wesley Stirk, Jeffrey Goeders |
Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Arkan Alkamil, Darshika G. Perera |
Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai |
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Samah Rahamneh, Lina Sawalha |
Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA Platform. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Adrian Tatulian, Soheil Salehi, Ronald F. DeMara |
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara |
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet-Moundi |
High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | David Andrews 0001, René Cumplido, Claudia Feregrino, Marco Platzner (eds.) |
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019 |
ReConFig |
2019 |
DBLP BibTeX RDF |
|
| 1 | Atiyehsadat Panahi, Keaten Stokke, David Andrews 0001 |
A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich |
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Siavash Rezaei, Eli Bozorgzadeh, Kanghee Kim |
UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Carsten Heinz, Yannick Lavan, Jaco A. Hofmann, Andreas Koch 0001 |
A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Caleb Donovick, Makai Mann, Clark W. Barrett, Pat Hanrahan |
Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Mirzaeian, Houman Homayoun, Avesta Sasan |
TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismael-Antonio Dávila-Rodríguez, Marco Aurelio Nuño-Maganda, Yahir Hernandez-Mier, Said Polanco-Martagón |
Decision-Tree Based Pixel Classification for Real-time Citrus Segmentation on FPGA. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | David Wilson 0004, Greg Stitt |
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ariel Podlubne, Diana Göhringer |
FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelrahman Elkanishy, Derrick T. Rivera, Paul M. Furth, Abdel-Hameed A. Badawy, Youssef Aly, Christopher P. Michael |
FPGA-Accelerated Decision Tree Classifier for Real-Time Supervision of Bluetooth SoC. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Michal Andrzejczak, Farnoud Farahmand, Kris Gaj |
Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Burak Unal, Md Sahil Hassan, Joshua Mack, Nirmal Kumbhare, Ali Akoglu |
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunwoong Kim, Keewoo Lee, Wonhee Cho 0001, Jung Hee Cheon, Rob A. Rutenbar |
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn, Andreas Dengel 0001 |
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt |
Volcan: System Integration of HLS and HMC on FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Guilherme Korol, Michael Guilherme Jordan, Raul Silveira Silva, Monica Magalhães Pereira, Marcelo Brandalero, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
A Runtime Power-Aware Phase Predictor for CGRAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin |
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Habib ul Hasan Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi 0001, Diana Göhringer |
Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf |
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Corbin Thurlow, Hayden Rowberry, Michael J. Wirthlin |
TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrei Hagiescu, Martin Langhammer, Bogdan Pasca 0001, Philip Colangelo, Jason Thong, Niayesh Ilkhani |
BFLOAT MLP Training Accelerator for FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev |
Low Area Overhead Custom Buffering for FFT. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Millar, Marcin Lukowiak, Stanislaw P. Radziszowski |
Design of a Flexible Schönhage-Strassen FFT Polynomial Multiplier with High- Level Synthesis to Accelerate HE in the Cloud. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Beck Strohmer, Anders Bøgild, Anders Stengaard Sørensen, Leon Bonde Larsen |
ROS-Enabled Hardware Framework for Experimental Robotics. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sina Boroumand, Philip Brisk |
Approximate Adder Tree Synthesis for FPGAs. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomohiro Kida, Yuichi Kawamata, Yuichiro Shibata, Kentaro Sano |
A High Level Synthesis Approach for Application Specific DMA Controllers. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Mudussir Ayub, Habibullah Ahmadzay, Josef Eckmüller, Franz Kreupl |
Electronic System Level Power and Performance Analysis for Multi-Processor-System-on-Chip. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sen Ma, Shanyuan Gao |
The Impact of Adopting Computational Storage in Heterogeneous Computing Systems. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Urlea, Wim Vanderbauwhede, Syed Waqar Nabi |
Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ievgen Kabin, Alejandro Sosa, Zoya Dyka, Dan Klann, Peter Langendörfer |
On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack. |
ReConFig |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu 0002, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel |
A Highly Parallel FPGA Implementation of Sparse Neural Network Training. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuai Xie, Zhongyuan Zhao 0004, Weiguang Sheng, Qin Wang 0009, Zhigang Mao |
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapotre, Guy Gogniat |
A small and adaptive coprocessor for information flow tracking in ARM SoCs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Ferozpuri, Kris Gaj |
High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Dillon Huff, Pat Hanrahan |
Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Sathre, Ahmed E. Helal, Wu-chun Feng |
A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and Transformation. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp S. Käsgen, Markus Weinhardt, Christian Hochberger |
A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jafari, Morteza Hosseini, Houman Homayoun, Tinoosh Mohsenin |
A Scalable and Low Power DCNN for Multimodal Data Classification. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan |
Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ievgen Kabin, Dan Kreiser, Zoya Dyka, Peter Langendörfer |
FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Yu Ting, Ardalan Amiri Sani, Eli Bozorgzadeh |
System Services for Reconfigurable Hardware Acceleration in Mobile Devices. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich |
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami |
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Ziener, Jutta Pirkl, Jürgen Teich |
Configuration Tampering of BRAM-based AES Implementations on FPGAs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Weiyi Sun, Hanqing Zeng, Yi-Hua Edward Yang, Viktor K. Prasanna |
Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGA. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Gökhan Akgün, Habib ul Hasan Khan, Mahmoud Ahmed Elshimy, Diana Göhringer |
Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loop. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiziana Fanni, Alfonso Rodríguez 0002, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre |
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kris Heid, Christian Hochberger |
AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Tempelmeier, Georg Sigl, Jens-Peter Kaps |
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | John McGlone, Paolo Palazzari, J. B. Leclere |
Accelerating Key In-memory Database Functionality with FPGA Technology. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Zoya Dyka, Dan Kreiser, Ievgen Kabin, Peter Langendörfer |
Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCA. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Safdar Mahmood, Pavel Shydlouski, Michael Hübner 0001 |
An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse Kinematics. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman |
LaKe: The Power of In-Network Computing. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Lester Kalms, Hassan Ibrahim, Diana Göhringer |
Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAK. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso |
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Vladimir Estivill-Castro, René Hexel, Morgan McColl |
High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Arpit Soni, Yoon Kah Leow, Ali Akoglu |
Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | David Andrews 0001, René Cumplido, Claudia Feregrino, Dirk Stroobandt (eds.) |
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018 |
ReConFig |
2018 |
DBLP BibTeX RDF |
|
| 1 | William Kamp, Norbert Abel, Gianni Comoretto |
Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Rafael Zamacola, Alberto García-Martínez, Javier Mora 0001, Andrés Otero, Eduardo de la Torre |
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Joe Avey, Phillip H. Jones, Joseph Zambreno |
An FPGA-based Hardware Accelerator for Iris Segmentation. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheming Jin, Hal Finkel |
Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC Kernel. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Alan Ehret, Mihailo Isakov, Michel A. Kinsy |
Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Cauwels, Joseph Zambreno, Phillip H. Jones |
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Paulina Fusiara, Gijs Schoonderbeek, Johan Pragt, Leon Hiemstra, Sjouke Kuindersma, Menno Schuil, Grant Hampson |
Design and Fabrication of Full Board Direct Liquid Cooling Heat Sink for Densely Packed FPGA Processing Boards. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed W. Hassan, Ahmed E. Helal, Peter M. Athanas, Wu-Chun Feng, Yasser Y. Hanafy |
Exploring FPGA-specific Optimizations for Irregular OpenCL Applications. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri |
An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet |
An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | William L. Harrison, Gerard Allwein |
Language Abstractions for Hardware-based Control-Flow Integrity Monitoring. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka |
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. |
ReConFig |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton |
Rapid circuit-specific inlining tuning for FPGA high-level synthesis. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano |
Glitch-aware variable pipeline optimization for CGRAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anthony Brandon, Michael Trimarchi |
Trusted display and input using screen overlays. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck |
Continuous live-tracing as debugging approach on FPGAs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Farnoud Farahmand, Ahmed Ferozpuri, William Diehl, Kris Gaj |
Minerva: Automated hardware optimization tool. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | John Watson |
Keynote 1 - Education is not learning facts, but training the mind to think. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreeja Chowdhury, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte |
Aging resilient RO PUF with increased reliability in FPGA. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic |
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas |
Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter |
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Bernard Girau, César Torres-Huitzil |
Optimal weight storage improves fault tolerance of SOMs. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif |
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Rettkowski, Diana Göhringer |
Application-specific processing using high-level synthesis for networks-on-chip. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
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| 1 | Ahmad Salman, Ahmed Ferozpuri, Ekawat Homsirikamol, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj |
A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tripti Jain, Klaus Schneider 0001, Ankesh Jain |
Deriving concentrators from binary sorters using half cleaners. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku |
Thorough analysis of PCIe Gen3 communication. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich |
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. |
ReConFig |
2017 |
DBLP DOI BibTeX RDF |
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