Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Hongbo Rong	Tree register allocation.	MICRO	2009	DBLP DOI BibTeX RDF	register allocation, chordal graph
17	Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt	Improving memory bank-level parallelism in the presence of prefetching.	MICRO	2009	DBLP DOI BibTeX RDF
17	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
17	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
17	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Application-aware prioritization mechanisms for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
17	Jaume Abella 0001, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González 0001	Low Vccmin fault-tolerant cache with highly predictable performance.	MICRO	2009	DBLP DOI BibTeX RDF	Vccmin, cache, faults, predictable performance
17	Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong 0001	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.	MICRO	2009	DBLP DOI BibTeX RDF	atomic region, chunk-based architecture, compiler optimization, sequential consistency
17	Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti	Light speed arbitration and flow control for nanophotonic interconnects.	MICRO	2009	DBLP DOI BibTeX RDF
17	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
17	Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001	Optimizing shared cache behavior of chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
17	Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel	Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.	MICRO	2009	DBLP DOI BibTeX RDF	Nehalem, Shanghai, benchmark, multi-core, coherency
17	Haibo Chen 0001, Liwei Yuan, Xi Wu 0001, Binyu Zang, Bo Huang 0002, Pen-Chung Yew	Control flow obfuscation with information flow tracking.	MICRO	2009	DBLP DOI BibTeX RDF	control flow obfuscation, opaque predicate, information flow tracking, control speculation
17	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
17	Alex Shye, Benjamin Scholbrock, Gokhan Memik	Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.	MICRO	2009	DBLP DOI BibTeX RDF
17	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
17	Mitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti	SCARAB: a single cycle adaptive routing and bufferless network.	MICRO	2009	DBLP DOI BibTeX RDF	routing, interconnection networks, multi-core
17	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
17	Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve	mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.	MICRO	2009	DBLP DOI BibTeX RDF	architecture, error detection, fault injection, multicore processors
17	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
17	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
17	Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge	Proactive transaction scheduling for contention management.	MICRO	2009	DBLP DOI BibTeX RDF	proactive scheduling, software runtime, hardware transactional memory
17	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
17	Changhee Jung, Nathan Clark	DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage.	MICRO	2009	DBLP DOI BibTeX RDF	data structure identification, interface functions, memory graphs
17	Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai	Architecting a chunk-based memory race recorder in modern CMPs.	MICRO	2009	DBLP DOI BibTeX RDF	memory race recorder, determinism, deterministic replay
17	Mohit Tiwari, Xun Li 0001, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood	Execution leases: a hardware-supported mechanism for enforcing strong non-interference.	MICRO	2009	DBLP DOI BibTeX RDF	gate level information flow tracking, covert channels, high assurance systems, timing channels
17	Dyer Rolán, Basilio B. Fraguela, Ramon Doallo	Adaptive line placement with the set balancing cache.	MICRO	2009	DBLP DOI BibTeX RDF	performance, adaptivity, cache, balancing
17	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
17	Brandon Lucia, Luis Ceze	Finding concurrency bugs with context-aware communication graphs.	MICRO	2009	DBLP DOI BibTeX RDF
17	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
17	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
17	Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim	Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping.	MICRO	2009	DBLP DOI BibTeX RDF	adaptive, GPU, mapping, heterogeneous, multicore, dynamic compilation
17	Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks	Tribeca: design for PVT variations with local recovery and fine-grained adaptation.	MICRO	2009	DBLP DOI BibTeX RDF
17	George Kornaros, Spyros Blionas	Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray.	EURASIP J. Adv. Signal Process.	2008	DBLP DOI BibTeX RDF
17	Chang-Burm Cho, Wangyuan Zhang, Tao Li 0006	Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability.	MASCOTS	2008	DBLP BibTeX RDF
17	Diana Marculescu, Sani R. Nassif	Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.	DATE	2008	DBLP DOI BibTeX RDF
17		41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy	MICRO	2008	DBLP BibTeX RDF
17	Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim	A unified methodology for power supply noise reduction in modern microarchitecture design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
17	Bin Li 0008, Lu Peng 0001, Balachandran Ramadass	Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	MART-aided models, performance prediction, design space exploration
17	Arun Rangasamy, Rahul Nagpal, Y. N. Srikant	Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	dvs, dynamic energy, energy, multiple clock domains
17	Yong-Kyu Jung	Non-FPGA-based Field-programmable Self-repairable (FPSR) Microarchitecture.	AHS	2008	DBLP DOI BibTeX RDF
17	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun 0003, Yuan Xie 0001, Hai Li 0001, Yiran Chen 0001	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
17	Deborah T. Marr	Microarchitecture Choices and Tradeoffs for Maximizing Processing Efficiency.		2008	RDF
17	Mark Woh, Yuan Lin 0002, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid 0001, Mladen Wilder, Krisztián Flautner	From SODA to scotch: The evolution of a wireless baseband processor.	MICRO	2008	DBLP DOI BibTeX RDF
17	Livio Soares, David K. Tam, Michael Stumm	Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer.	MICRO	2008	DBLP DOI BibTeX RDF
17	Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel	Tradeoffs in designing accelerator architectures for visual computing.	MICRO	2008	DBLP DOI BibTeX RDF
17	Haiming Liu 0001, Michael Ferdman, Jaehyuk Huh 0001, Doug Burger	Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
17	Arun Raghavan, Colin Blundell, Milo M. K. Martin	Token tenure: PATCHing token counting using directory-based cache coherence.	MICRO	2008	DBLP DOI BibTeX RDF
17	Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero	A distributed processor state management architecture for large-window processors.	MICRO	2008	DBLP DOI BibTeX RDF
17	Chen Tian 0002, Min Feng 0001, Vijay Nagarajan, Rajiv Gupta 0001	Copy or Discard execution model for speculative parallelization on multicores.	MICRO	2008	DBLP DOI BibTeX RDF
17	Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary	Evaluating the effects of cache redundancy on profit.	MICRO	2008	DBLP DOI BibTeX RDF
17	M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam	Power reduction of CMP communication networks via RF-interconnects.	MICRO	2008	DBLP DOI BibTeX RDF
17	Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood	A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.	MICRO	2008	DBLP DOI BibTeX RDF
17	Xi E. Chen, Tor M. Aamodt	Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs.	MICRO	2008	DBLP DOI BibTeX RDF
17	Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, William R. Mark	Toward a multicore architecture for real-time ray-tracing.	MICRO	2008	DBLP DOI BibTeX RDF
17	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu	Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
17	David E. Shaw	Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.	MICRO	2008	DBLP DOI BibTeX RDF
17	Eric Chun, Zeshan Chishti, T. N. Vijaykumar	Shapeshifter: Dynamically changing pipeline width and speed to address process variations.	MICRO	2008	DBLP DOI BibTeX RDF
17	Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti	Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.	MICRO	2008	DBLP DOI BibTeX RDF
17	Ramazan Bitirgen, Engin Ipek, José F. Martínez	Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.	MICRO	2008	DBLP DOI BibTeX RDF
17	Alok Garg, Michael C. Huang 0001	A performance-correctness explicitly-decoupled architecture.	MICRO	2008	DBLP DOI BibTeX RDF
17	Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie	Testudo: Heavyweight security analysis via statistical sampling.	MICRO	2008	DBLP DOI BibTeX RDF
17	Kypros Constantinides, Onur Mutlu, Todd M. Austin	Online design bug detection: RTL analysis, flexible mechanisms, and evaluation.	MICRO	2008	DBLP DOI BibTeX RDF
17	Benjamin C. Lee, Jamison D. Collins, Hong Wang 0003, David M. Brooks	CPR: Composable performance regression for scalable multiprocessor models.	MICRO	2008	DBLP DOI BibTeX RDF
17	Vikas R. Vasisht, Hsien-Hsin S. Lee	SHARK: Architectural support for autonomic protection against stealth by rootkit exploits.	MICRO	2008	DBLP DOI BibTeX RDF
17	Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz	Verification of chip multiprocessor memory systems using a relaxed scoreboard.	MICRO	2008	DBLP DOI BibTeX RDF
17	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware DRAM Controllers.	MICRO	2008	DBLP DOI BibTeX RDF
17	Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel	Dependence-aware transactional memory for increased concurrency.	MICRO	2008	DBLP DOI BibTeX RDF
17	Zhenghong Wang, Ruby B. Lee	A novel cache architecture with enhanced performance and security.	MICRO	2008	DBLP DOI BibTeX RDF
17	Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha	Token flow control.	MICRO	2008	DBLP DOI BibTeX RDF
17	Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal instruction fetch streaming.	MICRO	2008	DBLP DOI BibTeX RDF
17	Nidhi Aggarwal, James E. Smith 0001, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan	Implementing high availability memory with a duplication cache.	MICRO	2008	DBLP DOI BibTeX RDF
17	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Strategies for mapping dataflow blocks to distributed hardware.	MICRO	2008	DBLP DOI BibTeX RDF
17	Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick	Power to the people: Leveraging human physiological traits to control microprocessor frequency.	MICRO	2008	DBLP DOI BibTeX RDF
17	Abhishek Tiwari 0002, Josep Torrellas	Facelift: Hiding and slowing down aging in multicores.	MICRO	2008	DBLP DOI BibTeX RDF
17	Renée St. Amant, Daniel A. Jiménez, Doug Burger	Low-power, high-performance analog neural branch prediction.	MICRO	2008	DBLP DOI BibTeX RDF
17	Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke	The StageNet fabric for constructing resilient multicore systems.	MICRO	2008	DBLP DOI BibTeX RDF
17	Luke Yen, Stark C. Draper, Mark D. Hill	Notary: Hardware techniques to enhance signatures.	MICRO	2008	DBLP DOI BibTeX RDF
17	Samuel Rodrigo, José Flich, José Duato, Mark Hummel	Efficient unicast and multicast support for CMPs.	MICRO	2008	DBLP DOI BibTeX RDF
17	Yuho Jin, Ki Hwan Yum, Eun Jung Kim 0001	Adaptive data compression for high-performance low-power on-chip networks.	MICRO	2008	DBLP DOI BibTeX RDF
17	Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	Reconfigurable energy efficient near threshold cache architectures.	MICRO	2008	DBLP DOI BibTeX RDF
17	Hung Q. Le, William J. Starke, J. Stephen Fields, Francis P. O'Connell, Dung Q. Nguyen, Bruce J. Ronchetti, Wolfram Sauer, Eric M. Schwarz, Michael T. Vaden	IBM POWER6 microarchitecture.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
17	Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata	Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
17		40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA	MICRO	2007	DBLP BibTeX RDF
17	Santosh Talli, Ram Srinivasan, Jeanine E. Cook	Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization.	IPCCC	2007	DBLP DOI BibTeX RDF
17	Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong	Fine grain 3D integration for microarchitecture design through cube packing exploration.	ICCD	2007	DBLP DOI BibTeX RDF
17	Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew	Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization.	IISWC	2007	DBLP DOI BibTeX RDF
17	Chang-Burm Cho, Wangyuan Zhang, Tao Li 0006	Characterizing the Effect of Microarchitecture Design Parameters on Workload Dynamic Behavior.	IISWC	2007	DBLP DOI BibTeX RDF
17	Jason Zebchuk, Elham Safi, Andreas Moshovos	A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	MICRO	2007	DBLP DOI BibTeX RDF
17	Matthew J. Bridges, Neil Vachharajani, Yun Zhang 0005, Thomas B. Jablin, David I. August	Revisiting the Sequential Programming Model for Multi-Core.	MICRO	2007	DBLP DOI BibTeX RDF
17	Daniel Sánchez 0003, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam	Implementing Signatures for Transactional Memory.	MICRO	2007	DBLP DOI BibTeX RDF
17	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
17	Sebastian Winkel	Optimal versus Heuristic Global Code Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
17	Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin	Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly.	MICRO	2007	DBLP DOI BibTeX RDF
17	Jaume Abella 0001, Xavier Vera, Antonio González 0001	Penelope: The NBTI-Aware Processor.	MICRO	2007	DBLP DOI BibTeX RDF
17	Karin Strauss, Xiaowei Shen, Josep Torrellas	Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
17	Radu Teodorescu, Jun Nakano, Abhishek Tiwari 0002, Josep Torrellas	Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing.	MICRO	2007	DBLP DOI BibTeX RDF
17	Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe	Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.	MICRO	2007	DBLP DOI BibTeX RDF
17	John Kim, James D. Balfour, William J. Dally	Flattened Butterfly Topology for On-Chip Networks.	MICRO	2007	DBLP DOI BibTeX RDF
17	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
17	Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt	Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow.	MICRO	2007	DBLP DOI BibTeX RDF