Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb	Die Stacking (3D) Microarchitecture.	MICRO	2006	DBLP DOI BibTeX RDF
18	Anna Slobodová	Challenges for Formal Verification in Industrial Setting.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
18	Ndubuisi Ekekwe, Ralph Etienne-Cummings, Peter Kazanzides	A configurable VLSI chip for DC motor control for compact, low-current robotic systems.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Shiwen Hu, Lizy Kurian John	Impact of virtual execution environments on processor energy consumption and hardware adaptation.	VEE	2006	DBLP DOI BibTeX RDF	hardware adaptation, energy efficiency, power dissipation
18	Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
18	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	clock faults, Testing, clock distribution network, manufacturing test
18	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A self-tuning cache architecture for embedded systems.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
18	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A Self-Tuning Cache Architecture for Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
18	Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.	FPL	2004	DBLP DOI BibTeX RDF
18	Todd M. Austin	Designing robust microarchitectures.	DAC	2004	DBLP DOI BibTeX RDF	computer system design, reliable microarchitecture design, low-power, microarchitecture, system-on-a-chip
18	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.	HPCA	2003	DBLP DOI BibTeX RDF
18	Chris R. Jesshope	Multi-threaded Microprocessors - Evolution or Revolution.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
18	Fabrice Baray, Philippe Codognet, Daniel Diaz 0001, Henri Michel	Code-Based Test Generation for Validation of Functional Processor Descriptions.	TACAS	2003	DBLP DOI BibTeX RDF	Code-based test generation, functional hardware verification, constraint solving techniques
18	Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos	Virtual-scan: a novel approach for software-based self-testing of microprocessors.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli	REFLIX: A Processor Core for Reactive Embedded Applications.	FPL	2002	DBLP DOI BibTeX RDF
18	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
18	Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid	Using On-Chip Configurable Logic to Reduce Embedded System Software Energy.	FCCM	2002	DBLP DOI BibTeX RDF
18	Frank Vahid, Rilesh Patel, Greg Stitt	Propagating constants past software to hardware peripherals in fixed-application embedded systems.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	embedded systems, low power, synthesis, system-on-a-chip, intellectual property, platforms, cores, tuning, constant propagation
18	David M. Harris, Sam Naffziger	Statistical clock skew modeling with data delay variations.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
18	Hironori Komi, Antonio Ortega	Analysis of Cache Efficiency in 2D Wavelet Transform.	ICME	2001	DBLP DOI BibTeX RDF
18	R. D. Arthan	Analysis of Compiled Code: A Prototype Formal Model.	ZB	2000	DBLP DOI BibTeX RDF
18	Gang Qu 0001, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak	Function-level power estimation methodology for microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
18	Jae J. Chang, Myunghee Lee, Sungyong Jung, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills	Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown	High-level design verification of microprocessors via error modeling.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	design verification, error modeling, design errors
18	Phillip J. Windley	Specifying Instruction-Set Architectures in HOL: A Primer.	TPHOLs	1994	DBLP DOI BibTeX RDF
18	Carl Steidley	ROBOTICS: A Hands-On Introduction to Hardware (Abstract).	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
18	Nikitas J. Dimopoulos, Ben Huber, Kin F. Li, D. Caughey, Marco A. Escalante, Dongni Li, R. Burnett, Eric G. Manning	Modelling Signal Behaviour in DAME.	IEA/AIE (Vol. 2)	1990	DBLP DOI BibTeX RDF
18	Philip Heidelberger, M. Seetha Lakshmi	A Performance Comparison of Multi-Micro and Mainframe Database Architectures.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
18	Manfred Ruschitzka, Andrew Choi, John L. Clevenger	Sibyl: a relational database system with remote-access capabilities.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF
18	William Hyman, William Lively	A proposed study to access the impact of microprocessors on health care delivery.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
18	Paul M. Russo	Microprocessors at work: session overview.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
18	Teresa L. McLaurin, Stylianos Diamantidis, Irakis Diamantidis	The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper.	IEEE Des. Test Comput.	2009	DBLP DOI BibTeX RDF
18	Gang Jin, Lei Wang 0011, Zhiying Wang	The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.	NAS	2009	DBLP DOI BibTeX RDF
18	Kevin Reick, Pia N. Sanda, Scott B. Swaney, Jeffrey W. Kellington, Michael J. Mack, Michael S. Floyd, Daniel Henderson	Fault-Tolerant Design of the IBM Power6 Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, fault isolation, RAS, instruction retry, Hot Chips 19
18	Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja	MMV: A Metamodeling Based Microprocessor Validation Environment.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
18	Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani	Case Study on Speed Failure Causes in a Microprocessor.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
18	Nima Mehdizadeh, Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi	Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor.	ARES	2008	DBLP DOI BibTeX RDF
18	Chun-Liang Hsu, Sheng-Yuan Yang, Wei-Bin Wu 0001	Implementing Speech-Recognition Microprocessor into Intelligent Control-System of Home-Appliance.	APSCC	2008	DBLP DOI BibTeX RDF
18	Andreas Ehliar, Per Karlström, Dake Liu	A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.	FPL	2008	DBLP DOI BibTeX RDF
18	Md. Manzur Rahman, Md. Nayim Kabir, S. M. Shahriar Rashid	Microprocessor Based Design of the Control Mechanism of Automatic Mail Sorting Machine.	CSSE (1)	2008	DBLP DOI BibTeX RDF
18	Hongnan Zhang, Chao Jiang, Yayou Huang, Saichun Hu	Design of Infrared Signal Emission Based on MCS-51 Microprocessor.	ICNSC	2008	DBLP DOI BibTeX RDF
18	Da Wang, Rui Li, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
18	Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy 0001, Shay Gueron	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Babu Turumella, Mukesh Sharma	Assertion-based verification of a 32 thread SPARCTM CMT microprocessor.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, coverage, assertions, multi-threading
18	Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Tao Li 0006, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio 0001	OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	branch prediction, processor architectures, Pipeline processors, performance of systems, hardware/software interfaces, computer system implementation
18	Anita Lungu, Daniel J. Sorin	Verification-Aware Microprocessor Design.	PACT	2007	DBLP DOI BibTeX RDF
18	Dipnarayan Guha, Thambipillai Srikanthan	Reconfigurable Frame Parser Design for Multi-Radio Support on Asynchronous Microprocessor Cores.	ICCTA	2007	DBLP DOI BibTeX RDF
18	Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak	Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor.	ISVLSI	2007	DBLP DOI BibTeX RDF
18	Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda	Design Methodology for 2.4GHz Dual-Core Microprocessor.	ASP-DAC	2007	DBLP DOI BibTeX RDF
18	Lachezar Yordanov, Miroslav Mihaylov, Vladimir Vitkov	Advanced microprocessor system with serial memory for harvester testing.	CompSysTech	2007	DBLP DOI BibTeX RDF	automatic control, computer systems and technologies, grain harvester, serial interface module, microcontroller
18	Nagarajan Venkateswaran, Arjun Kumeresh, Harish Chandran	DNA Based Evolutionary Approach for Microprocessor Design Automation.	ICANNGA (1)	2007	DBLP DOI BibTeX RDF
18	Jing Wang, Shengbing Zhang, Zhang Meng	Testing of a 32-bit High Performance Embedded Microprocessor.	SIES	2007	DBLP DOI BibTeX RDF
18	Chunta Chu, Xinyi Zhang, Lei He 0001, Tong Jing	Temperature aware microprocessor floorplanning considering application dependent power load.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Michael J. Schulte, Dimitri Tan, Carl Lemonds	Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier.	ICCD	2007	DBLP DOI BibTeX RDF
18	Kimish Patel, Wonbok Lee, Massoud Pedram	Active bank switching for temperature control of the register file in a microprocessor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	register file, thermal model, temperature-aware design
18	Constantine A. Murenin	Generalised Interfacing with Microprocessor System Hardware Monitors.	ICNSC	2007	DBLP DOI BibTeX RDF
18	Alon Flaisher, Alon Gluska, Eli Singerman	Case study: Integrating FV and DV in the Verification of the Intel CoreTM 2 Duo Microprocessor.	FMCAD	2007	DBLP DOI BibTeX RDF
18	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja	Model Based Test Generation for Microprocessor Architecture Validation.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Chico: An On-chip Hardware Checker for Pipeline Control Logic.	MTV	2007	DBLP DOI BibTeX RDF
18	Pedro Trancoso	Adaptive High-End Microprocessor for Power-Performance Efficiency.	DSD	2006	DBLP DOI BibTeX RDF
18	Seong-Won Lee, Neungsoo Park, Jean-Luc Gaudiot	Low Power Microprocessor Design for Embedded Systems.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
18	Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin	Ultra low-cost defect protection for microprocessor pipelines.	ASPLOS	2006	DBLP DOI BibTeX RDF	defect-protection, reliability, pipelines, low-cost
18	Alon Gluska	Practical methods in coverage-oriented verification of the merom microprocessor.	DAC	2006	DBLP DOI BibTeX RDF	logic design, coverage, logic verification, functional coverage
18	Jorge Campos, Hussain Al-Asaad	Circuit Profiling Mechanisms for High-Level {ATPG}.	MTV	2006	DBLP DOI BibTeX RDF
18	Tamarah Arons, Elad Elster, Terry Murphy, Eli Singerman	Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation.	MTV	2006	DBLP DOI BibTeX RDF	Formal methods, Test generation, Software verification and validation
18	Vasanth Venkatachalam, Michael Franz	Power reduction techniques for microprocessor systems.	ACM Comput. Surv.	2005	DBLP DOI BibTeX RDF	power reduction, Energy dissipation
18	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers
18	Bob Bentley	Validating a Modern Microprocessor.	CAV	2005	DBLP DOI BibTeX RDF
18	Harit Modi, Lawrence Spracklen, Yuan Chou, Santosh G. Abraham	Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures.	MASCOTS	2005	DBLP DOI BibTeX RDF
18	Greg Stitt, Frank Vahid	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.	DATE	2005	DBLP DOI BibTeX RDF
18	Pedro Trancoso	Design Space Navigation for Neighboring Power-Performance Efficient Microprocessor Configurations.	ARCS	2005	DBLP DOI BibTeX RDF
18	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari	REMIC: design of a reactive embedded microprocessor core.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Luís Gomes 0001, Anikó Costa	Remote Laboratory Support for an Introductory Microprocessor Course.	MSE	2005	DBLP DOI BibTeX RDF
18	Ryuichi Takahashi, Hajime Ohiwa	Legitimate Peripheral Participation on FPGA for Fine-Grain Microprocessor Design Education.	MSE	2005	DBLP DOI BibTeX RDF
18	Jean-Samuel Chenard, Ahmed Usman Khalid, Milos Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic	Expandable and Robust Laboratory for Microprocessor Systems.	MSE	2005	DBLP DOI BibTeX RDF
18	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Automatic Completion and Refinement of Verification Sets for Microprocessor Cores.	EvoWorkshops	2005	DBLP DOI BibTeX RDF
18	Jesse Fang	Challenges and Opportunities on Multi-core Microprocessor.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
18	Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante	New evolutionary techniques for test-program generation for complex microprocessor cores.	GECCO	2005	DBLP DOI BibTeX RDF	evolutionary algorithms, automatic test program generation
18	William Lloyd Bircher, M. Valluri, J. Law, Lizy K. John	Runtime identification of microprocessor energy saving opportunities.	ISLPED	2005	DBLP DOI BibTeX RDF	speculative microprocessors, modeling, energy efficiency, power
18	James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De	Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Nicolas Renaud	How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family.	IOLTS	2005	DBLP DOI BibTeX RDF
18	Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kurian John, Joydeep Ghosh	Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
18	Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee	Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor.	VTS	2005	DBLP DOI BibTeX RDF
18	Yale N. Patt	The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints?	AICCSA	2005	DBLP DOI BibTeX RDF
18	Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet	A generic micro-architectural test plan approach for microprocessor verification.	DAC	2005	DBLP DOI BibTeX RDF	generic test plan, test generation, coverage, micro-architecture, dynamic verification
18	Umar Saif, James W. Anderson, Anthony Degangi, Anant Agarwal	Gigabit routing on a software-exposed tiled-microprocessor.	ANCS	2005	DBLP DOI BibTeX RDF	RAW router, tiled architecture, programmable router
18	Jorge Campos, Hussain Al-Asaad	Search-Space Optimizations for High-Level ATPG.	MTV	2005	DBLP DOI BibTeX RDF
18	Charles H.-P. Wen, Li-C. Wang	Simulation Data Mining for Functional Test Pattern Justification.	MTV	2005	DBLP DOI BibTeX RDF
18	Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt	Reducing the Soft-Error Rate of a High-Performance Microprocessor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
18	Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin	Tolerating Hard Faults in Microprocessor Array Structures.	DSN	2004	DBLP DOI BibTeX RDF
18	Piotr Gawkowski, Janusz Sosnowski	Evaluation of Transient Fault Susceptibility in Microprocessor Systems.	DSD	2004	DBLP DOI BibTeX RDF
18	Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott	Dynamically Trading Frequency for Complexity in a GALS Microprocessor.	MICRO	2004	DBLP DOI BibTeX RDF
18	Srihari Makineni, Ravi R. Iyer 0001	Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor.	HPCA	2004	DBLP DOI BibTeX RDF
18	Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo	Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.	FPL	2004	DBLP DOI BibTeX RDF
18	Daisuke Maruyama, Akira Kanuma, Takashi Mochiyama, Hiroaki Komatsu, Yaroku Sugiyama, Noriyuki Ito	Detection of multiple transitions in delay fault test of SPARC64 microprocessor.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir	Interconnect-power dissipation in a microprocessor.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect power, wire spacing, routing, low-power design
18	Yue Luo, Lizy Kurian John, Lieven Eeckhout	Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation.	SBAC-PAD	2004	DBLP DOI BibTeX RDF