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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14306 occurrences of 4820 keywords
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Results
Found 45278 publication records. Showing 45278 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Mikael R. K. Patel |
A design representation for high level synthesis. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
Data Structures, High Level Synthesis, Design Automation, Design Representation |
23 | Liliana Díaz-Olavarrieta, Safwat G. Zaky |
A new synthesis technique for multilevel combinational circuits. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
testing, mappings, synthesis, Combinational |
23 | Kassem Saleh, Robert L. Probert |
Synthesis of Error-Recoverable Protocol Specifications from Service Specifications. |
ICCI |
1990 |
DBLP DOI BibTeX RDF |
syntactic correctness, synthesis, error-recovery, protocol design, semantic correctness, Communication software |
23 | Yaoxue Zhang, Kaoru Takahashi, Norio Shiratori, Shoichi Noguchi |
An Interactive Protocol Synthesis Algorithm Using a Global State Transition Graph. |
IEEE Trans. Software Eng. |
1988 |
DBLP DOI BibTeX RDF |
interactive protocol synthesis algorithm, global state transition graph, global state transition graph, deadlock avoidance rules, complete reception, protocols, graph theory, finite-state machines, finite automata, buffer overflow, production rules, interactive programming, deadlock freeness |
23 | Ted J. Biggerstaff |
Factored Specifications In The Synthesis Of LISP Functions. |
ACM Annual Conference (1) |
1978 |
DBLP DOI BibTeX RDF |
Automatic program synthesis, Factored specifications, LISP programs, LISP, Program specification |
22 | Zhen-Hua Ling, Korin Richmond, Junichi Yamagishi, Ren-Hua Wang |
Integrating Articulatory Features Into HMM-Based Parametric Speech Synthesis. |
IEEE Trans. Speech Audio Process. |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani |
A cycle-based synthesis algorithm for reversible logic. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Armando Solar-Lezama |
The Sketching Approach to Program Synthesis. |
APLAS |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Yun Sheng, Abdul Hamid Sadka, Ahmet M. Kondoz |
Automatic Single View-Based 3-D Face Synthesis for Unsupervised Multimedia Applications. |
IEEE Trans. Circuits Syst. Video Technol. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
DDBDD: Delay-Driven BDD Synthesis for FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández 0001 |
An Integrated Layout-Synthesis Approach for Analog ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Lin Yuan, Gang Qu 0001, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli |
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Andrew B. Kahng, Kambiz Samadi |
CMP Fill Synthesis: A Survey of Recent Studies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Robert Wille, Hoang Minh Le 0001, Gerhard W. Dueck, Daniel Große |
Quantified Synthesis of Reversible Logic. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Sujan Pandey, Rolf Drechsler |
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Andrey Mokhov, Alexandre Yakovlev |
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
22 | James McDermott, Niall Griffith, Michael O'Neill 0001 |
Evolutionary Computation Applied to Sound Synthesis. |
The Art of Artificial Evolution |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Almitra Pradhan, Ranga Vemuri |
On the Use of Hash Tables for Efficient Analog Circuit Synthesis. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rui Zhang, Pallav Gupta, Niraj K. Jha |
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Sehoon Yea, Anthony Vetro |
RD-Optimized View Synthesis Prediction for Multiview Video Coding. |
ICIP (1) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade |
Register Sharing Verification During Data-Path Synthesis. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mumtaz Siddiqui, Alex Villazón, Thomas Fahringer |
Semantic-Based On-demand Synthesis of Grid Activities for Automatic Workflow Generation. |
eScience |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi |
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Sujan Pandey, Christian Genz, Rolf Drechsler |
Co-synthesis of custom on-chip bus and memory for MPSoC architectures. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Vyas Krishnan, Srinivas Katkoori |
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Kevin Oo Tinmaung, David Howland, Russell Tessier |
Power-aware FPGA logic synthesis using binary decision diagrams. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
FPGA, binary decision diagram, dynamic power |
22 | Robert Wille, Daniel Große |
Fast exact Toffoli network synthesis of reversible logic. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia |
The coming of age of physical synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Borzoo Bonakdarpour, Sandeep S. Kulkarni |
Exploiting Symbolic Techniques in Automated Synthesis of Distributed Programs with Large State Space. |
ICDCS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
DDBDD: Delay-Driven BDD Synthesis for FPGAs. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mitsuko Aramaki, Richard Kronland-Martinet |
Analysis-synthesis of impact sounds by real-time dynamic filtering. |
IEEE Trans. Speech Audio Process. |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Keiichi Tokuda |
An HMM-Based Approach to Flexible Speech Synthesis. |
ISCSLP |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk |
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Zhigang Gao, Zhaohui Wu 0001 |
Implementation Synthesis of Embedded Software under the Group-Based Scheduling Model. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Wen-Chieh Lin, James Hays, Chenyu Wu, Yanxi Liu 0001, Vivek Kwatra |
Quantitative Evaluation of Near Regular Texture Synthesis Algorithms. |
CVPR (1) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Yulia Korukhova |
Automatic Deductive Synthesis of Lisp Programs in the System ALISA. |
JELIA |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid |
System Synthesis for Networks of Programmable Blocks. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Bernd Finkbeiner, Sven Schewe |
Uniform Distributed Synthesis. |
LICS |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng 0001 |
Bitwidth-aware scheduling and binding in high-level synthesis. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ron van der Meyden, Thomas Wilke |
Synthesis of Distributed Systems from Knowledge-Based Specifications. |
CONCUR |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Renqiu Huang, Ranga Vemuri |
On-Line Synthesis for Partially Reconfigurable FPGAs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha |
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Lech Józwiak, Szymon Bieganski |
Information Trans-Coders in Information-Driven Circuit Synthesis. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Jhing-Fa Wang, Han-Jen Hsu, Hong-Ming Wang |
Intelligent Sub-patch Texture Synthesis Algorithm for Smart Camera. |
KES |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Vida Kianzad, Shuvra S. Bhattacharyya |
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems. |
ASAP |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Paulo Tabuada |
Open Maps, Alternating Simulations and Control Synthesis. |
CONCUR |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar 0001 |
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Alex Doboli, Ranga Vemuri |
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Zhun Fan, Kisung Seo, Jianjun Hu, Ronald C. Rosenberg, Erik D. Goodman |
System-Level Synthesis of MEMS via Genetic Programming and Bond Graphs. |
GECCO |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Madhubanti Mukherjee, Ranga Vemuri |
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey |
High-level Synthesis of Multi-process Behavioral Descriptions. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Liming Xiu, Zhihong You |
A "flying-adder" architecture of frequency and phase synthesis with scalability. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Srivaths Ravi 0001, Niraj K. Jha |
Test synthesis of systems-on-a-chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Ramesh Karri, Balakrishnan Iyer, Israel Koren |
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Thomas A. Henzinger, Sriram C. Krishnan, Orna Kupferman, Freddy Y. C. Mang |
Synthesis of Uninitialized Systems. |
ICALP |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Yue Yu, Jiebo Luo, Chang Wen Chen |
Multiresolution Block Sampling-Based Method for Texture Synthesis. |
ICPR (1) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Junhyung Um, Jae-Hoon Kim 0001, Taewhan Kim |
Layout-driven resource sharing in high-level synthesis. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Keith S. Vallerio, Niraj K. Jha |
Task graph transformation to aid system synthesis. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Aleksander Slusarczyk, Lech Józwiak |
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Cheng-Yuan Lin, Jyh-Shing Roger Jang, Shaw-Hwa Hwang |
An On-the-Fly Mandarin Singing Voice Synthesis System. |
IEEE Pacific Rim Conference on Multimedia |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Kiyoshi Akama, Hidekatsu Koike, Hiroshi Mabuchi |
A Theoretical Foundation of Program Synthesis by Equivalent Transformation. |
Ershov Memorial Conference |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Chih-Yuan Chen, Shing-Wu Tung |
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri |
Application Specific Macro Based Synthesis. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Srivaths Ravi 0001, Niraj K. Jha |
Synthesis of System-on-a-chip for Testability. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Song Chen, Adam Postula |
Synthesis of custom interleaved memory systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
22 | U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary |
A System-Level Synthesis Algorithm with Guaranteed Solution Quality. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Boubakeur Boufama |
The Use of Homographies for View Synthesis. |
ICPR |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk |
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Apostolos A. Kountouris, Christophe Wolinski |
High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Zhang Yang, Rajesh K. Gupta 0001 |
A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Hakim Kahlouche |
STEPS: A Software Tool-set for automatEd Protocol Synthesis. |
ICCCN |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang |
PSM: an object-oriented synthesis approach to multiprocessor system design. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Luca Benini, Giovanni De Micheli |
Automatic synthesis of low-power gated-clock finite-state machines. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Taewhan Kim, C. L. Liu 0001 |
An integrated algorithm for incremental data path synthesis. |
J. VLSI Signal Process. |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Jun Gu, Ruchir Puri |
Asynchronous circuit synthesis with Boolean satisfiability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Hyeong-Kyo Kim, Thomas P. Barnwell III |
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Jaewon Kim, Sung-Mo Kang |
A timing-driven data path layout synthesis with integer programming. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
routing, integer programming, timing-driven placement, data path, bit-slice |
22 | Alex Orailoglu, Ramesh Karri |
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
22 | D. L. Springer, Donald E. Thomas |
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Daniel D. Gajski, Loganath Ramachandran |
Introduction to High-Level Synthesis. |
IEEE Des. Test Comput. |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Kenneth Y. Yun, Bill Lin 0001, David L. Dill, Srinivas Devadas |
Performance-driven synthesis of asynchronous controllers. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy |
The Siemens high-level synthesis system CALLAS. |
IEEE Trans. Very Large Scale Integr. Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Raul Camposano, Larry F. Saunders, Raja M. Tabet |
VHDL as Input for High-Level Synthesis. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Efim B. Kinber |
Some Models of Inductive Syntactical Synthesis from Sample Computations. |
Baltic Computer Science |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Giovanni De Micheli, David C. Ku, Frédéric Mailhot 0001, Thomas K. Truong |
The Olympus Synthesis System. |
IEEE Des. Test Comput. |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Anup Hosangadi, Farzan Fallah, Ryan Kastner |
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
constant multiplications, DSP synthesis, high level synthesis, linear systems, common subexpression elimination, algebraic methods |
21 | Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh |
Quality of EDA CAD Tools: Definitions, Metrics and Directions. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Design Quality Metrics, Integrated Design Exploration, Incremental Synthesis, Layout-Driven Synthesis' System-Level Interconnect Prediction and Planning, Tool Interoperability, Deep Submicron Designs |
21 | Biplav Srivastava, Subbarao Kambhampati, Amol Dattatraya Mali |
A Structured Approach for Synthesizing Planners from Specifications. |
ASE |
1997 |
DBLP DOI BibTeX RDF |
planners synthesis, domain-independent approach, error-proneness, manual coding, knowledge-based software synthesis tools, CLAY, Kestrel Interactive Development System, declarative control knowledge, AI, specifications, knowledge based systems, structured approach |
21 | Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien |
A Method for Synthesizing Area Efficient Multilevel PTL Circuits. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
multilevel logic synthesis, logic synthesis, Pass transistor logic |
21 | Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao |
Easily Testable Data Path Allocation Using Input/Output Registers. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design |
21 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
21 | Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi |
Design-for-debugging of application specific designs. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
debugging requirements, scheduling, computational complexity, combinatorial optimization, controllability, high level synthesis, design for testability, observability, application specific integrated circuits, circuit CAD, hardware support, polynomial time complexity, Design-for-Debugging, synthesis algorithm |
21 | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja |
An optimized testable architecture for finite state machines. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence |
21 | B. M. Subraya, Anshul Kumar, Shashi Kumar |
An HOL based framework for design of correct high level synthesizers. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
HOL based framework, high level synthesizer design, design correctness guarantee, verifiable templates, synthesis module correctness, formal verification, high level synthesis, modularity, formal logic, higher order logic, verification process, formal framework |
21 | Janos Sztipanovits, Gabor Karsai, Csaba Biegl, Ted Bapty, Ákos Lédeczi, Amit Misra |
MULTIGRAPH: an architecture for model-integrated computing. |
ICECCS |
1995 |
DBLP DOI BibTeX RDF |
Multigraph Architecture, complex embedded systems, meta-level architecture, domain specific model integrated program synthesis environments, application specific model interpreters, executable programs synthesis, real-time systems, programming environments, computer architecture, program interpreters, model-integrated computing, integrated modeling, MULTIGRAPH, model analysis |
21 | Jason Cong, Albert Liu, Bin Liu 0006 |
A variation-tolerant scheduler for better than worst-case behavioral synthesis. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
scheduling, variation, behavioral synthesis |
21 | Frank Vahid, Tony Givargis |
Highly-cited ideas in system codesign and synthesis. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
hardware/software codesign, citations, system synthesis |
21 | Michael Kipp, Michael Neff, Kerstin H. Kipp, Irene Albrecht |
Towards Natural Gesture Synthesis: Evaluating Gesture Units in a Data-Driven Approach to Gesture Synthesis. |
IVA |
2007 |
DBLP DOI BibTeX RDF |
Nonverbal Behavior Generation, Gesture Synthesis, Embodied Conversational Agents |
21 | Manjunath Kudlur, Kevin Fan, Scott A. Mahlke |
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
system-level synthesis, loop accelerator, application-specific hardware |
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