Search results for "ASIP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto	A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter.	VLSI Design	2004	DBLP DOI BibTeX RDF
25	Chandra Shekhar 0001, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar	Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary.	VLSI Design	2004	DBLP DOI BibTeX RDF
25	Zhijie Shi, Xiao Yang 0001, Ruby B. Lee	Arbitrary Bit Permutations in One or Two Cycles.	ASAP	2003	DBLP DOI BibTeX RDF
25	Jeonghun Cho, Yunheung Paek, David B. Whalley	Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	dual memory, memory assignment, non-orthogonal architecture, compiler, graph coloring, maximum spanning tree
25	Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Analysis of the influence of register file size on energyconsumption, code size, and execution time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
25	Bruce R. Childers, Jack W. Davidson	Custom Wide Counterflow Pipelines for High-Performance Embedded Applications.	IEEE PACT	2000	DBLP DOI BibTeX RDF
25	Bruce R. Childers, Jack W. Davidson	An Infrastructure for Designing Custom Embedded Counter-flow Pipelines.	HICSS	2000	DBLP DOI BibTeX RDF
25	Forest Fisher, Steve A. Chien, Edisanter Lo, Ronald Greeley	SAR Image Processing Using Artificial Intelligence Planning.	ICIAP	1999	DBLP DOI BibTeX RDF
20	Yaron Yeger, Onno J. Boxma, Jacques Resing, Maria Vlasiou	ASIP tandem queues with consumption.	SIGMETRICS Perform. Evaluation Rev.	2024	DBLP DOI BibTeX RDF
20	Wei Chen 0100, Dake Liu	Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
20	Cangyuan Li, Ying Wang 0001, Huawei Li 0001, Yinhe Han 0001	APPEND: Rethinking ASIP Synthesis in the Era of AI.	DAC	2023	DBLP DOI BibTeX RDF
20	Ahmed M. Hamed, M. Watheq El-Kharashi, Ashraf Salem, Mona Safar	A Multicycle Pipelined GCM-Based AUTOSAR Communication ASIP.	IEEE Access	2022	DBLP DOI BibTeX RDF
20	Muxuan Gao, He Chen, Dake Liu	An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost.	Sensors	2022	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Roghayeh Ataie, Mohammad Hossein Shafiabadi, Abolghasem Ghasempour	Design and implementation of an ASIP for SHA-3 hash algorithm.	Int. J. Inf. Comput. Secur.	2022	DBLP DOI BibTeX RDF
20	Vasileios Leon, George Lentaris, Dimitrios Soudris, Simon Vellas, Mathieu Bernou	Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
20	Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David	ASIP Accelerator for LUT-based Neural Networks Inference.	NEWCAS	2022	DBLP DOI BibTeX RDF
20	Alexander Antonov	Superscalar Out-of-Order RISC-V ASIP Based on Programmable Hardware Generator with Decoupled Computations and Flow Control.	MECO	2022	DBLP DOI BibTeX RDF
20	Mood Venkanna, Rameshwar Rao 0001, P. Chandra Sekhar	Design of filter for image de-noising using discrete wavelet transform for ASIP.	Int. J. Comput. Vis. Robotics	2021	DBLP DOI BibTeX RDF
20	Shahriar Shahabuddin, Aarne Mämmelä, Markku J. Juntti, Olli Silvén	ASIP for 5G and Beyond: Opportunities and Vision.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
20	Onno J. Boxma, Offer Kella, Uri Yechiali	Workload distributions in ASIP queueing networks.	Queueing Syst. Theory Appl.	2021	DBLP DOI BibTeX RDF
20	Yunxiang Tang, Biao Long, Dake Liu	An ASIP design for low loss compression of front-haul data in 5G base stations.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
20	Seungseok Nam, Emil Matús, Gerhard P. Fettweis	Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs.	ISVLSI	2021	DBLP DOI BibTeX RDF
20	Joost Hoozemans, Kati Tervo, Pekka Jääskeläinen, Zaid Al-Ars	Energy Efficient Multistandard Decompressor ASIP.	ICCDE	2021	DBLP DOI BibTeX RDF
20	Seungseok Nam, Emil Matús, Sadia Moriam, Gerhard P. Fettweis	Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCs.	ISVLSI	2020	DBLP DOI BibTeX RDF
20	Przemyslaw Mazurek	BOSON - Application-Specific Instruction Set Processor (ASIP) for Educational Purposes.	ICARCV	2020	DBLP DOI BibTeX RDF
20	Seungseok Nam, Emil Matús, Gerhard P. Fettweis	An ASIP Approach to Path Allocation in TDM NoCs using Adaptive Search Region.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
20	Manil Dev Gomony, Mihaela Jivanescu, Nikolas Olaziregi	Towards ASIP Architecture-Driven Algorithm Development.	IESS	2019	DBLP DOI BibTeX RDF
20	Steffen Malkowsky, Hemanth Prabhu, Liang Liu 0002, Ove Edfors, Viktor Öwall	A Programmable 16-Lane SIMD ASIP for Massive MIMO.	ISCAS	2019	DBLP DOI BibTeX RDF
20	Wei-pei Huang, Ray C. C. Cheung, Hong Yan 0001	An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation.	ASAP	2019	DBLP DOI BibTeX RDF
20	Juan Fernando Eusse Giraldo	ASIP algorithmic/architectural co-exploration based on high level performance estimation.		2019	RDF
20	Jinli Rao, Tianyong Ao, Shu Xu, Kui Dai, Xuecheng Zou	Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor.	IEICE Trans. Inf. Syst.	2018	DBLP DOI BibTeX RDF
20	Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	HOG-Based Object Detection Processor Design Using ASIP Methodology.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
20	Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam, Michel Jézéquel	Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
20	Vianney Lapotre, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet	Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.	EURASIP J. Adv. Signal Process.	2017	DBLP DOI BibTeX RDF
20	Lukas Gerlach 0001, Guillermo Payá Vayá, Shuang Liu, Moritz Weißbrich, Holger Blume, Daniel Marquardt, Simon Doclo	Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP.	SAMOS	2017	DBLP DOI BibTeX RDF
20	Shahriar Shahabuddin, Olli Silvén, Markku J. Juntti	ASIP design for multiuser MIMO broadcast precoding.	EuCNC	2017	DBLP DOI BibTeX RDF
20	Mood Venkanna, Rameshwar Rao 0001, P. Chandra Sekhar	Application of ASIP in Embedded Design with Optimized Clock Management.	ICITKM	2017	DBLP DOI BibTeX RDF
20	Naotaka Yoshida, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi	A hybrid HW/SW 802.11ac/ax system design platform with ASIP implementation.	ISPACS	2017	DBLP DOI BibTeX RDF
20	Aydin Aysu, Ege Gulcan, Daisuke Moriyama, Patrick Schaumont	Compact and low-power ASIP design for lightweight PUF-based authentication protocols.	IET Inf. Secur.	2016	DBLP DOI BibTeX RDF
20	Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner 0001, Jean-Philippe Diguet	A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
20	Zhenqi Wei, Peilin Liu, Rongdi Sun, Jun Dai, Zunquan Zhou, Xiangming Geng, Rendong Ying	HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
20	Gianluca Barbon, Michael Margolis, Filippo Palumbo, Franco Raimondi, Nick Weldin	Taking Arduino to the Internet of Things: The ASIP programming model.	Comput. Commun.	2016	DBLP DOI BibTeX RDF
20	Onno J. Boxma, Offer Kella, Uri Yechiali	An ASIP model with general gate opening intervals.	Queueing Syst. Theory Appl.	2016	DBLP DOI BibTeX RDF
20	Paolo Meloni, Francesca Palumbo, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo	MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
20	Nico Mentzer, Guillermo Payá Vayá, Holger Blume	Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
20	Ubaid Ahmad, Min Li 0001, Amir Amin, Meng Li 0012, Liesbet Van der Perre, Rudy Lauwereins, Sofie Pollin	An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
20	Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid	Concurrent memory subsystem and application optimization for ASIP design.	SAMOS	2016	DBLP DOI BibTeX RDF
20	Dunia Jamma, Omar Ahmed, Shawki Areibi, Gary Gréwal, Nicholas Molloy	Design exploration of ASIP architectures for the K-Nearest Neighbor machine-learning algorithm.	ICM	2016	DBLP DOI BibTeX RDF
20	Yao Qin, Hua Wang, Zhiping Jia, Hui Xia	A flexible and scalable implementation of elliptic curve cryptography over GF(p) based on ASIP.	IPCCC	2016	DBLP DOI BibTeX RDF
20	Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	An efficient embedded processor for object detection using ASIP methodology.	ASAP	2016	DBLP DOI BibTeX RDF
20	Andreas Karlsson	Design of Energy-Efficient High-Performance ASIP-DSP Platforms.		2016	RDF
20	Juan Fernando Eusse Giraldo, Christopher Williams 0004, Rainer Leupers	CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
20	Laura Micconi, Jan Madsen, Paul Pop	System-level synthesis of multi-ASIP platforms using an uncertainty model.	Integr.	2015	DBLP DOI BibTeX RDF
20	Xiaolin Chen, Andreas Minwegen, Bilal Syed Hussain, Anupam Chattopadhyay, Gerd Ascheid, Rainer Leupers	Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
20	Nuno Neves 0002, Nuno Sebastião, David Martins de Matos, Pedro Tomás, Paulo F. Flores, Nuno Roma	Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
20	Yao Xin, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, Theodore W. Berger	An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics.	IEEE ACM Trans. Comput. Biol. Bioinform.	2015	DBLP DOI BibTeX RDF
20	Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini	ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.	Future Gener. Comput. Syst.	2015	DBLP DOI BibTeX RDF
20		An Application Specific Instruction Set Processor (ASIP) for the Niederreiter Cryptosystem.	IACR Cryptol. ePrint Arch.	2015	DBLP BibTeX RDF
20	Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig	Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP.	DDECS	2015	DBLP DOI BibTeX RDF
20	Fang Xiao, Yiqing Zhou 0001, Shan Huang, Jiangnan Lin, Lin Liu	An ASIP based physical layer virtualization method of centralized radio access network.	IPCCC	2015	DBLP DOI BibTeX RDF
20	Mohammed A. El-Motaz, M. Wagih Ismail, Mohsen Raafat, Ali S. Faried, Mohammed A. Raghieb, Nassr M. Ismail, Sherif A. Hafez, Ahmed H. El-Kady, Esmaail A. El-Sayed, Mohamed A. Sharaf, Ibrahim Shazly, Wael E. Abd El-Kawi, Chadi M. Mohamed, Mohamed N. Elhidery, Karim Mohammed, Omar A. Nasr	A highly scalable vector oriented ASIP-based multi-standard digital receiver.	ICECS	2015	DBLP DOI BibTeX RDF
20	Peter Reichel, Jens Döge, Nico Peter, Christoph Hoppe, Andreas Reichel	An ASIP-based control system for Vision Chips with highly parallel signal processing.	ISIE	2015	DBLP DOI BibTeX RDF
20	Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai	A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems.	BioCAS	2015	DBLP DOI BibTeX RDF
20	Yuji Yokota, Shingo Yoshizawa, Hiroshi Ochi	ASIP implementation of a low complexity iterative BD precoder for MU-MIMO system.	ISCIT	2015	DBLP DOI BibTeX RDF
20	Mirco Bordoni, Michele Bottone, Bob Fields, Nikos Gorogiannis, Michael Margolis, Giuseppe Primiero, Franco Raimondi	Towards Cyber-physical Systems as Services: The ASIP Protocol.	SEsCPS@ICSE	2015	DBLP DOI BibTeX RDF
20	Anmol Gupta, Ashutosh Pal	Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications.	VLSID	2015	DBLP DOI BibTeX RDF
20	Laura Micconi	A Probabilistic Approach for the System-Level Design of Multi-ASIP Platforms.		2015	RDF
20	Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda	Retargeting Derivative-ASIP with Assembly Converter Tool.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
20	Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose	Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study.	CoRR	2014	DBLP BibTeX RDF
20	Rajitha Navarathna, Swarnalatha Radhakrishnan, Roshan G. Ragel	Loop Unrolling in Multi-pipeline ASIP Design.	CoRR	2014	DBLP BibTeX RDF
20	Yi Wang 0016, Yajun Ha	A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
20	Roel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal	BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching.	DDECS	2014	DBLP DOI BibTeX RDF
20	Nico Mentzer, Guillermo Payá Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter	Instruction-set extension for an ASIP-based SIFT feature extraction.	ICSAMOS	2014	DBLP DOI BibTeX RDF
20	Juan Fernando Eusse Giraldo, Christopher Williams 0004, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid	Pre-architectural performance estimation for ASIP design based on abstract processor models.	ICSAMOS	2014	DBLP DOI BibTeX RDF
20	Zdenek Prikryl	Fast Simulation of Pipeline in ASIP Simulators.	MTV	2014	DBLP DOI BibTeX RDF
20	Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue	A flexible ASIP architecture for connected components labeling in embedded vision applications.	DATE	2014	DBLP DOI BibTeX RDF
20	Nuno Sebastião, Paulo F. Flores, Nuno Roma	Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications.	HPCS	2014	DBLP DOI BibTeX RDF
20	Souhail Haggui, Imen Debbabi, Fethi Tlili	Enhanced implementation of morphological operators on a synthesizable ASIP.	ICMCS	2014	DBLP DOI BibTeX RDF
20	Ting Chen, Hengzhu Liu, Botao Zhang	A reconfigurable ASIP for high-throughput and flexible FFT processing in SDR environment.	ICDIP	2014	DBLP DOI BibTeX RDF
20	Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai	An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology.	BioCAS	2014	DBLP DOI BibTeX RDF
20	Zhenzhi Wu, Dake Liu	Flexible multistandard FEC processor design with ASIP methodology.	ASAP	2014	DBLP DOI BibTeX RDF
20	Ting Chen, Xiaowei Pan, Hengzhu Liu, Tiebin Wu	Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0.	ISQED	2014	DBLP DOI BibTeX RDF
20	Mahesh Nanjundappa, Sandeep K. Shukla	Compiling polychronous programs into conditional partial orders for ASIP synthesis.	FormaliSE	2014	DBLP DOI BibTeX RDF
20	Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda	A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
20	Lech Józwiak	HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications.	ISVLSI	2013	DBLP DOI BibTeX RDF
20	Yuankai Chen, Hai Zhou 0001	Resource-constrained high-level datapath optimization in ASIP design.	DATE	2013	DBLP DOI BibTeX RDF
20	Matthias Hartmann, Praveen Raghavan, Liesbet Van der Perre, Prashant Agrawal, Wim Dehaene	Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design.	DSD	2013	DBLP DOI BibTeX RDF
20	Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner 0001, Jean-Philippe Diguet	Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.	DSD	2013	DBLP DOI BibTeX RDF
20	Raymond Frijns, A. L. J. Kamp, Sander Stuijk, Jeroen Voeten, M. Bontekoe, K. J. A. Gemei, Henk Corporaal	Dataflow-Based Multi-ASIP Platform Approach for Digital Control Applications.	DSD	2013	DBLP DOI BibTeX RDF
20	Vianney Lapotre, Michael Hübner 0001, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet	An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.	ReCoSoC	2013	DBLP DOI BibTeX RDF
20	Juan Fernando Eusse, Christopher Williams 0004, Rainer Leupers	CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design.	ReCoSoC	2013	DBLP DOI BibTeX RDF
20	Laura Micconi, Deepak Gangadharan, Paul Pop, Jan Madsen	Multi-ASIP platform synthesis for real-time applications.	SIES	2013	DBLP DOI BibTeX RDF
20	Deepak Gangadharan, Laura Micconi, Paul Pop, Jan Madsen	Multi-ASIP platform synthesis for Event-Triggered applications with cost/performance trade-offs.	RTCSA	2013	DBLP DOI BibTeX RDF
20	Tuo Li 0001, Muhammad Shafique 0001, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran	DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.	ICCAD	2013	DBLP DOI BibTeX RDF
20	Shoko Nakatsuka, Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai	An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology.	BioCAS	2013	DBLP DOI BibTeX RDF
20	Laura Micconi, Rosilde Corvino, Deepak Gangadharan, Jan Madsen, Paul Pop, Lech Józwiak	Hierarchical DSE for multi-ASIP platforms.	MECO	2013	DBLP DOI BibTeX RDF
20	Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner 0001	Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.	ISCAS	2013	DBLP DOI BibTeX RDF
20	Nuno Neves 0002, Nuno Sebastião, Andre Patricio, David Martins de Matos, Pedro Tomás, Paulo F. Flores, Nuno Roma	BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment.	ASAP	2013	DBLP DOI BibTeX RDF
20	Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker 0001	ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores.	ISSoC	2013	DBLP DOI BibTeX RDF
20	Tuo Li 0001	Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.		2013	RDF