Search results for "COOL"

Hits ?▲	Authors	Title	Venue	Year	Link
39	Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham	A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39		2017 IEEE Symposium in Low-Power and High-Speed Chips, COOL Chips 2017, Yokohama, Japan, April 19-21, 2017	COOL Chips	2017	DBLP BibTeX RDF
39	Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano	Leveraging asymmetric body bias control for low power LSI design.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Min-Kwan Kee, Seung-Jin Lee, Hyun-Su Seon, Jongsung Lee 0003, Gi-Ho Park	Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Takumi Maruyama	SPARC64TM XII: Fujitsu's latest 12 core processor for mission critical servers.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Yu Pu, Giby Samson, Chunlei Shi, Dongkyu Park, Ken Easton, Rudy Beraha, J. Hadi, Mark Lin, E. Arvelo, J. Fatehi, J. Kumar, Moses Derkalousdian, P. Aghera, Adam Newham, H. Sheraji, Karam Chatha, R. McLaren, V. Ganesan, S. Namasivayam, Danny Butterfield, Ravi Shenoy, Rashid Attar	Blackghost: An ultra-low-power all-in-one 28nm CMOS SoC for Internet-of-Things.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi	An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Koji Nii, Hiroyuki Kondo	Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, Hoi-Jun Yoo	An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu	A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Takuya Toyoshima, Masayuki Sato 0001, Ryusuke Egawa, Hiroaki Kobayashi	An application-adaptive data allocation method for multi-channel memory.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Keita Azegami, Hayate Okuhara, Hideharu Amano	Body bias control for renewable energy source with a high inner resistance.	COOL Chips	2017	DBLP DOI BibTeX RDF
39	Mihir N. Mody, Hetul Sanghvi, Niraj Nandan, Shashank Dabral, Rajasekhar Allu, Rajat Sagar, Kedar Chitnis, Jason Jones, Brijesh Jadhav, Sujith Shivalingappa, Aish Dubey	A 216 GOPS flexible WDR Image Processor for ADAS SoC.	COOL Chips	2017	DBLP DOI BibTeX RDF
39		2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016	COOL Chips	2016	DBLP BibTeX RDF
39	Piyali Goswami, Yogesh Marathe, Kedar Chitnis, Koichi Saito	Thermal safety through Limp Home Mode for intelligent Rear View Camera Systems.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Hiroshi Inoue	How SIMD width affects energy efficiency: A case study on sorting.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, Tadaaki Yamauchi	A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Tadao Nakamura	Message from the advisory committee chair.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel	MuCCRA4-BB: A fine-grained body biasing capable DRP.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Hiroaki Nishi	Panel discussions "computing and communication evolution for IoT innovations".	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Makoto Ikeda, Fumio Arakawa	Message from the program committee chairs.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A cache partitioning mechanism to protect shared data for CMPs.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Hiroaki Kobayashi	Message from the organizing committee chair.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Yusuke Shirota, Shiyo Yoshimura, Satoshi Shirai, Tatsunori Kanai	Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima	ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Megumi Ito, Moriyoshi Ohara	A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Youchang Kim, Dongjoo Shin, Jinsu Lee, Hoi-Jun Yoo	A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots.	COOL Chips	2016	DBLP DOI BibTeX RDF
39	Kyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Junyoung Park 0002, Hoi-Jun Yoo	An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream.	COOL Chips	2016	DBLP DOI BibTeX RDF
39		2015 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XVIII, Yokohama, Japan, April 13-15, 2015	COOL Chips	2015	DBLP BibTeX RDF
39	Jun Zhou 0022, Huawei Li 0001, Tiancheng Wang, Ying Wang 0001, Xiaowei Li 0001	TURO: A lightweight turn-guided routing scheme for 3D NoCs.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa	An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann 0001, Wolfgang Rosenstiel	Fined-grained body biasing for frequency scaling in advanced SOI processes.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Akira Takeda, Akira Yokosawa, Shintaro Sano, Shunsuke Sasaki, Takeshi Kodaka, Takahiro Tokuyoshi, Toshiki Kizu	A novel energy-efficient data acquisition method for wearable devices.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano	A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Chengguang Han, Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	An energy-efficient dynamic memory address mapping mechanism.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	JinSeok Oh, Sungyu Kim, Eunji Jeong, Soo-Mook Moon	OS-less dynamic binary instrumentation for embedded firmware.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Anna Zhang, Jun Yao 0001, Yasuhiko Nakashima	Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, Karthikeyan Sankaralingam	MIAOW - An open source RTL implementation of a GPGPU.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Hideki Makiyama, Takumi Hasegawa, Yoshiki Yamamoto, Shinobu Okanishi, Keiichi Maekawa, Naoki Banno, Makoto Miyamura, Koichiro Okamoto, Noriyuki Iguchi, Yasuhiro Ogasahara, Hidekazu Oda, Shiro Kamohara, Yasushi Yamagata, Nobuyuki Sugii, Hiromitsu Hada	0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Anant Deval, Avinash Ananthakrishnan, Craig Forbell	Power management on 14 nm Intel® Core- M processor.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Injoon Hong, Dongjoo Shin, Youchang Kim, Kyeongryeol Bong, Seongwook Park, Kyuho Jason Lee, Hoi-Jun Yoo	A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal	An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Yusuke Shirota, Shiyo Yoshimura, Tatsunori Kanai	Electronic Paper Display update scheduler for extremely low power non-volatile embedded systems.	COOL Chips	2015	DBLP DOI BibTeX RDF
39	Shinpei Kato	Panel discussions computing technology for autonomous driving.	COOL Chips	2015	DBLP DOI BibTeX RDF
39		2014 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVII, Yokohama, Japan, April 14-16, 2014	COOL Chips	2014	DBLP BibTeX RDF
39	Jun Yao 0001, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka	A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Motoki Wada, Mikiko Sato, Mitaro Namiki	A fine grained power management supported by just-in-time compiler.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima, Hidetomo Kobayashi, Seiichi Yoneda, Atsuo Isobe, Naoaki Tsutsui, Suguru Hondo, Yasutaka Suzuki, Yutaka Okazaki, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Gensuke Goto, Masahiro Fujita, James Myers, Pekka Korpinen, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki	Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Ying Wang 0001, Yinhe Han 0001, Huawei Li 0001	A low power DRAM refresh control scheme for 3D memory cube.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Tadao Nakamura	Message from the advisory committee chair.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Hiroaki Kobayashi	Message from the organizing committee chair.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Masaki Kondo, Fumio Arakawa, Masato Edahiro	Establishing a standard interface between multi-manycore and software tools - SHIM.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Gyeonghoon Kim, Seongwook Park, Kyuho Jason Lee, Youchang Kim, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Junyoung Park 0002, Hoi-Jun Yoo	A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura	A low power NoC router using the marching memory through type.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro	Parallel design of control systems utilizing dead time for embedded multicore processors.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Yuttakon Yuttakonkit, Jun Yao 0001, Yasuhiko Nakashima	A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Gaku Nakagawa, Shuichi Oikawa	Language runtime support for NVM/DRAM hybrid main memory.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Jun'ichi Segawa, Yusuke Shirota, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai	Aggressive use of Deep Sleep mode in low power embedded systems.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Ye Gao, Masayuki Sato 0001, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	An energy optimization method for vector processing mechanisms.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Yunyun Jiang, Yi Yang 0033, Tian Xiao, Tianwei Sheng, Wenguang Chen	Kernel data race detection using debug register in Linux.	COOL Chips	2014	DBLP DOI BibTeX RDF
39	Makoto Ikeda, Fumio Arakawa	Message from the program committee chairs.	COOL Chips	2014	DBLP DOI BibTeX RDF
39		2013 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVI, Yokohama, Japan, April 17-19, 2013	COOL Chips	2013	DBLP BibTeX RDF
39	Masayuki Sato 0001, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A flexible insertion policy for dynamic cache resizing mechanisms.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Hiroaki Kobayashi	Message from the Organizing Committee Chair.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Sugako Otani, Naoshi Ishikawa, Hiroyuki Kondo	RXv2 processor core for low-power microcontrollers.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Wei Wang, Jun Yao 0001, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng	HW/SW approaches to accelerate GRAPES in an FU array.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara	Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Tadao Nakamura	Message from the Advisory Committee Chair.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Hidetomo Kobayashi, Kiyoshi Kato, Takuro Ohmaru, Seiichi Yoneda, Tatsuji Nishijima, Shuhei Maeda, Kazuaki Ohshima, Hikaru Tamura, Hiroyuki Tomatsu, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Jun Koyama, Shunpei Yamazaki	Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Bert Gyselinckx, Hiroshi Kanayama, Michael McCool, Shintaro Momose, Takeshi Kataoka, James Myers, Toshio Yoshida	Keynote & invited speaker's biography [7 biographies].	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Junyoung Park 0002, Injoon Hong, Gyeonghoon Kim, Youchang Kim, Kyuho Jason Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo	A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara	Automatic parallelization, performance predictability and power control for mobile-applications.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Vinod Pangracious, Habib Mehrez, Zied Marrakchi	Architecture level TSV count minimization methodology for 3D tree-based FPGA.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Kazuhisa Ishizaka, Takamichi Miyamoto, S. Akimoto, A. Iketani, T. Hosomi, Junji Sakai	Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Makoto Ikeda, Fumio Arakawa	Message from the Program Committee Chairs.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama 0003, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki	Hardware support for resource partitioning in real-time embedded systems.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Hao Zhang 0020, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Yoshio Masubuchi, Bert Gyselinckx, Michael McCool, Shintaro Momose, James Myers, Toshio Yoshida	Panel discussions the next step in processor evolution.	COOL Chips	2013	DBLP DOI BibTeX RDF
39	Hiroaki Kobayashi, Makoto Ikeda, Fumio Arakawa (eds.)	2012 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XV, Yokohama, Japan, April 18-20, 2012	COOL Chips	2012	DBLP BibTeX RDF
39	Tse-Wei Chen 0001, Makoto Ikeda	Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa	An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki	Dependable Responsive Multithreaded Processor for distributed real-time systems.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Koji Hashimoto	Poster preface.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano	Trade-off analysis of fine-grained power gating methods for functional units in a CPU.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Jinwook Oh, Gyeonghoon Kim, Junyoung Park 0002, Injoon Hong, Seungjin Lee 0001, Joo-Young Kim 0001, Hoi-Jun Yoo	A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda	A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Ye Gao, Naoki Shoji, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A media-oriented vector architectural extension with a high bandwidth cache system.	COOL Chips	2012	DBLP DOI BibTeX RDF
39	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation.	COOL Chips	2012	DBLP DOI BibTeX RDF
39		2011 IEEE Symposium on Low-Power and High-Speed Chips, Cool Chips XIV, Yokohama, Japan, 20-22 April, 2011	COOL Chips	2011	DBLP BibTeX RDF
39	Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa	A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Daejin Park, Tag Gon Kim, Chang-Min Kim, Sungho Kwak	A low-power sync processor with a floating-point timer and universal edge tracer for 3DTV active shutter glasses.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong	A new match line sensing technique in Content Addressable Memory.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano	FlexGrip™: A small and high-performance programmable hardware for highly sequential application.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Masato Motomura, Takafumi Aoki, Toru Awashima, Toru Baji, Masaaki Ishikawa	Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Hideki Yamada, Toshiyuki Yamagishi, Tomoya Suzuki, Kuniaki Ito, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa	A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	C. A. Court, Paul H. J. Kelly	Loop-Directed Mothballing: Power-gating execution units using fast analysis of inner loops.	COOL Chips	2011	DBLP DOI BibTeX RDF
39	Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato	An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.	COOL Chips	2011	DBLP DOI BibTeX RDF