Search results for "DPLL"

Hits ?▲	Authors	Title	Venue	Year	Link
21	Marco Favorito	Forward LTLf Synthesis: DPLL At Work.	IPS-RCRA-SPIRIT@AI*IA	2023	DBLP BibTeX RDF
21	Ivor Uhliarik	Enhancing and Evaluating the Product Fuzzy DPLL Solver.	SN Comput. Sci.	2022	DBLP DOI BibTeX RDF
21	Takuya Noguchi, Akihiro Fujiwara	An asynchronous P system with a DPLL algorithm for solving SAT.	Int. J. Netw. Comput.	2022	DBLP BibTeX RDF
21	Ping Lu, Minhan Chen, Shaishav Desai	An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications.	MWSCAS	2022	DBLP DOI BibTeX RDF
21	Jinghui Jiang, Zhenpei Huang, Qiao Xiang, Lu Tang 0004, Jiwu Shu	P4-DPLL: accelerating SAT solving using switching ASICs.	FFSPIN@SIGCOMM	2022	DBLP DOI BibTeX RDF
21	Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie	A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta	A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM.	ISCAS	2022	DBLP DOI BibTeX RDF
21	Lianbo Wu, Thomas Burger, Philipp Schönle, Qiuting Huang	A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
21	Martin Capek, Pavel Surynek	DPLL(MAPF): an Integration of Multi-Agent Path Finding and SAT Solving Technologies.	CoRR	2021	DBLP BibTeX RDF
21	Nikita Gaevoy	Hard satisfiable formulas for DPLL algorithms using heuristics with small memory.	CoRR	2021	DBLP BibTeX RDF
21	Hao Zheng, Eric Thompson, John Hogan, Daniel O'Hare	Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources.	NEWCAS	2021	DBLP DOI BibTeX RDF
21	Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi	A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.	ISSCC	2021	DBLP DOI BibTeX RDF
21	Takuya Noguchi, Akihiro Fujiwara	An asynchronous P system with a DPLL algorithm for solving a satisfiability problem.	CANDAR	2021	DBLP DOI BibTeX RDF
21	Martin Capek, Pavel Surynek	DPLL(MAPF): an Integration of Multi-Agent Path Finding and SAT Solving Technologies.	SOCS	2021	DBLP DOI BibTeX RDF
21	Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun 0001	A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
21	Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta	A Fast Settling Fractional-N DPLL With Loop-Order Switching.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
21	Cezar-Constantin Andrici, Stefan Ciobaca	Who Verifies the Verifiers? A Computer-Checked Implementation of the DPLL Algorithm in Dafny.	CoRR	2020	DBLP BibTeX RDF
21	Ivor Uhliarik	The Implementation of a Product Fuzzy DPLL Solver.	IJCCI	2020	DBLP DOI BibTeX RDF
21	Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi	17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.	ISSCC	2020	DBLP DOI BibTeX RDF
21	Lianbo Wu, Thomas Burger, Philipp Schönle, Qiuting Huang	A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
21	Sabyasachi Bhattacharyya, Aradhana Misra, Kandarpa Kumar Sarma	A BCH code assisted modified NCO based LSPF-DPLL topology for Nakagami-m, Rayleigh and Rician fading channels.	Digit. Commun. Networks	2019	DBLP DOI BibTeX RDF
21	Pavel Surynek	On the Tour Towards DPLL(MAPF) and Beyond.	CoRR	2019	DBLP BibTeX RDF
21	Cezar-Constantin Andrici, Stefan Ciobaca	Verifying the DPLL Algorithm in Dafny.	FROM	2019	DBLP DOI BibTeX RDF
21	Olivier Bailleux	Subsumption-driven clause learning with DPLL+restarts.	CoRR	2019	DBLP BibTeX RDF
21	Pavel Surynek	On the Tour Towards DPLL(MAPF) and Beyond.	DDC@AI*IA	2019	DBLP BibTeX RDF
21	Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng 0001, Rui Wu 0001, Kenichi Okada	A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
21	Umut Oztok, Adnan Darwiche	An Exhaustive DPLL Algorithm for Model Counting.	J. Artif. Intell. Res.	2018	DBLP DOI BibTeX RDF
21	Pallavi Paliwal, Debasattam Pal, Shalabh Gupta	Stability Analysis for Fast Settling Switched DPLL.	CoRR	2018	DBLP BibTeX RDF
21	Dusan Guller	Technical Foundations of a DPLL-Based SAT Solver for Propositional Gödel Logic.	IEEE Trans. Fuzzy Syst.	2018	DBLP DOI BibTeX RDF
21	Zhihong Luo, Guoxing Wang, Khalil Yousef, Benjamin Lau, Yong Lian 0001, Chun-Huat Heng	A 0.0129 mm2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
21	Xiaohua Huang, Han Liu, Woogeun Rhee, Zhihua Wang 0001	A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
21	Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun 0001	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
21	Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori	A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
21	Zuow-Zun Chen, Yen-Cheng Kuan, Yilei Li, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang	DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
21	Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb	Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
21	Andrew Reynolds 0001, Maverick Woo, Clark W. Barrett, David Brumley, Tianyi Liang, Cesare Tinelli	Scaling Up DPLL(T) String Solvers Using Context-Dependent Simplification.	CAV (2)	2017	DBLP DOI BibTeX RDF
21	Mohieddin Moradi, Mehdi Ehsanian	An FPGA based DPLL with fuzzy logic controllable loop filters.	ICM	2017	DBLP DOI BibTeX RDF
21	Bertram Felgenhauer, Aart Middeldorp	Constructing Cycles in the Simplex Method for DPLL(T).	ICTAC	2017	DBLP DOI BibTeX RDF
21	Ivor Uhliarik	Foundations of a DPLL-Based Solver for Fuzzy Answer Set Programs.	IJCCI (Selected Papers)	2017	DBLP DOI BibTeX RDF
21	Ioannis L. Syllaios	Hybrid-DPLL-based constant-envelope modulator for Internet-of-Things chipsets.	ISCAS	2017	DBLP DOI BibTeX RDF
21	Supeng Liu, Yuanjin Zheng	A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
21	Yiwei Wu, Hang Gong, Xiangwei Zhu, Gang Ou	A DPLL Method Applied to Clock Steering.	IEEE Trans. Instrum. Meas.	2016	DBLP DOI BibTeX RDF
21	Cheng-Ru Ho, Mike Shuo-Wei Chen	A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
21	Donald W. Loveland, Ashish Sabharwal, Bart Selman	DPLL: The Core of Modern Satisfiability Solvers.	Martin Davis on Computability, Computational Logic, and Mathematical Foundations	2016	DBLP DOI BibTeX RDF
21	Sabyasachi Bhattacharyya, Aradhana Misra, Kandarpa Kumar Sarma	A modified NCO based LSPF-DPLL Phase Resolver for wireless communication.	RAIT	2016	DBLP DOI BibTeX RDF
21	Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori	19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.	ISSCC	2016	DBLP DOI BibTeX RDF
21	Guy Katz, Clark W. Barrett, Cesare Tinelli, Andrew Reynolds 0001, Liana Hadarean	Lazy proofs for DPLL(T)-based SMT solvers.	FMCAD	2016	DBLP DOI BibTeX RDF
21	Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb	Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.	A-SSCC	2016	DBLP DOI BibTeX RDF
21	Basab Chatterjee, B. N. Biswas, Sudhabindu Ray	A novel DSP-based PFC-DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity.	Int. J. Commun. Syst.	2015	DBLP DOI BibTeX RDF
21	Masaki Azuma, Hiroomi Hikawa	Scalable Hardware Winner-Take-All Neural Network with DPLL.	IEICE Trans. Inf. Syst.	2015	DBLP DOI BibTeX RDF
21	Liana Hadarean, Alex Horn, Tim King 0001	A Concurrency Problem with Exponential DPLL(T) Proofs.	CoRR	2015	DBLP BibTeX RDF
21	Ulrich Berger 0001, Andrew Lawrence, Fredrik Nordvall Forsberg, Monika Seisenberger	Extracting verified decision procedures: DPLL and Resolution.	Log. Methods Comput. Sci.	2015	DBLP DOI BibTeX RDF
21	Khadija Bousmar, Fabrice Monteiro, Zineb Habbas, Sofiène Dellagi, Abbas Dandache	A new FPGA-based DPLL algorithm to improve SAT solvers.	ICM	2015	DBLP DOI BibTeX RDF
21	Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu	A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.	CICC	2015	DBLP DOI BibTeX RDF
21	Ioannis L. Syllaios, Henrik T. Jensen 0001	DPLL with hybrid ΔΣ phase/frequency detector.	ISCAS	2015	DBLP DOI BibTeX RDF
21	Tianyi Liang, Andrew Reynolds 0001, Cesare Tinelli, Clark W. Barrett, Morgan Deters	A DPLL(T) Theory Solver for a Theory of Strings and Regular Expressions.	CAV	2014	DBLP DOI BibTeX RDF
21	Masaki Azuma, Hiroomi Hikawa	Supervised learning of DPLL based winner-take-all neural network.	ICES	2014	DBLP DOI BibTeX RDF
21	Quoc-Sang Phan	Symbolic Execution as DPLL Modulo Theories.	ICCSW	2014	DBLP DOI BibTeX RDF
21	Younghoon Kim, Min-Ki Jeon, Changsik Yoo	Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control.	ISIC	2014	DBLP DOI BibTeX RDF
21	Olaf Beyersdorff, Nicola Galesi, Massimo Lauria	Parameterized Complexity of DPLL Search Procedures.	ACM Trans. Comput. Log.	2013	DBLP DOI BibTeX RDF
21	Min Zhou 0001, Fei He 0001, Bow-Yaw Wang, Ming Gu 0001, Jiaguang Sun 0001	A Unified Framework for DPLL(T) + Certificates.	J. Appl. Math.	2013	DBLP DOI BibTeX RDF
21	Till Berger, David Sabel	Parallelizing DPLL in Haskell.	Software Engineering (Workshops)	2013	DBLP BibTeX RDF
21	Dusan Guller	A DPLL Procedure for the Propositional Product Logic.	IJCCI	2013	DBLP DOI BibTeX RDF
21	R. G. H. van Uden, Chigo M. Okonkwo, Vincent A. J. M. Sleiffer, H.-S. Chen, Maxim Kuschnerov, Huug de Waardt, Antonius M. J. Koonen	Employing a single DPLL for joint carrier phase estimation in few-mode fiber transmission.	OFC/NFOEC	2013	DBLP BibTeX RDF
21	Hiroomi Hikawa	DPLL based hardware SOM with a new winner-take-all circuit.	IJCNN	2013	DBLP DOI BibTeX RDF
21	Martin Brain, Vijay Victor D'Silva, Leopold Haller, Alberto Griggio, Daniel Kroening	An Abstract Interpretation of DPLL(T).	VMCAI	2013	DBLP DOI BibTeX RDF
21	Masaki Azuma, Hiroomi Hikawa	A new winner-take-all neural network using DPLL and phase modulated signal.	ISPACS	2013	DBLP DOI BibTeX RDF
21	Mahfuza Farooque, Stéphane Graham-Lengrand, Assia Mahboubi	A bisimulation between DPLL(T) and a proof-search strategy for the focused sequent calculus.	LFMTP	2013	DBLP DOI BibTeX RDF
21	Konstantin Korovin	From Resolution and DPLL to Solving Arithmetic Constraints.	FroCos	2013	DBLP DOI BibTeX RDF
21	Surjadeep Sarkar, Basab Chatterjee, Ujjwal Maulik, Baidyanath Biswas	Elimination of truncation and round off error and enhancement of stability using a new split loop DPLL.	Int. J. Commun. Syst.	2012	DBLP DOI BibTeX RDF
21	Andrew Lawrence, Ulrich Berger 0001, Monika Seisenberger	Extracting a DPLL Algorithm.	MFPS	2012	DBLP DOI BibTeX RDF
21	Harold S. Connamacher	Exact thresholds for DPLL on random XOR-SAT and NP-complete extensions of XOR-SAT.	Theor. Comput. Sci.	2012	DBLP DOI BibTeX RDF
21	Dmitry Itsykson, Dmitry Sokolov 0001	Lower bounds for myopic DPLL algorithms with a cut heuristic.	Electron. Colloquium Comput. Complex.	2012	DBLP BibTeX RDF
21	Mahfuza Farooque, Stéphane Lengrand, Assia Mahboubi	Two simulations about DPLL(T)	CoRR	2012	DBLP BibTeX RDF
21	Dimitris Achlioptas, Ricardo Menchaca-Mendez	Exponential Lower Bounds for DPLL Algorithms on Satisfiable Random 3-CNF Formulas.	SAT	2012	DBLP DOI BibTeX RDF
21	Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala	A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
21	Dejan Jovanovic	SMT Beyond DPLL(T): A New Approach to Theory Solvers and Theory Combination.		2012	RDF
21	Youssef Hamadi, Saïd Jabbour, Cédric Piette, Lakhdar Sais	Deterministic Parallel DPLL.	J. Satisf. Boolean Model. Comput.	2011	DBLP DOI BibTeX RDF
21	Marcello Balduccini	Improving DPLL Solver Performance with Domain-Specific Heuristics: the ASP Case	CoRR	2011	DBLP BibTeX RDF
21	Qassim Nasir, Saleh R. Al-Araji	Linearized Phase Detector Zero Crossing DPLL Performance Evaluation in Faded Mobile Channels.	Circuits Syst.	2011	DBLP DOI BibTeX RDF
21	Dmitry Itsykson, Dmitry Sokolov 0001	Lower Bounds for Myopic DPLL Algorithms with a Cut Heuristic.	ISAAC	2011	DBLP DOI BibTeX RDF
21	Qassim Nasir, Saleh R. Al-Araji	Performance evaluation of Sigma Delta Zero Crossing DPLL.	ICECS	2011	DBLP DOI BibTeX RDF
21	Dmitry Itsykson, Dmitry Sokolov 0001	The Complexity of Inversion of Explicit Goldreich's Function by DPLL Algorithms.	CSR	2011	DBLP DOI BibTeX RDF
21	Olaf Beyersdorff, Nicola Galesi, Massimo Lauria	Parameterized Complexity of DPLL Search Procedures.	SAT	2011	DBLP DOI BibTeX RDF
21	Alexey Ignatiev, Alexander A. Semenov	DPLL+ROBDD Derivation Applied to Inversion of Some Cryptographic Functions.	SAT	2011	DBLP DOI BibTeX RDF
21	Tero Laitinen, Tommi A. Junttila, Ilkka Niemelä	Equivalence Class Based Parity Reasoning with DPLL(XOR).	ICTAI	2011	DBLP DOI BibTeX RDF
21	Matti Järvisalo	On the Relative Efficiency of DPLL and OBDDs with Axiom and Join.	CP	2011	DBLP DOI BibTeX RDF
21	Raihan Hassnain Kibria	Soft computing approaches to DPLL SAT solver optimization.		2011	RDF
21	Natarajan Shankar, Marc Vaucher	The Mechanical Verification of a DPLL-Based Satisfiability Solver.	LSFA	2010	DBLP DOI BibTeX RDF
21	Paul Beame, Russell Impagliazzo, Toniann Pitassi, Nathan Segerlind	Formula Caching in DPLL.	ACM Trans. Comput. Theory	2010	DBLP DOI BibTeX RDF
21	Ruzica Piskac, Leonardo Mendonça de Moura, Nikolaj S. Bjørner	Deciding Effectively Propositional Logic Using DPLL and Substitution Sets.	J. Autom. Reason.	2010	DBLP DOI BibTeX RDF
21	Filip Maric, Predrag Janicic	Formal Correctness Proof for DPLL Procedure.	Informatica	2010	DBLP BibTeX RDF
21	Dusan Guller	A DPLL Procedure for the Propositional Gödel Logic.	IJCCI (ICFC-ICNC)	2010	DBLP BibTeX RDF
21	Tero Laitinen, Tommi A. Junttila, Ilkka Niemelä	Extending Clause Learning DPLL with Parity Reasoning.	ECAI	2010	DBLP BibTeX RDF
21	Mate Soos	Enhanced Gaussian Elimination in DPLL-based SAT Solvers.	POS@SAT	2010	DBLP DOI BibTeX RDF
21	Chang-Hua Lin, Chien-Ming Wang, Min-Hsuan Hung, Shang-Po Hsieh	Reducing the Parasitic Capacitance Effect in LCD Panel for Backlight Module Based on Primary-Side Control and DPLL Technique.	IEEE Trans. Ind. Electron.	2009	DBLP DOI BibTeX RDF
21	Maria Paola Bonacina, Christopher Lynch, Leonardo Mendonça de Moura	On Deciding Satisfiability by DPLL(G+T) and Unsound Theorem Proving.	CADE	2009	DBLP DOI BibTeX RDF
21	Lukas Kroc, Ashish Sabharwal, Bart Selman	Relaxed DPLL Search for MaxSAT.	SAT	2009	DBLP DOI BibTeX RDF
21	G. Sripriya, Alan Bundy, Alan Smaill	Concurrent-distributed programming techniques for SAT using DPLL-stålmarck.	HPCS	2009	DBLP DOI BibTeX RDF
21	Peter Baumgartner 0001, Cesare Tinelli	The model evolution calculus as a first-order DPLL method.	Artif. Intell.	2008	DBLP DOI BibTeX RDF