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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | James R. Bell, Janet Beyers, Ronald E. Jonas |
Precision RISC Organization: An Independednt Operation For PA-RISC Products and Standards. |
COMPCON |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Jonathan W. Mills |
Coming to grips with a RISC: a report of the progress of the LOW RISC design group. |
SIGARCH Comput. Archit. News |
1987 |
DBLP DOI BibTeX RDF |
|
25 | Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi |
A hardware peripheral for Java bytecodes translation acceleration. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
stack folding, ASIC, RISC, Java processor |
25 | Rajeev Kumar 0004, Dipankar Das 0002 |
Code compression for performance enhancement of variable-length embedded processors. |
ACM Trans. Embed. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
bus switching, code decompression, instruction memory, variable-length ISAs, embedded systems, Code compression, RISC processor |
25 | Stefan Tillich, Johann Großschädl |
Power Analysis Resistant AES Implementation with Instruction Set Extensions. |
CHES |
2007 |
DBLP DOI BibTeX RDF |
embedded RISC processor, SPARC V8 architecture, SCA resistance, Advanced Encryption Standard, power analysis, instruction set extensions |
25 | Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini |
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping |
25 | Stefan Tillich, Johann Großschädl |
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. |
CHES |
2006 |
DBLP DOI BibTeX RDF |
embedded RISC processor, SPARC V8 architecture, Advanced Encryption Standard, instruction set extensions, efficient implementation |
25 | Kai Schramm, Christof Paar |
IT Security Project: Implementation of the Advanced Encryption Standard (AES) on a Smart Card. |
ITCC (1) |
2004 |
DBLP DOI BibTeX RDF |
RISC architecture, smart cards, AES, side channel attacks |
25 | Gaetan Allaert, Dirk Craeynest, Philippe Waroquiers |
European air traffic flow management: porting a large application to GNU/linux. |
SIGAda |
2003 |
DBLP DOI BibTeX RDF |
CFMU, ETFMS, GNU, HP-PA RISC, HP-UX, Korn shell, eurocontrol, intel 80x86, performance, Ada, C++, C, linux, portability, COTS, POSIX, GNAT, air traffic management |
25 | Yukikazu Nakamoto |
Operating System Supports to Enhance Fault Tolerance of Real-Time Systems. |
WORDS |
2003 |
DBLP DOI BibTeX RDF |
Virtual Memory Management, Translation Look a side Buffer (TLB), Real-time Operating System, RISC Processor |
25 | Peter Gottschling, Wolfgang E. Nagel |
An Efficient Parallel Linear Solver with a Cascadic Conjugate Gradient Method: Experience with Reality. |
Euro-Par |
2000 |
DBLP DOI BibTeX RDF |
floating point performance, matrix sparsity pattern, cascadic conjugate gradient method, risc processors |
25 | Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek |
A Parallel Multimedia Processor for Macroblock Based Compression Standards. |
ICIP (2) |
1997 |
DBLP DOI BibTeX RDF |
parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1 |
25 | Jeffrey K. Hollingsworth, Barton P. Miller, M. J. R. Goncalves, Oscar Naim, Zhichen Xu, Ling Zheng |
MDL: A Language and Compiler for Dynamic Program Instrumentation. |
IEEE PACT |
1997 |
DBLP DOI BibTeX RDF |
dynamic program instrumentation, running programs, instrumentation code, PA-RISC, Power 2 architecture, Alpha architecture, x86 architecture, Metric Description Language, Paradyn Parallel Performance Tools, platform independent descriptions, message channels, modules, MDL, nodes, procedures, application program, compiler generators, SPARC, files, dynamic code generation, performance data |
25 | Paul F. Stelling, Vojin G. Oklobdzija |
Implementing Multiply-Accumulate Operation in Multiplication Time. |
IEEE Symposium on Computer Arithmetic |
1997 |
DBLP DOI BibTeX RDF |
multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed |
25 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
25 | T. Boggess, F. Shirley |
High-performance scalable computing for real-time applications. |
ICCCN |
1997 |
DBLP DOI BibTeX RDF |
high-performance scalable computing, interconnect technologies, high-performance computing technologies, embedded military applications, heterogeneous computer nodes, high-throughput system area network, standardized intelligent node-to-network interface, LANai, Sanders, Ptolemy environment, high density interconnect packaging, avionics applications, PacketWay, Internet Engineering Task Force proposed standard, high speed inter-SAN encryption, simulation, modeling, real-time systems, reconfigurable computing, real-time applications, RISC, switched network, digital signal processor, Myrinet |
25 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating system construction by domain based approaches. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
system construction, domain based approaches, target system, abstract system specification, formal specification, specification, requirements, VHDL, digital systems, object-oriented approach, RISC processors |
25 | G. Braschi, Giovanni Danese, Ivo De Lotto, D. Dotti, M. Gallati, Francesco Leporati, M. Mazzoleni |
A Parallel Processing System for Simulations of Vortex Blob Interactions. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
vortex blob interactions, 2D incompressible flows, complex interacting circulations, parallelisation techniques, Parallel Virtual Machine environment, i860 Risc Intel units, simulation, parallel algorithms, parallel architectures, digital simulation, distributed memory systems, flow, physics computing, special purpose computers, special purpose computer, reduced instruction set computing, flow simulation, parallel processing system, transputer systems, vortices |
25 | Wentong Cai 0001, Alfred Heng, Peter J. Varman |
Benchmarking IBM SP1 system for SPMD programming. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
IBM SP1 system benchmarking, SPMD programming, IBM Scalable POWERparallel series, RISC System/6000 processing element, MPL, high performance switch, performance evaluation, parallel processing, message passing, distributed memory systems, PVM, communication overhead, distributed memory parallel computer, reduced instruction set computing, message passing libraries |
25 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating System-Level Design: From Specification to Architecture. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
system-level design automation, digital systems specification, system components, knowledge-based configuration system, object-oriented domain model, reduced instruction set computing, RISC processors, system functions |
25 | Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers |
Low-Power Embedded Microprocessor Design. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles |
25 | Sheng-Yih Guan, Avi Bleiweiss, Richard Lipes |
Parallel implementation of volume rendering on Denali graphics systems. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
computer graphic equipment, computer peripheral equipment, Denali graphics systems, 3D graphics systems, texture mapping capability, standard graphics pipeline, pipelined parallel architecture, Kubota Graphics Corporation, maximum intensity projection, iso-surface rendering, partitioning data allocation scheme, texture memory requirements, transformation and rasterization modules, frame buffer modules, parallel node, general purpose RISC processor, object parallelism, hardware ASICs, pixel memory, pixel parallelism, resource allocation, parallel architectures, volume rendering, pipeline processing, dynamic load balancing, image texture, parallel implementation, rendering (computer graphics), reduced instruction set computing, static load balancing |
25 | Vatsa Santhanam, Daryl Odnert |
Register Allocation Across Procedure and Module Boundaries. |
PLDI |
1990 |
DBLP DOI BibTeX RDF |
RISC |
25 | Dingju Chen |
Hierarchical blocking and data flow analysis for numerical linear algebra. |
SC |
1990 |
DBLP DOI BibTeX RDF |
RISC |
25 | Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba |
An Architecture of a Dataflow Single Chip Processor. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
RISC |
25 | Paul A. Karger |
Using Registers to Optimize Cross-Domain Call Performance. |
ASPLOS |
1989 |
DBLP DOI BibTeX RDF |
RISC |
25 | Keshav Pingali |
Lazy evaluation and the logic variable. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
RISC, Miranda |
25 | Fred C. Chow, Steven Correll, Mark I. Himelstein, Earl Killian, Larry Weber |
How Many Addressing Modes are Enough? |
ASPLOS |
1987 |
DBLP DOI BibTeX RDF |
RISC |
22 | Wolfgang Schreiner |
The RISC ProofNavigator: a proving assistant for program verification in the classroom. |
Formal Aspects Comput. |
2009 |
DBLP DOI BibTeX RDF |
Interactive proving assistants, Teaching formal methods, Computer-aided verification |
22 | Trung-Nghia Vu, Syng-Yup Ohn, Chul-Woo Kim |
RISC: A New Filter Approach for Feature Selection from Proteomic Data. |
ICMB |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Kevin D. Kissell |
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Salah Merniz, Mohamed Benmohammed |
A Methodology for the Formal Verification of RISC Microprocessors A Functional Approach. |
AICCSA |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mark G. Arnold |
A RISC Processor with Redundant LNS Instructions. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
22 | K. S. Tham, Douglas L. Maskell |
Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001 |
An automated development framework for a RISC processor with reconfigurable instruction set extensions. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung |
Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications. |
ISNN (2) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Paul Capewell, Ian Watson |
A RISC Hardware Platform for Low Power Java. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier |
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Low-Cost Software-Based Self-Testing of RISC Processor Cores. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ricardo Chaves, Leonel Sousa |
RDSP: A RISC DSP based on Residue Number System. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno |
A New MPEG-2 Solution Using a 2nd ALU in the RISC. |
KES |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Forrest Brewer, Steve Haynal |
Symbolic NFA scheduling of a RISC microprocessor. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim |
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Michael Gschwind, Valentina Salapura, Dietmar Maurer |
FPGA prototyping of a RISC processor core for embedded applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda |
MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
microprocessor, decoder, MPEG, AAC |
22 | Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain |
Expression-tree-based algorithms for code compression on embedded RISC architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Hui Wu 0001, Joxan Jaffar, Roland H. C. Yap |
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
inter-instructional latency, instruction scheduling, feasible schedule, deadline constraints |
22 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco |
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Fault Injection, Software Fault-Tolerance |
22 | Hui Wu 0001, Joxan Jaffar, Roland H. C. Yap |
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies. |
CP |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Keith D. Cooper, Nathaniel McIntosh |
Enhanced Code Compression for Embedded RISC Processors. |
PLDI |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada |
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch |
22 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda |
Energy optimization of multilevel cache architectures for RISC and CISC processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Thomas W. Albrecht, Johann Notbauer, Stefan Rohringer |
HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
22 | Ramesh C. Agarwal |
A Super Scalar Sort Algorithm for RISC Processors. |
SIGMOD Conference |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Russell D. Meier 0001 |
Rapid prototyping of a RISC architecture for implementation in FPGAs. |
FCCM |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Sofiène Tahar, Ramayya Kumar |
Implementing a Methodology for Formally Verifying RISC Processors in HOL. |
HUG |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Olga Caprotti |
Extending RISC-CLP (Real) to Handle Symbolic Functions. |
DISCO |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Petr Kroha |
Code Generation for a RISC Machine. |
CC |
1988 |
DBLP DOI BibTeX RDF |
|
18 | Kazim Yumbul, Erkay Savas |
Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit. |
SIN |
2009 |
DBLP DOI BibTeX RDF |
security, computer architecture, public key cryptography, instruction set extensions, cryptographic algorithms, aes |
18 | Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001 |
Systematic Software-Based Self-Test for Pipelined Processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Analyzing Functional Coverage in Bounded Model Checking. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek |
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Chih-Hsu Yen, Yu-Shiang Lin, Bing-Fei Wu |
An efficient implementation of a low-complexity MP3 algorithm with a stream cipher. |
Multim. Tools Appl. |
2007 |
DBLP DOI BibTeX RDF |
DSP, DRM, MP3, Multimedia security, Low complexity |
18 | Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch |
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro |
A low-SER efficient core processor architecture for future technologies. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Tomas Dedek, Tomas Marek, Tomás Martínek |
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Jeabin Lee, Byeong-Gyu Nam, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo |
A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. |
EUC |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung |
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation |
18 | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. |
PDCAT |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Sarosh H. Patel, Rajeev Sanyal, Tarek M. Sobh |
RISCBOT: A WWW-Enabled Mobile Surveillance and Identification Robot. |
J. Intell. Robotic Syst. |
2006 |
DBLP DOI BibTeX RDF |
image processing, wireless, character recognition, autonomous robot, telerobotics |
18 | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Jianying Peng, Xing Qin, Jian Yang 0015, Xiaolang Yan, Xiexiong Chen |
A Programmable Bitstream Parser for Multiple Video Coding Standards. |
ICICIC (3) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
A portable specification of zero-overhead looping control hardware applied to embedded processors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Alexandros C. Dimopoulos, Christos Pavlatos, Ioannis Panagopoulos, George K. Papakonstantinou |
An Efficient Hardware Implementation for AI Applications. |
SETN |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Yijun Liu, Stephen B. Furber |
A Low Power Embedded Dataflow Coprocessor. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian 0001, Neda Zolfaghari |
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Gary Gostin, Jean-Francois Collard, Kirby Collins |
The architecture of the HP Superdome shared-memory multiprocessor. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
|
18 | A. Murat Fiskiran, Ruby B. Lee |
On-Chip Lookup Tables for Fast Symmetric-Key Encryption. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis |
Software-Based Self-Test for Pipelined Processors: A Case Study. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Sarah Monisha Pulimood, Boumediene Belkhouche |
A Mobile Computational model for Internet programming. |
ACM Southeast Regional Conference |
2004 |
DBLP DOI BibTeX RDF |
Internet programming, mobile computational model, mobile computation |
18 | Johann Großschädl, Erkay Savas |
Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m). |
CHES |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Matjaz Verderber, Andrej Zemva, Damjan Lampret |
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
18 | George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis |
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ryuichi Takahashi, Hajime Ohiwa |
Situated Learning on FPGA for Superscalar Microprocessor Design Education. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Matjaz Verderber, Andrej Zemva, Andrej Trost |
HW/SW Codesign of the MPEG-2 Video Decoder. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
18 | James O. Hamblen |
Using an FPGA-based SOC Approach for Senior Design Projects. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch |
Hardware/Software Trade-Offs for Advanced 3G Channel Coding. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses |
A Flexible Architecture for H.263 Video Coding. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
Design of Application Specific CISC Using PEAS-III. |
IEEE International Workshop on Rapid System Prototyping |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo |
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Tyng-Yeu Liang, Ce-Kuen Shieh, Jun-Qi Li |
An Effective Selection Policy for Load Balancing in Software DSM. |
ICPP |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack |
Instruction Set Extensions for MPEG-4 Video. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Byung-Sun Yang, Soo-Mook Moon, Seongbae Park, Junpyo Lee, SeungIl Lee, Jinpyo Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman |
LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation. |
IEEE PACT |
1999 |
DBLP DOI BibTeX RDF |
Java JIT compilation, register allocation |
18 | Jörg Hilgenstock, Klaus Herrmann 0002, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch |
A Video Signal Processor for MIMD Multiprocessing. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Hyun-Kyu Yun, Aaron Smith, Harvey F. Silverman |
Speech recognition HMM training on reconfigurable parallel processor. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
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