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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | James R. Bell, Janet Beyers, Ronald E. Jonas |
Precision RISC Organization: An Independednt Operation For PA-RISC Products and Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28 - March 4, 1994, pp. 40-46, 1994, IEEE Computer Society, 0-8186-5380-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Jonathan W. Mills |
Coming to grips with a RISC: a report of the progress of the LOW RISC design group. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 15(1), pp. 53-62, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
25 | Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi |
A hardware peripheral for Java bytecodes translation acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 552-553, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
stack folding, ASIC, RISC, Java processor |
25 | Rajeev Kumar 0004, Dipankar Das 0002 |
Code compression for performance enhancement of variable-length embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(3), pp. 35:1-35:36, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus switching, code decompression, instruction memory, variable-length ISAs, embedded systems, Code compression, RISC processor |
25 | Stefan Tillich, Johann Großschädl |
Power Analysis Resistant AES Implementation with Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 303-319, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded RISC processor, SPARC V8 architecture, SCA resistance, Advanced Encryption Standard, power analysis, instruction set extensions |
25 | Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini |
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 167-172, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping |
25 | Stefan Tillich, Johann Großschädl |
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 270-284, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
embedded RISC processor, SPARC V8 architecture, Advanced Encryption Standard, instruction set extensions, efficient implementation |
25 | Kai Schramm, Christof Paar |
IT Security Project: Implementation of the Advanced Encryption Standard (AES) on a Smart Card. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Conference on Information Technology: Coding and Computing (ITCC'04), Volume 1, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 176-180, 2004, IEEE Computer Society, 0-7695-2108-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
RISC architecture, smart cards, AES, side channel attacks |
25 | Gaetan Allaert, Dirk Craeynest, Philippe Waroquiers |
European air traffic flow management: porting a large application to GNU/linux. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGAda ![In: Proceedings of the 2003 Annual ACM SIGAda International Conference on Ada: The Engineering of Correct and Reliable Software for Real-Time & Distributed Systems using Ada and Related Technologies 2003, San Diego, CA, USA, December 7-11, 2003, pp. 29-37, 2003, ACM, 1-58113-476-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CFMU, ETFMS, GNU, HP-PA RISC, HP-UX, Korn shell, eurocontrol, intel 80x86, performance, Ada, C++, C, linux, portability, COTS, POSIX, GNAT, air traffic management |
25 | Yukikazu Nakamoto |
Operating System Supports to Enhance Fault Tolerance of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WORDS ![In: 8th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2003), 15-17 January 2003, Guadalajara, Mexico, pp. 10-17, 2003, IEEE Computer Society, 0-7695-1929-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Virtual Memory Management, Translation Look a side Buffer (TLB), Real-time Operating System, RISC Processor |
25 | Peter Gottschling, Wolfgang E. Nagel |
An Efficient Parallel Linear Solver with a Cascadic Conjugate Gradient Method: Experience with Reality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 784-794, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
floating point performance, matrix sparsity pattern, cascadic conjugate gradient method, risc processors |
25 | Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek |
A Parallel Multimedia Processor for Macroblock Based Compression Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 570-573, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1 |
25 | Jeffrey K. Hollingsworth, Barton P. Miller, M. J. R. Goncalves, Oscar Naim, Zhichen Xu, Ling Zheng |
MDL: A Language and Compiler for Dynamic Program Instrumentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 201-, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
dynamic program instrumentation, running programs, instrumentation code, PA-RISC, Power 2 architecture, Alpha architecture, x86 architecture, Metric Description Language, Paradyn Parallel Performance Tools, platform independent descriptions, message channels, modules, MDL, nodes, procedures, application program, compiler generators, SPARC, files, dynamic code generation, performance data |
25 | Paul F. Stelling, Vojin G. Oklobdzija |
Implementing Multiply-Accumulate Operation in Multiplication Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 99-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed |
25 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 201-210, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
25 | T. Boggess, F. Shirley |
High-performance scalable computing for real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1997), September 22-25, 1997 Las Vegas, NV, USA, pp. 332-335, 1997, IEEE Computer Society, 0-8186-8186-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
high-performance scalable computing, interconnect technologies, high-performance computing technologies, embedded military applications, heterogeneous computer nodes, high-throughput system area network, standardized intelligent node-to-network interface, LANai, Sanders, Ptolemy environment, high density interconnect packaging, avionics applications, PacketWay, Internet Engineering Task Force proposed standard, high speed inter-SAN encryption, simulation, modeling, real-time systems, reconfigurable computing, real-time applications, RISC, switched network, digital signal processor, Myrinet |
25 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating system construction by domain based approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 336-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
system construction, domain based approaches, target system, abstract system specification, formal specification, specification, requirements, VHDL, digital systems, object-oriented approach, RISC processors |
25 | G. Braschi, Giovanni Danese, Ivo De Lotto, D. Dotti, M. Gallati, Francesco Leporati, M. Mazzoleni |
A Parallel Processing System for Simulations of Vortex Blob Interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 115-122, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
vortex blob interactions, 2D incompressible flows, complex interacting circulations, parallelisation techniques, Parallel Virtual Machine environment, i860 Risc Intel units, simulation, parallel algorithms, parallel architectures, digital simulation, distributed memory systems, flow, physics computing, special purpose computers, special purpose computer, reduced instruction set computing, flow simulation, parallel processing system, transputer systems, vortices |
25 | Wentong Cai 0001, Alfred Heng, Peter J. Varman |
Benchmarking IBM SP1 system for SPMD programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 430-, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
IBM SP1 system benchmarking, SPMD programming, IBM Scalable POWERparallel series, RISC System/6000 processing element, MPL, high performance switch, performance evaluation, parallel processing, message passing, distributed memory systems, PVM, communication overhead, distributed memory parallel computer, reduced instruction set computing, message passing libraries |
25 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating System-Level Design: From Specification to Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 104-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
system-level design automation, digital systems specification, system components, knowledge-based configuration system, object-oriented domain model, reduced instruction set computing, RISC processors, system functions |
25 | Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers |
Low-Power Embedded Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 600-605, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles |
25 | Sheng-Yih Guan, Avi Bleiweiss, Richard Lipes |
Parallel implementation of volume rendering on Denali graphics systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 700-706, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
computer graphic equipment, computer peripheral equipment, Denali graphics systems, 3D graphics systems, texture mapping capability, standard graphics pipeline, pipelined parallel architecture, Kubota Graphics Corporation, maximum intensity projection, iso-surface rendering, partitioning data allocation scheme, texture memory requirements, transformation and rasterization modules, frame buffer modules, parallel node, general purpose RISC processor, object parallelism, hardware ASICs, pixel memory, pixel parallelism, resource allocation, parallel architectures, volume rendering, pipeline processing, dynamic load balancing, image texture, parallel implementation, rendering (computer graphics), reduced instruction set computing, static load balancing |
25 | Vatsa Santhanam, Daryl Odnert |
Register Allocation Across Procedure and Module Boundaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 28-39, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RISC |
25 | Dingju Chen |
Hierarchical blocking and data flow analysis for numerical linear algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 12-19, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RISC |
25 | Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba |
An Architecture of a Dataflow Single Chip Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 46-53, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
25 | Paul A. Karger |
Using Registers to Optimize Cross-Domain Call Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 194-204, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
25 | Keshav Pingali |
Lazy evaluation and the logic variable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 2nd international conference on Supercomputing, ICS 1988, Saint Malo, France, July 4-8, 1988, pp. 560-572, 1988, ACM, 0-89791-272-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
RISC, Miranda |
25 | Fred C. Chow, Steven Correll, Mark I. Himelstein, Earl Killian, Larry Weber |
How Many Addressing Modes are Enough? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 117-121, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
RISC |
22 | Wolfgang Schreiner |
The RISC ProofNavigator: a proving assistant for program verification in the classroom. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 21(3), pp. 277-291, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Interactive proving assistants, Teaching formal methods, Computer-aided verification |
22 | Trung-Nghia Vu, Syng-Yup Ohn, Chul-Woo Kim |
RISC: A New Filter Approach for Feature Selection from Proteomic Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMB ![In: Medical Biometrics, First International Conference, ICMB 2008, Hong Kong, China, January 4-5, 2008, Proceedings, pp. 17-24, 2008, Springer, 978-3-540-77410-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Kevin D. Kissell |
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 9-21, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Salah Merniz, Mohamed Benmohammed |
A Methodology for the Formal Verification of RISC Microprocessors A Functional Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 13-16 May 2007, Amman, Jordan, pp. 492-499, 2007, IEEE Computer Society, 1-4244-1030-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mark G. Arnold |
A RISC Processor with Redundant LNS Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 475-482, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | K. S. Tham, Douglas L. Maskell |
Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001 |
An automated development framework for a RISC processor with reconfigurable instruction set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung |
Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 1340-1349, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 133-137, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Paul Capewell, Ian Watson |
A RISC Hardware Platform for Low Power Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 138-143, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier |
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 39-48, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Low-Cost Software-Based Self-Testing of RISC Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10714-10719, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ricardo Chaves, Leonel Sousa |
RDSP: A RISC DSP based on Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 128-137, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno |
A New MPEG-2 Solution Using a 2nd ALU in the RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 7th International Conference, KES 2003, Oxford, UK, September 3-5, 2003, Proceedings, Part II, pp. 734-740, 2003, Springer, 3-540-40804-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Forrest Brewer, Steve Haynal |
Symbolic NFA scheduling of a RISC microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 429-434, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim |
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 163-172, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Michael Gschwind, Valentina Salapura, Dietmar Maurer |
FPGA prototyping of a RISC processor core for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 241-250, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda |
MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 29(3), pp. 247-254, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
microprocessor, decoder, MPEG, AAC |
22 | Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain |
Expression-tree-based algorithms for code compression on embedded RISC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 530-533, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Hui Wu 0001, Joxan Jaffar, Roland H. C. Yap |
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 281-290, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
inter-instructional latency, instruction scheduling, feasible schedule, deadline constraints |
22 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco |
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 17-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fault Injection, Software Fault-Tolerance |
22 | Hui Wu 0001, Joxan Jaffar, Roland H. C. Yap |
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2000, 6th International Conference, Singapore, September 18-21, 2000, Proceedings, pp. 457-469, 2000, Springer, 3-540-41053-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Keith D. Cooper, Nathaniel McIntosh |
Enhanced Code Compression for Embedded RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, May 1-4, 1999, pp. 139-149, 1999, ACM, 1-58113-094-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada |
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 279-280, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch |
22 | Uming Ko, Poras T. Balsara, Ashwini K. Nanda |
Energy optimization of multilevel cache architectures for RISC and CISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 299-308, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Thomas W. Albrecht, Johann Notbauer, Stefan Rohringer |
HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 808-811, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
22 | Ramesh C. Agarwal |
A Super Scalar Sort Algorithm for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 1996 ACM SIGMOD International Conference on Management of Data, Montreal, Quebec, Canada, June 4-6, 1996., pp. 240-246, 1996, ACM Press, 978-0-89791-794-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Russell D. Meier 0001 |
Rapid prototyping of a RISC architecture for implementation in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 190-196, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Sofiène Tahar, Ramayya Kumar |
Implementing a Methodology for Formally Verifying RISC Processors in HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HUG ![In: Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings, pp. 281-294, 1993, Springer, 3-540-57826-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Olga Caprotti |
Extending RISC-CLP (Real) to Handle Symbolic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISCO ![In: Design and Implementation of Symbolic Computation Systems, International Symposium, DISCO '93, Gmunden, Austria, September 15-17, 1993, Proceedings, pp. 241-255, 1993, Springer, 3-540-57235-X. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Petr Kroha |
Code Generation for a RISC Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Compilers and High Speed Compilation, 2nd CCHSC Workshop, Berlin GDR, October 10-14, 1988, Proceedings, pp. 204-214, 1988, Springer, 3-540-51364-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
18 | Kazim Yumbul, Erkay Savas |
Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIN ![In: Proceedings of the 2nd International Conference on Security of Information and Networks, SIN 2009, Gazimagusa, North Cyprus, October 6-10, 2009, pp. 143-151, 2009, ACM, 978-1-60558-412-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
security, computer architecture, public key cryptography, instruction set extensions, cryptographic algorithms, aes |
18 | Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001 |
Systematic Software-Based Self-Test for Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1441-1453, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Analyzing Functional Coverage in Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1305-1314, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek |
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 296-301, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Chih-Hsu Yen, Yu-Shiang Lin, Bing-Fei Wu |
An efficient implementation of a low-complexity MP3 algorithm with a stream cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 35(3), pp. 335-355, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DSP, DRM, MP3, Multimedia security, Low complexity |
18 | Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch |
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 241-250, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 165-170, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro |
A low-SER efficient core processor architecture for future technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1448-1453, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Tomas Dedek, Tomas Marek, Tomás Martínek |
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 648-651, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Jeabin Lee, Byeong-Gyu Nam, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo |
A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2112-2115, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 196-208, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung |
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 594-599, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation |
18 | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), 3-6 December 2007, Adelaide, Australia, pp. 185-192, 2007, IEEE Computer Society, 0-7695-3049-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Sarosh H. Patel, Rajeev Sanyal, Tarek M. Sobh |
RISCBOT: A WWW-Enabled Mobile Surveillance and Identification Robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 45(1), pp. 15-30, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
image processing, wireless, character recognition, autonomous robot, telerobotics |
18 | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
A design flow for configurable embedded processors based on optimized instruction set extension synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 581-586, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Jianying Peng, Xing Qin, Jian Yang 0015, Xiaolang Yan, Xiexiong Chen |
A Programmable Bitstream Parser for Multiple Video Coding Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (3) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 609-612, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
A portable specification of zero-overhead looping control hardware applied to embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Alexandros C. Dimopoulos, Christos Pavlatos, Ioannis Panagopoulos, George K. Papakonstantinou |
An Efficient Hardware Implementation for AI Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETN ![In: Advances in Artificial Intelligence, 4th Helenic Conference on AI, SETN 2006, Heraklion, Crete, Greece, May 18-20, 2006, Proceedings, pp. 35-45, 2006, Springer, 3-540-34117-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Yijun Liu, Stephen B. Furber |
A Low Power Embedded Dataflow Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 246-247, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1060-1061, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian 0001, Neda Zolfaghari |
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 227-230, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Gary Gostin, Jean-Francois Collard, Kirby Collins |
The architecture of the HP Superdome shared-memory multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 239-245, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | A. Murat Fiskiran, Ruby B. Lee |
On-Chip Lookup Tables for Fast Symmetric-Key Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 356-363, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis |
Software-Based Self-Test for Pipelined Processors: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 535-543, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Sarah Monisha Pulimood, Boumediene Belkhouche |
A Mobile Computational model for Internet programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, Huntsville, Alabama, USA, April 2-3, 2004, pp. 347-352, 2004, ACM, 1-58113-870-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Internet programming, mobile computational model, mobile computation |
18 | Johann Großschädl, Erkay Savas |
Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 133-147, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Matjaz Verderber, Andrej Zemva, Damjan Lampret |
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20238-20243, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis |
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20014-20019, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ryuichi Takahashi, Hajime Ohiwa |
Situated Learning on FPGA for Superscalar Microprocessor Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 243-, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Matjaz Verderber, Andrej Zemva, Andrej Trost |
HW/SW Codesign of the MPEG-2 Video Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 179, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | James O. Hamblen |
Using an FPGA-based SOC Approach for Senior Design Projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 18-19, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch |
Hardware/Software Trade-Offs for Advanced 3G Channel Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 396-401, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses |
A Flexible Architecture for H.263 Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 70-77, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
Design of Application Specific CISC Using PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 12-17, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo |
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 9-10, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Tyng-Yeu Liang, Ce-Kuen Shieh, Jun-Qi Li |
An Effective Selection Policy for Load Balancing in Software DSM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2000 International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, August 21-24, 2000, pp. 105-114, 2000, IEEE Computer Society, 0-7695-0768-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack |
Instruction Set Extensions for MPEG-4 Video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 23(1), pp. 27-49, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Byung-Sun Yang, Soo-Mook Moon, Seongbae Park, Junpyo Lee, SeungIl Lee, Jinpyo Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman |
LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 128-138, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Java JIT compilation, register allocation |
18 | Jörg Hilgenstock, Klaus Herrmann 0002, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch |
A Video Signal Processor for MIMD Multiprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 50-55, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Hyun-Kyu Yun, Aaron Smith, Harvey F. Silverman |
Speech recognition HMM training on reconfigurable parallel processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 242-243, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
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