Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Maurizio Bruno, Alberto Macii, Massimo Poncino	A Statistic Power Model for Non-synthetic RTL Operators.	PATMOS	2003	DBLP DOI BibTeX RDF
39	Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Test Pattern Generation for High Quality Loosely Deterministic BIST.	DATE	2003	DBLP DOI BibTeX RDF
39	Kee Sup Kim, Rathish Jayabharathi, Craig Carstens	SpeedGrade: An RTL Path Delay Fault Simulator.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
39	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
39	Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams	BIST hardware synthesis for RTL data paths based on testcompatibility classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
39	Nazanin Mansouri, Ranga Vemuri	Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.	DATE	1999	DBLP DOI BibTeX RDF
39	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
39	Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen	A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications.	DAC	1997	DBLP DOI BibTeX RDF
39	Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung	A C-Based RTL Design Verification Methodology for Complex Microprocessor.	DAC	1997	DBLP DOI BibTeX RDF	C
33	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Andrea Fedeli	Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	hybrid, RTL, design flow, TLM, assertion-based verification
33	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
32	Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard	Maintaining consistency between systemC and RTL system designs.	DAC	2006	DBLP DOI BibTeX RDF	SPIRIT, transactor, verification, systemC, RTL, TLM, testbench, VIP
32	Li Shen 0002	RTL Concurrent Fault Simulation.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, high-level testing, circuit modeling
32	M. Balakrishnan, Heman Khanna	Allocation of FIFO structures in RTL data paths.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	synthesis, RTL, ILP, FIFO, data path
32	Lionel Bening	A Two-State Methodology for RTL Logic Simulation.	DAC	1999	DBLP DOI BibTeX RDF	2-state, X-state, pessimism, simulation, optimism, random, initialization, RTL
32	Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen	High-level languages: the future or a passing fad?	FPGA	2007	DBLP DOI BibTeX RDF	high-level design languages, RTL design
32	Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo	Automatic Partitioner for Behavior Level Distributed Logic Simulation.	FORTE	2005	DBLP DOI BibTeX RDF	RTL level partitioner, behavior level partitioner, distributed simulation, parallel simulation
32	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick	The scaling challenge: can correct-by-construction design help?	ISPD	2003	DBLP DOI BibTeX RDF	clocked repeaters, correct-by-construction design, design fabrics, post-RTL design, routing, interconnect, placement, logic synthesis, scaling, technology mapping, repeaters
32	Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy	Synthesis of Scan Chains for Netlist Descriptions at RT-Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	scan synthesis, design for testability (DFT), register transfer level (RTL)
32	Kavel M. Büyüksahin, Farid N. Najm	High-level power estimation with interconnect effects.	ISLPED	2000	DBLP DOI BibTeX RDF	high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
32	Kazushige Higuchi, Kazuhiro Shirakawa	Innovative System-level Design Environment Based on FORM for Transport Processing System.	DATE	1998	DBLP DOI BibTeX RDF	Transport processing system, RTL generation, Specification editor, Formal specification, System design, System level simulation
32	Cheng-Ta Hsieh, Qing Wu 0002, Chih-Shun Ding, Massoud Pedram	Statistical sampling and regression analysis for RT-level power evaluation.	ICCAD	1996	DBLP DOI BibTeX RDF	RT-Level power evaluation, power macro-modeling formulation, statistical analysis, random sampling, regression analysis, statistical sampling, regression estimator, RTL simulation
32	Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu 0002, Massoud Pedram	Stratified random sampling for power estimation.	ICCAD	1996	DBLP DOI BibTeX RDF	RT-Level power evaluation, power macro-modeling formulation, statistical analysis, random sampling, regression analysis, statistical sampling, regression estimator, RTL simulation
32	Jesse D. Bingham, John Erickson, Gaurav Singh, Flemming Andersen	Industrial strength refinement checking.	FMCAD	2009	DBLP DOI BibTeX RDF
32	Hiren D. Patel, Sandeep K. Shukla	On Cosimulating Multiple Abstraction-Level System-Level Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
32	Christian Haufe, Frank Rogin	Ad-Hoc Translations to Close Verilog Semantics Gap.	DDECS	2008	DBLP DOI BibTeX RDF
32	Wei-Min Wu, Min-Chuan Chen	USAT: An Integrated Platform for Satisfiability Solving and Model Checking.	CSSE (4)	2008	DBLP DOI BibTeX RDF
32	Loganathan Lingappan, Niraj K. Jha	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
32	Loganathan Lingappan, Niraj K. Jha	Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Gaurav Singh 0006, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
32	Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull	Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.	DATE	2007	DBLP DOI BibTeX RDF
32	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull	Interactive presentation: Implementation of a transaction level assertion framework in SystemC.	DATE	2007	DBLP DOI BibTeX RDF
32	Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange	Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation.	DAC	2007	DBLP DOI BibTeX RDF
32	Namrata Shekhar, Priyank Kalla, Florian Enescu	Equivalence verification of arithmetic datapaths with multiple word-length operands.	DATE	2006	DBLP DOI BibTeX RDF
32	Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler	Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.	ICCD	2005	DBLP DOI BibTeX RDF
32	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
32	Prabhat Mishra 0001, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir	A Top-Down Methodology for Microprocessor Validation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
32	Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim	High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study.	DATE	2004	DBLP DOI BibTeX RDF
32	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	High-level test compaction techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	G. Surendra, S. K. Nandy 0001, Paul Sathya	ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications.	VLSI Design	2001	DBLP DOI BibTeX RDF
32	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
32	Toshiaki Tanaka, Tsutomu Kobayashi, Osamu Karatsu	HARP: FORTRAN to silicon [compilation system].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
31	Rajat Subhra Chakraborty, Swarup Bhunia	RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation.	VLSI Design	2010	DBLP DOI BibTeX RDF	resgister transfer level (RTL), Hardware Security, IP protection
31	Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara	BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
31	Joan Carletta, Christos A. Papachristou	Testability analysis and insertion for RTL circuits based on pseudorandom BIST.	ICCD	1995	DBLP DOI BibTeX RDF	pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
31	Stanislaw Deniziak, Mariusz Wisniewski	A symbolic RTL synthesis for LUT-based FPGAs.	DDECS	2009	DBLP DOI BibTeX RDF
31	Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara	Fast false path identification based on functional unsensitizability using RTL information.	ASP-DAC	2009	DBLP DOI BibTeX RDF
31	Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller	An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs.	ISQED	2009	DBLP DOI BibTeX RDF
31	Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham	Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL.	VLSI Design	2009	DBLP DOI BibTeX RDF
31	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	TBV, Model checking, fault models, functional verification, TLM
31	Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman	Power Conscious RTL Test Scheduling.	DSD	2008	DBLP DOI BibTeX RDF
31	Kypros Constantinides, Onur Mutlu, Todd M. Austin	Online design bug detection: RTL analysis, flexible mechanisms, and evaluation.	MICRO	2008	DBLP DOI BibTeX RDF
31	Dan Zhu, Tun Li, Yang Guo 0003, Sikun Li	2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions.	ISQED	2008	DBLP DOI BibTeX RDF	cutpoints, Program slicing, Sequential equivalence checking
31	Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham	Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Register Transfer Level implementation, Verification, Hardware Description Languages, arithmetic logic unit
31	Allan Crone, Gabriel Chidolue	Functional Verification of Low Power Designs at RTL.	PATMOS	2007	DBLP DOI BibTeX RDF	Low power aware management, Corruption, UPF, Simulation, Retention, PCF
31	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Incremental ABV for functional validation of TL-to-RTL design refinement.	DATE	2007	DBLP DOI BibTeX RDF
31	Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors.	ICCAD	2007	DBLP DOI BibTeX RDF
31	Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu	Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
31	Vyas Krishnan, Srinivas Katkoori	Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
31	Masahiro Fujita	Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	formal verification, High-level synthesis, equivalence checking, behavior synthesis
31	Masahiro Fujita	Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.	CHARME	2005	DBLP DOI BibTeX RDF
31	Enrico Macii	RTL power estimation and optimization.	SBCCI	2004	DBLP DOI BibTeX RDF
31	Sherif G. Aly 0001, Ashraf M. Salem	Observability-Based RTL Simulation using JAVA.	IWSOC	2004	DBLP DOI BibTeX RDF
31	Paul Flugger	RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.	PATMOS	2003	DBLP DOI BibTeX RDF
31	Dong Xiang, Shan Gu, Hideo Fujiwara	Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
31	Liang Zhang 0012, Michael S. Hsiao, Indradeep Ghosh	Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
31	Prabhat Mishra 0001, Arun Kejariwal, Nikil D. Dutt	Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
31	Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin	An Efficient Mechanism for Debugging RTL Description.	IWSOC	2003	DBLP DOI BibTeX RDF
31	Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii	Clock-tree power optimization based on RTL clock-gating.	DAC	2003	DBLP DOI BibTeX RDF	clock-tree synthsis, low-power design
31	Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai	Advanced techniques for RTL debugging.	DAC	2003	DBLP DOI BibTeX RDF	simulation, visualization, verification, debug, reasoning
31	Mehrdad Nourani, Christos A. Papachristou	False path exclusion in delay analysis of RTL structures.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
31	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka	A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits.	VTS	2002	DBLP DOI BibTeX RDF
31	Srivaths Ravi 0001, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha	Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
31	Harry Foster	Applied Boolean Equivalence Verification and RTL Static Sign-Off.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
31	Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu	An RTL design-space exploration method for high-level applications.	ASP-DAC	2001	DBLP DOI BibTeX RDF
31	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
31	Srivaths Ravi 0001, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana	A Technique for Identifying RTL and Gate-Level Correspondences.	ICCD	2000	DBLP DOI BibTeX RDF
31	Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu	Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.	VTS	2000	DBLP DOI BibTeX RDF
31	Christos A. Papachristou, Yusuf Alzazeri	A Method of Distributed Controller Design for RTL Circuits.	DATE	1999	DBLP DOI BibTeX RDF
31	Arvind Srinivasan 0004, Gary D. Huber, David P. LaPotin	Accurate area and delay estimation from RTL descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
31	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
31	Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
31	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Min Xu, Fadi J. Kurdahi	Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	FPGAs, high-level synthesis, floorplan, binding
31	Min Xu, Fadi J. Kurdahi	Layout-Driven RTL Binding Techniques for High-Level Synthesis.	ISSS	1996	DBLP DOI BibTeX RDF	layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process
31	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design for testability technique for RTL circuits using control/data flow extraction.	ICCAD	1996	DBLP DOI BibTeX RDF
30	Md. Imtiaz Rashid, Benjamin Carrion Schafer	MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR.	DATE	2023	DBLP DOI BibTeX RDF
30	Shogo Semba, Hiroshi Saito	RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones.	IEEE Access	2022	DBLP DOI BibTeX RDF
30	Xingyu Meng, Shamik Kundu, Arun K. Kanuparthi, Kanad Basu	RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
30		RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
30	Neiel Leyva, Alireza Monemi, Enrique Vallejo 0001	SynFull-RTL: Evaluation Methodology for RTL NoC Designs.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
30	Dian-Lun Lin, Haoxing Ren, Yanqing Zhang 0002, Brucek Khailany, Tsung-Wei Huang	From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus.	ICPP	2022	DBLP DOI BibTeX RDF
30	Rasheed Kibria, M. Sazadur Rahman, Farimah Farahmandi, Mark M. Tehranipoor	RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications.	ITC	2022	DBLP DOI BibTeX RDF
30	Guillem López-Paradís, Adrià Armejach, Miquel Moretó	gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator.	ICPP	2021	DBLP DOI BibTeX RDF
30	Shogo Semba, Hiroshi Saito	Conversion from Synchronous RTL Models to Asynchronous RTL Models.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2019	DBLP DOI BibTeX RDF
30	Tara Ghasempouri, Alessandro Danese, Graziano Pravadelli, Nicola Bombieri, Jaan Raik	RTL Assertion Mining with Automated RTL-to-TLM Abstraction.	FDL	2019	DBLP DOI BibTeX RDF
30	Tobias Strauch	Timing driven RTL-to-RTL partitioner for multi-FPGA systems.	FPL	2013	DBLP DOI BibTeX RDF
30	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
30	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco	Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.	MTV	2012	DBLP DOI BibTeX RDF
30	Nils Bulling, Berndt Farwer	Expressing Properties of Resource-Bounded Systems: The Logics RTL* and RTL.	CLIMA	2009	DBLP DOI BibTeX RDF