Search results for "SOI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
33	Ming Jin, Soi-Hoi Lam	A Virtual-Reality Based Integrated Driving-Traffic Simulation System to Study the Impacts of Intelligent Transportation Systems (ITS).	CW	2003	DBLP DOI BibTeX RDF
33	Inder Soi, Krishan Aggarwal	A review of computer-communication network classification schemes.	IEEE Commun. Mag.	1981	DBLP DOI BibTeX RDF
33	Yifei Luo, Gang Chen, Kuan Zhou	A picosecond TDC architecture for multiphase PLLs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc
33	Tak H. Ning	GLSVLSI 2008 invited/keynote talk.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	soi, cmos scaling
33	Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	64-bit Power Architecture, design dependency solution, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, multi-operating system, synergistic processor, real-time system, modularity, power management, Linux, multi-core, multi-threading, SOC, thermal management, design environment, CELL Processor, clock distribution, virtualization technology, SOI, correct-by-construction, re-use, design hierarchy
33	Paul Beckett	Low-power circuits using dynamic threshold devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate
33	Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang	Strained-si devices and circuits for low-power applications.	ISLPED	2003	DBLP DOI BibTeX RDF	band offset, strained-Si MOSFET, mobility, SOI, SiGe
33	Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie	Full Chip Thermal Simulation.	ISQED	2000	DBLP DOI BibTeX RDF	full chip, interconnect, SOI, thermal simulation
33	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
32	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
32	Wolfgang Theilmann, Ramin Yahyapour, Joe Butler	Multi-level SLA Management for Service-Oriented Infrastructures.	ServiceWave	2008	DBLP DOI BibTeX RDF	service-oriented infrastructure (SOI), adaptive infrastructures, manageability, service level agreement (SLA), non-functional properties, e-contracting
32	Stephen C. Terry, Mohammad M. Mojarradi, Benjamin J. Blalock, Jesse A. Richmond	Adaptive gate biasing: a new solution for body-driven current mirrors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SOI analog, body driving, current mirrors, ultra-low-voltage analog circuit design
27	Myoungsu Son, Juho Sung, Hyoung Won Baac, Changhwan Shin	Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET.	IEEE Access	2023	DBLP DOI BibTeX RDF
27	Hiroaki Satoh, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa	Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor.	Sensors	2023	DBLP DOI BibTeX RDF
27	Vimal Kumar Mishra, Rajeev K. Chauhan	Performance Analysis of Fully Depleted SOI Tapered Body Reduced Source (FD-SOI TBRS) MOSFET for Low Power Digital Applications.	FICTA (2)	2016	DBLP DOI BibTeX RDF
27	Xiao-liang Yang, Ying Wang 0041, Bin Du, Cheng-Hao Yu	Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
27	Wen-Teng Chang, Chun-Ming Lai, Wen-Kuan Yeh	Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
27	Liwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi 0001, Robert K. F. Teng	An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology.	ASICON	2013	DBLP DOI BibTeX RDF
27	Yong Woo Jeon, Dae Hyun Ka, Chong-Gun Yu, Won-Ju Cho, M. Saif Islam, Jong Tae Park 0003	NBTI and hot carrier effect of SOI p-MOSFETs fabricated in strained Si SOI wafer.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
27	Osamu Takahashi, Chad Adams, D. Ault, Erwin Behnen, O. Chiang, Scott R. Cottier, Paula K. Coulman, James Culp, Gilles Gervais, M. S. Gray, Y. Itaka, C. J. Johnson, Fumihiro Kono, L. Maurice, Kevin W. McCullen, Lam Nguyen, Y. Nishino, Hiromi Noro, Jürgen Pille, Mack W. Riley, M. Shen, Chiaki Takano, Shunsako Tokito, Tina Wagner, Hiroshi Yoshihara	Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI.	ISSCC	2008	DBLP DOI BibTeX RDF
27	Weimin Wu, Xin Li, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew, Ronald van Langevelde, Geert D. J. Smit, Andries J. Scholten, Dirk B. M. Klaassen, Josef Watts	PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs.	CICC	2007	DBLP DOI BibTeX RDF
27	Weimin Wu, Xin Li, Hailing Wang, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew	SP-SOI: a third generation surface potential based compact SOI MOSFET Model.	CICC	2005	DBLP DOI BibTeX RDF
27	David Axelrad	Application des technologies CMOS sur SOI aux fonctions d'interface des liens de communication haut débit (> 10 Gbit/s). (Application of CMOS on SOI technologies to high-speed Datacom interface functions (> 10Gbit/s)).		2005	RDF
27	Andrew Marshall, Sreedhar Natarajan	PD-SOI and FD-SOI: a comparison of circuit performance.	ICECS	2002	DBLP DOI BibTeX RDF
25	Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto	Symmetry constraint based on mismatch analysis for analog layout in SOI technology.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Devesh Nema, Thomas Toifl	Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Feng Liu, Jin He 0003, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang 0002, Mansun Chan	Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes.	ISQED	2008	DBLP DOI BibTeX RDF	double-gate MOSFET, drain current, compact model
25	Yu Zhou, Somnath Paul, Swarup Bhunia	Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.	ISQED	2008	DBLP DOI BibTeX RDF
25	Jennifer Blain Christen, Andreas G. Andreou	A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Eugenio Culurciello, Pujitha Weerakoon	Vertically-Integrated Three-Dimensional SOI Photodetectors.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Donghwi Kim, Ridha Kamoua, Milutin Stanacevic	Low-Power Low-Noise Neural Amplifier in 0.18µm FD-SOI Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski	A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.	ISQED	2007	DBLP DOI BibTeX RDF
25	Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.	ISQED	2007	DBLP DOI BibTeX RDF
25	Edward Choi, Andreas G. Andreou	Architecture of a µRFID with integrated antenna in 3D SOI-CMOS.	CISS	2007	DBLP DOI BibTeX RDF
25	Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa	High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI.	PATMOS	2006	DBLP DOI BibTeX RDF
25	Julius Georgiou, Andreas G. Andreou, Philippe O. Pouliquen	A mixed analog/digital asynchronous processor for cortical computations in 3D SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Francisco Tejada, Andreas G. Andreou, Philippe O. Pouliquen	Stacked, standing wave detectors in 3D SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Francisco Tejada, Andreas G. Andreou	Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Pablo Sergio Mandolesi, Pedro Julián, Andreas G. Andreou	A simplicial CNN visual processor in 3D SOI-CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Jin He 0003, Xing Zhang 0002, Ganggang Zhang, Yangyuan Wang	A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs.	ISQED	2006	DBLP DOI BibTeX RDF
25	Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
25	M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
25	John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath	Design of a 3-D fully depleted SOI computational RAM.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
25	Jinho Park, David J. Allstot	A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
25	Amaury Nève, Denis Flandre, Jean-Jacques Quisquater	SOI Technology for Future High-Performance Smart Cards.	IEEE Micro	2003	DBLP DOI BibTeX RDF
25	Rajiv V. Joshi, Ching-Te Chuang, Samuel K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi	PD/SOI SRAM performance in presence of gate-to-body tunneling current.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	Shaikh S. Ahmed, Dragica Vasileska	Modeling of Narrow-Width SOI Devices: The Role of Quantum Mechanical Narrow Channel Effects on Device Performance.	LSSC	2003	DBLP DOI BibTeX RDF
25	Olivier Thomas, Amara Amara	An SOI 4 transistors self-refresh ultra-low-voltage memory cell.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
25	Mamidala Jagadesh Kumar, D. Venkateshrao	A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design.	VLSI Design	2003	DBLP DOI BibTeX RDF
25	Yi-Chang, Edwin W. Greeneich	A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
25	Volker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau	0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology.	ISLPED	1998	DBLP DOI BibTeX RDF
25	Philip B. M. Wolbert, Gerhard K. M. Wachutka, Benno H. Krabbenborg, Ton J. Mouthaan	Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
23	Steven O. Kimbrough, Ann Kuo, Hoong Chuin Lau	Effective heuristic methods for finding non-optimal solutions of interest in constrained optimization models.	GECCO	2010	DBLP DOI BibTeX RDF	candle-lighting analysis, deliberation support, post-solution analysis, sensitivity analysis, constrained optimization
23	Brian D. Jeffs, Karl F. Warnick	Bias Corrected PSD Estimation for an Adaptive Array With Moving Interference.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
23	François Vincent, Olivier Besson, Cédric Richard	Matched Subspace Detection With Hypothesis Dependent Noise Power.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
23	Patcharee Basu, Achmad Husni Thamrin, Shoko Mikawa, Keiko Okawa, Jun Murai	Internet Technologies and Infrastructure for Asia-Wide Distance Education.	SAINT	2007	DBLP DOI BibTeX RDF
23	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
23	Zhaonian Zhang, Andreas G. Andreou	Design of An Ultra Wideband Transmitter in 0.18µm 3D Silicon on Insulator CMOS.	CISS	2007	DBLP DOI BibTeX RDF
23	Jae-Joon Kim, Kaushik Roy 0001	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
23	Jyi-Tsong Lin, Mike Chang	A New 1T DRAM Cell With Enhanced Floating Body Ef.	MTDT	2006	DBLP DOI BibTeX RDF
23	Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr	A method for generating structurally aligned grids for semiconductor device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Matteo Galli, Daniele Bajoni, M. Belotti, F. Paleari, Maddalena Patrini, Giorgio Guizzetti, Dario Gerace, M. Agio, Lucio C. Andreani, D. Peyrade, Y. Chen	Measurement of photonic mode dispersion and linewidths in silicon-on-insulator photonic crystal slabs.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
23	Jackson He, Mark Chang, Enrique Castro-Leon	Evolution of the Intel's e-Business Data Center toward a Service-Oriented Infrastructure.	ICEBE	2005	DBLP DOI BibTeX RDF
23	Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil	The G4-FET: a universal and programmable logic gate.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	G4-FET, programmable gate, universal logic gate, full adder
23	Lingyang Song, Alister G. Burr, Huiheng Mai	Multiple-symbol differential space-time OFDM over frequency-selective channels.	VTC Fall (2)	2004	DBLP DOI BibTeX RDF
23	Te-Hsin Huang, Ertan Zencir, Mehmet R. Yuce, Numan Sadi Dogan, Wentai Liu, Ercument Arvas	A 22-mW 435 MHz silicon on insulator CMOS high-gain LNA for subsampling receivers.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
23	Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
23	Kenneth L. Shepard, Dae-Jin Kim	Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology.	DAC	2000	DBLP DOI BibTeX RDF
23	Selim J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois	3D CMOS SOL for high performance computing.	ISLPED	1998	DBLP DOI BibTeX RDF
21	Paul Beckett, Heiko Rudolph	Run.	DELTA	2010	DBLP DOI BibTeX RDF	low power computer architecture, modeling, SOI, VHDL-AMS, double gate
20	Raúl Valín Ferreiro, Natalia Seoane, Manuel Aldegunde, Antonio J. García-Loureiro	The MOSFET Virtual Organisation: Grid Computing for Simulation in Nanoelectronics.	eScience	2009	DBLP DOI BibTeX RDF	DG-SOI MOSFET, EGI, NGI-es, Grid computing, Monte Carlo Simulation, Nanoelectronics
13	Christian Elgaard, Mustafa Özen, Eric Westesson, Ahmed Mahmoud, Florent Torres, Shakila Bint Reyaz, Therese Forsberg, Rehman Akbar, Hans Hagberg, Henrik Sjöland	Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Daniel Widmann, Tobias Tannert, Xuan-Quang Du, Thomas Veigel, Markus Grözing, Manfred Berroth	A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Christian Sbrana, Alessandro Catania, Maksym Paliy, Stefano Di Pascoli, Sebastiano Strangio, Massimo Macucci, Giuseppe Iannaccone	Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Tian Liang, Zhenyu Sun, Lintao Hu, Maoqi Zhu, Mingbo Zhang, Qinghua Liu, Jian Chen 0012, Deyong Chen, Yulan Lu, Junbo Wang 0002	Microelectrochemical Rotational Vibration Sensor With SOI-Based Microelectrodes Used for Seismic Monitoring.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
13	Bob Vanhoof, Wim Dehaene	A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	Jaehyun Kwon, Jaeyong Lee 0005, Taehun Kim, Donghwan Seo, Jinho Yoo, Jaeheon Cho, Changkun Park	Asymmetric SOI CMOS Switch With Series and Parallel Resonators to Enhance Isolation.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
13	Shuhao Fan, Qi Zhou, Ka-Meng Lei, Rui Paulo Martins, Pui-In Mak	17.2 A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm3 Resolution.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Loïck Le Guevel, Chen Wang, Joseph C. Bardin	29.1 A 22nm FD-SOI <1.2mW/Active-Qubit AWG-Free Cryo-CMOS Controller for Fluxonium Qubits.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Kaisarbek Omirzakhov, Firooz Aflatouni	12.1 Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Babak Hashemi, Sandro Rao, Maurizio Casalino, Francesco Giuseppe Della Corte	Design and Simulation of Single-Mode and Polarization Independent Deeply Etched Amorphous Silicon on SOI Waveguides.	PHOTOPTICS	2024	DBLP DOI BibTeX RDF
13	Indrajit Das, Hari Kishore Kakara, Vasudeva Reddy, Venkata Vanukuru	A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi using a 130 nm SOI CMOS Technology.	VLSID	2024	DBLP DOI BibTeX RDF
13	Panagiotis G. Zarkos, Sidney Buchbinder, Christos G. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanovic	Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Adrian Kneip, Martin Lefebvre 0002, Julien Verecken, David Bol	IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Shuhao Fan, Qi Zhou, Ka-Meng Lei, Pui-In Mak, Rui Paulo Martins	A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm3 Field of View.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Wonwoo Seo, Sunghyuk Kim, Byunghun Ko, Hee-Sauk Jhon, Jung-Hyun Kim 0005	High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Pierre Ferrer, François Rivet, Hervé Lapuyade, Yann Deval	A Walsh-Based Arbitrary Waveform Generator for 5G Applications in 28nm FD-SOI CMOS Technology.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Maisha Sadia, Partha Sarathi Paul 0002, Md Sakib Hasan	Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Adrian Kneip, David Bol	A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Lang Chen, Lisheng Chen, Zeyu Ge, Yichuang Sun, Xi Zhu 0001	A 40-GHz Load Modulated Balanced Power Amplifier Using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Mateus Bernardino Moreira, Francois Rivet, Magali De Matos, Hervé Lapuyade, Yann Deval	A (0.75-1.13) mW and (2.4-5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Enis Kobal, Teerachot Siriburanon, Robert Bogdan Staszewski, Anding Zhu	A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Ali Esmailiyan, Elena Blokhina, Dennis Andrade-Miceli, Eoin Faust, Panagiotis Giounanlis, Dirk Leipold, Hongying Wang, Imran Bashir, Eugene Koskin, Teerachot Siriburanon, Robert Bogdan Staszewski	An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Abhishek Ray, Alok Naugarhiya, Guru Prasad Mishra	Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Lijuan Wu, Tao Qiu, Xuanting Song, Banghui Zhang, Heng Liu, Qing Liu	Analytical model for high-k SOI pLDMOS with self-adaptive balance of polarization charge.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Sasi Kiran Suddarsi, K. J. Dhanaraj, Gopi Krishna Saramekala	Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re-S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET).	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Zhigang Li, David Cordeau, Jean-Marie Paillot, Sébastien Charpentier, Matthieu Lécuyer, Francis Huin	Analysis and design of K-band low-phase-noise differential DCOs implemented in 22 nm FD-SOI for 76-81 GHz automotive radars.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy	A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.	CoRR	2023	DBLP DOI BibTeX RDF
13	Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr 0001, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich	A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.	CoRR	2023	DBLP DOI BibTeX RDF