Search results for "SPARC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche	Partial triplication of a SPARC-V8 microprocessor using fault injection.	LASCAS	2015	DBLP DOI BibTeX RDF
21	Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister	4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.	ISSCC	2015	DBLP DOI BibTeX RDF
21	Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang	4.3 Fine-grained adaptive power management of the SPARC M7 processor.	ISSCC	2015	DBLP DOI BibTeX RDF
21	Emmanuel Senft, Paul Baxter 0001, James Kennedy 0001, Tony Belpaeme	SPARC: Supervised Progressively Autonomous Robot Competencies.	ICSR	2015	DBLP DOI BibTeX RDF
21	Chen Zhao, Kuizhi Mei, Fei Wang 0008, Nanning Zheng 0001	A high-efficient floating point coprocessor for SPARC Leon2 embedded processor.	ASICON	2015	DBLP DOI BibTeX RDF
21	Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen	A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
21	Ram Sivaramakrishnan, Sumti Jairath	Next generation SPARC processor cache hierarchy.	Hot Chips Symposium	2014	DBLP DOI BibTeX RDF
21	Stephen Phillips	M7: Next generation SPARC.	Hot Chips Symposium	2014	DBLP DOI BibTeX RDF
21	Xue Yang, Lixin Yu, Yunkai Feng	Design of SPARC V8 superscalar pipeline applied Tomasulo's algorithm.	ICDIP	2014	DBLP DOI BibTeX RDF
21	Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin	Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor.	A-SSCC	2014	DBLP DOI BibTeX RDF
21	Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith 0002, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister	The Next Generation 64b SPARC Core in a T4 SoC Processor.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
21	John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa	The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets.	IEEE Micro	2013	DBLP DOI BibTeX RDF
21	Evgenii Balai, Michael Gelfond, Yuanlin Zhang 0002	SPARC - Sorted ASP with Consistency Restoring Rules	CoRR	2013	DBLP BibTeX RDF
21	Ali Vahidsafa, Sutikshan Bhutani	SPARC M6 Oracle's next generation processor for enterprise systems.	Hot Chips Symposium	2013	DBLP DOI BibTeX RDF
21	Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen	3.6GHz 16-core SPARC SoC processor in 28nm.	ISSCC	2013	DBLP DOI BibTeX RDF
21	Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin	Bandwidth and power management of glueless 8-socket SPARC T5 system.	ISSCC	2013	DBLP DOI BibTeX RDF
21	Manish Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja	Sparc T4: A Dynamically Threaded Server-on-a-Chip.	IEEE Micro	2012	DBLP DOI BibTeX RDF
21	Sebastian Turullols, Ram Sivaramakrishnan	SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets.	Hot Chips Symposium	2012	DBLP DOI BibTeX RDF
21	Alexander Korobkov	Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs).	ISPD	2012	DBLP DOI BibTeX RDF
21	Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith 0002, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister	The next-generation 64b SPARC core in a T4 SoC processor.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Xijun Wang 0001, Wei Chen 0002, Zhigang Cao 0001	SPARC: Superposition-Aided Rateless Coding in Wireless Relay Systems.	IEEE Trans. Veh. Technol.	2011	DBLP DOI BibTeX RDF
21	Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway W. Tam, Alan P. Smith 0002, Ha Pham, Hongping Penny Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong	A 40 nm 16-Core 128-Thread SPARC SoC Processor.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
21	Michiel W. van Tol	A Characterization of the SPARC T3-4 System	CoRR	2011	DBLP BibTeX RDF
21	Mikhail I. Gofman, Ruiqi Luo, Ping Yang 0002, Kartik Gopalan	SPARC: a security and privacy aware virtual machinecheckpointing mechanism.	WPES	2011	DBLP DOI BibTeX RDF
21	Peng Liu, Lixin Yu, Qin Hui	An Improved On-chip Debug Architecture for SPARC Processor based on Shadow Scan Technique.	PECCS	2011	DBLP BibTeX RDF
21	Annemie Ribbens, Jeroen Hermans, Frederik Maes, Dirk Vandermeulen, Paul Suetens	SPARC: unified framework for automatic segmentation, probabilistic atlas construction, registration and clustering of brain MR images.	ISBI	2010	DBLP DOI BibTeX RDF
21	Chao Wang 0077, Zhongchuan Fu, Hongsong Chen, Wei Ba, Bin Li, Lin Chen, Zexu Zhang, Yuying Wang, Gang Cui	CFCSS without Aliasing for SPARC Architecture.	CIT	2010	DBLP DOI BibTeX RDF	CFCSS(Control Flow Checking by Software Signatures), COTS(Commercial-Off-The-Shelf), multi-core, Aliasing, transient fault
21	Jinuk Luke Shin, Kenway W. Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Penny Li, Alan P. Smith 0002, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong	A 40nm 16-core 128-thread CMT SPARC SoC processor.	ISSCC	2010	DBLP DOI BibTeX RDF
21	Michael Hofstätter, Peter Schön, Christoph Posch	A SPARC-compatible general purpose address-event processor with 20-bit l0ns-resolution asynchronous sensor data interface in 0.18μm CMOS.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar	Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
21	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Rock: A High-Performance Sparc CMT Processor.	IEEE Micro	2009	DBLP DOI BibTeX RDF
21	Sandro Penolazzi, Luca Bolognino, Ahmed Hemani	Energy and Performance Model of a SPARC Leon3 Processor.	DSD	2009	DBLP DOI BibTeX RDF
21	Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo Candido Xavier, Ricardo Pannain, Paulo Centoducatte, Rodolfo Jardim de Azevedo	SPARC16: A New Compression Approach for the SPARC Architecture.	SBAC-PAD	2009	DBLP DOI BibTeX RDF
21	Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, David Greenhill	Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
21	Chimène Fankam, Stéphane Jean, Guy Pierra, Ladjel Bellatreche	Extension de l'architecture de bases de données ANSI/SPARC pour expliciter la sémantique des données.	CAL	2008	DBLP BibTeX RDF
21	Marc Tremblay, Shailender Chaudhry	A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor.	ISSCC	2008	DBLP DOI BibTeX RDF
21	Anjali Vij, Richard Ratliff	Implementation Update: Logic Mapping On SPARC- Microprocessors.	ITC	2008	DBLP DOI BibTeX RDF
21	Daniel Chen 0001, Gabriela Jacques-Silva, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Bruce G. Mealey	Error Behavior Comparison of Multiple Computing Systems: A Case Study Using Linux on Pentium, Solaris on SPARC, and AIX on POWER.	PRDC	2008	DBLP DOI BibTeX RDF
21	Ana Sonia Leon, Kenway W. Tam, Jinuk Luke Shin, David Weisner, Francis Schumacher	A Power-Efficient High-Throughput 32-Thread SPARC Processor.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Pierre Guironnet de Massas, Paul Amblard, Frédéric Pétrot	On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	José A. Martínez-Lozano, Víctor Estellés, Francisco Molero, José Luis Gómez-Amo, María Pilar Utrillas, Manuel Pujadas, Juan Carlos Fortea, Luis Guanter	Atmospheric Components Determination From Ground-Level Measurements During the Spectra Barax Campaigns (SPARC) Field Campaigns.	IEEE Trans. Geosci. Remote. Sens.	2007	DBLP DOI BibTeX RDF
21	Timothy Johnson, Umesh Nawathe	An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2).	ISPD	2007	DBLP DOI BibTeX RDF
21	David W. Yen	Chip Multi-Threading and the SPARC Evolution.	APPT	2007	DBLP DOI BibTeX RDF
21	Umesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King C. Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park	An 8-Core 64-Thread 64b Power-Efficient SPARC SoC.	ISSCC	2007	DBLP DOI BibTeX RDF
21	Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh	Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip.	ITC	2007	DBLP DOI BibTeX RDF
21	Jason M. Hart, Kyung T. Lee, Dennis Chen, Lik Cheng, Chipai Chou, Anand Dixit, Dale Greenley, Gregory Gruber, Kenneth Ho, Jesse Hsu, Naveen G. Malur, John Wu	Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
21	Ana Sonia Leon, Jinuk Luke Shin, Kenway W. Tam, William Bryg, Francis Schumacher, Poonacha Kongetira, David Weisner, Allan Strong	A Power-Efficient High-Throughput 32-Thread SPARC Processor.	ISSCC	2006	DBLP DOI BibTeX RDF
21	Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun	Niagara: A 32-Way Multithreaded Sparc Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, Shared memory, Multithreaded processors
21	Luis Guanter, Luis Alonso 0002, José F. Moreno	A method for the surface reflectance retrieval from PROBA/CHRIS data over land: application to ESA SPARC campaigns.	IEEE Trans. Geosci. Remote. Sens.	2005	DBLP DOI BibTeX RDF
21	Bill Clarke, Adam Czezowski, Peter E. Strazdins	Implemention Aspects of a SPARC V9 Complete Machine Simulator.	ACSC	2002	DBLP BibTeX RDF
21	Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You	A third-generation SPARC V9 64-b microprocessor.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
21	Richard K. Johnson	A Question of Access: SPARC, BioOne, and Society-Driven Electronic Publishing.	D Lib Mag.	2000	DBLP DOI BibTeX RDF
21	Thomas Handschuch	Solaris 7 Systemadministration - Management von Workstation und Server mit Solaris 2 und Solaris 7 auf SPARC und Intel (2. Aufl.).		1999	RDF
21	Tomás Bautista, Antonio Núñez	Flexible design of SPARC cores: a quantitative study.	CODES	1999	DBLP DOI BibTeX RDF
21	R. B. Reese	EDA on Unix/Sparc and Win95/Intel platforms: does compatibility exist?	MSE	1997	DBLP DOI BibTeX RDF
21	Val Popescu, Bill McNamara	Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor.	DAC	1996	DBLP DOI BibTeX RDF
21	António de Brito Ferrari	Sparc® architecture, assembly language programming, & C : Richard P Paul Prentice-Hall Inc, Englewood Cliffs, NJ, USA (1994) ISBN 0 13 876889 7, £34.75, 448 pp.	Microprocess. Microsystems	1995	DBLP DOI BibTeX RDF
21	Dale Greenley, J. Bauman, D. Chang, Dennis Chen, R. Eltejaein, Philip A. Ferolito, P. Fu, Robert B. Garner, D. Greenhill, H. Grewal, Kalon Holdbrook, B. Kim, Leslie Kohn, Hang Kwan, M. Levitt, Guillermo Maturana, D. Mrazek, Chitresh Narasimhaiah, Kevin Normoyle, N. Parveen, P. Patel, A. Prabhu, Marc Tremblay, Michelle Wong, L. Yang, Krishna Yarlagadda, Robert K. Yu, Robert Yung, Gregory B. Zyner	UltraSPARC: The Next Generation Superscalar 64-bit SPARC.	COMPCON	1995	DBLP DOI BibTeX RDF
21	David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk	HALSIM - A Very Fast SPARC-V9 Behavioral Model.	MASCOTS	1995	DBLP DOI BibTeX RDF
21	David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk	HALSIM - a very fast SPARC V9 behavioral model.	SIGARCH Comput. Archit. News	1994	DBLP DOI BibTeX RDF
21	Vasilij M. Suvorov	Vergleichende Untersuchungen zu RISC-Prozessoren am Beispiel MIPS und SPARC.		1994	RDF
21	William F. Keown Jr., Philip J. Koopman Jr., Aaron Collins	Performance of the HARRIS RTX 2000 Stack Architecture versus the Sun 4 SPARC and the Sun 3 M68020 Architectures.	SIGARCH Comput. Archit. News	1992	DBLP DOI BibTeX RDF
21	William F. Keown Jr., Philip J. Koopman Jr., Aaron Collins	Real-Time Performance of the HARRIS RTX 2000 Stack Architecture Versus the Sun 4 SPARC and the Sun 3 M68020 Architectures With a Proposed Real-Time Performance BenchMark.	SIGMETRICS Perform. Evaluation Rev.	1992	DBLP DOI BibTeX RDF
21	Anant Agrawal, Robert B. Garner	SPARC: A scalable processor architecture.	Future Gener. Comput. Syst.	1992	DBLP DOI BibTeX RDF
21	Gabriel P. Silva, Júlio S. Aude	Evaluation of a sparc architecture with harvard bus and branch target cache.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
21		SPARC architecture manual - version 8.		1992	RDF
21	Olaf S. Schoepke	Using the Entropy in the SPARC Instruction Set.	ICCI	1992	DBLP BibTeX RDF
21	Josef Templ	Design and Implementation of SPARC-Oberon.	Struct. Program.	1991	DBLP BibTeX RDF
21	Paul Afshar	Trends in building a SPARC compatible system: a case study in methods and tools.	Compcon	1991	DBLP DOI BibTeX RDF
21	Tom Lacey	Put a SPARC into your PC.	Compcon	1991	DBLP DOI BibTeX RDF
21	Robert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly	An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC
21	Roland L. Lee, Alex Y. Kwok, Faye A. Briggs	The Floating-Point Performance of a Superscalar SPARC Processor.	ASPLOS	1991	DBLP DOI BibTeX RDF
21	Merrick Darley, Bill Kronlage, Dvaid Bural, Bob Churchill, David Pulling, Paul Wang, Rick Iwamoto, Larry Yang	The TMS390C602A floating-point coprocessor for Sparc systems.	IEEE Micro	1990	DBLP DOI BibTeX RDF
21	Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino	Implementing Sparc in ECL.	IEEE Micro	1990	DBLP DOI BibTeX RDF
21	Mark Birman, Allen Samuels, George Chu, Ting Chuk, Larry Hu, John McLeod, John Barnes	Developing the WTL3170/3171 Sparc floating-point coprocessors.	IEEE Micro	1990	DBLP DOI BibTeX RDF
21	S. M. Hitchcock	SPARC: architecture to implementations.	Microprocess. Microsystems	1990	DBLP DOI BibTeX RDF
21	Larry Press	The Toshiba T1000, IBM's Academic Computing Conference and SPARC PSs.	Commun. ACM	1989	DBLP BibTeX RDF
21	Anant Agrawal, Eric W. Brown 0002, Joe Petolino, James R. Peterson	Design Considerations for a Bipolar Implementation of SPARC.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Steve R. Kleiman, Dock Williams	SunOS on SPARC.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Masood Namjoo, Anant Agrawal, D. C. Jackson, Lesley Quach	CMOS Gate Array Implementation of the SPARC Architecture.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Steven S. Muchnick, C. Aoki, V. Ghodsi, M. Helft, M. Lee, Richard Tuck, D. Weaver, A. Wu	Optimizing Compilers for the SPARC Architecture: An Overview.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Masood Namjoo, F. Abu-Nofal, Doug Carmean, R. Chandramouli, Y. Chang, J. Goforth, W. Hsu, Rick Iwamoto, C. Murphy, U. Naot, Mike Parkin, Joan M. Pendleton, C. Porter, J. Reaves, R. Reddy, George Swan, D. Tinker, P. Tong, Larry Yang	CMOS Custom Implementation of the SPARC Architecture.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Robert B. Garner, Anant Agrawal, Faye A. Briggs, Eric W. Brown 0002, David Hough 0001, Bill Joy 0001, Steve R. Kleiman, Steven S. Muchnick, Masood Namjoo, David A. Patterson 0001, Joan M. Pendleton, Richard Tuck	The Scalable Processor Architecture (SPARC).	COMPCON	1988	DBLP DOI BibTeX RDF
21	L. Quach, R. Chueh	CMOS Gate Array Implementation of SPARC.	COMPCON	1988	DBLP DOI BibTeX RDF
21	Masood Namjoo	First 32-bit SPARC-based processors implemented in high-speed CMOS.	ICCD	1988	DBLP DOI BibTeX RDF
21		X3/SPARC Database Systems Study Group Solicits Members	SIGMOD Rec.	1987	DBLP BibTeX RDF
21	Thomas Burns, Elizabeth N. Fong, David Jefferson, Richard Knox, Leo Mark, Christopher Reedy, Louis Reich, Nick Roussopoulos, Walter Truszkowski	Reference Model for DBMS Standardization, Database Architecture Framework Task Group (DAFTG) of the ANSI/X3/SPARC Database System Study Group.	SIGMOD Rec.	1986	DBLP BibTeX RDF
21	Eric K. Clemons	Data Models and the ANSI/SPARC Architecture.	Principles of Database Design (I)	1985	DBLP BibTeX RDF
21	Michael L. Brodie, Joachim W. Schmidt	Final Report of the ANSI/X3/SPARC DBS-SG Relational Database Task Group.	SIGMOD Rec.	1982	DBLP DOI BibTeX RDF
21	Sudhir K. Arora, Surya R. Dumpala	Data Base Facilities in an ANSI SPARC Data Base Machine.	COMPCON	1982	DBLP BibTeX RDF
21	Asuman Dogac, Peter P. Chen	Entity-Relationship Model in the ANSI/SPARC Framework.	ER	1981	DBLP BibTeX RDF
21	Sudhir K. Arora, Surya R. Dumpala, Kenneth C. Smith	WCRC: An ANSI SPARC Machine Architecture for Data Base Management.	ISCA	1981	DBLP BibTeX RDF
21	Eric K. Clemons	Design of a prototype ANSI/SPARC three-schema data base system.	MARK	1979	DBLP DOI BibTeX RDF
21	Dennis Tsichritzis, Anthony C. Klug	The ANSI/X3/SPARC DBMS Framework Report of the Study Group on Dabatase Management Systems.	Inf. Syst.	1978	DBLP DOI BibTeX RDF
21	Frank Manola	On Relating the CODASYL Database Languages and the ANSI/SPARC Framework.	VLDB	1978	DBLP BibTeX RDF
21	Anthony C. Klug, Dennis Tsichritzis	Multiple View Support within the ANSI/SPARC Framework.	VLDB	1977	DBLP BibTeX RDF
21	Michael E. Senko	DIAM as a Detailed Example of the ANSI SPARC Architecture.	IFIP Working Conference on Modelling in Data Base Management Systems	1976	DBLP BibTeX RDF
21		Interim Report: ANSI/X3/SPARC Study Group on Data Base Management Systems 75-02-08	FDT Bull. ACM SIGFIDET SIGMOD	1975	DBLP BibTeX RDF
21	Charles W. Bachman	Summary of Current Work - ANSI/X3/SPARC/Study Group - Database Systems.	FDT Bull. ACM SIGFIDET SIGMOD	1974	DBLP DOI BibTeX RDF
21	Millard H. Perstein	Report to SPARC (the standards planning and requirements committee of ANSI) from the ad hoc committee on operating system control languages.	ACM SIGAPL APL Quote Quad	1971	DBLP DOI BibTeX RDF